1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/Target/MRegisterInfo.h"
20 #include "Support/Annotation.h"
21 #include "Support/iterator"
27 class MachineBasicBlock;
31 typedef int MachineOpCode;
33 //===----------------------------------------------------------------------===//
34 /// Special flags on instructions that modify the opcode.
35 /// These flags are unused for now, but having them enforces that some
36 /// changes will be needed if they are used.
38 enum MachineOpCodeFlags {
39 AnnulFlag, /// 1 if annul bit is set on a branch
40 PredTakenFlag, /// 1 if branch should be predicted taken
41 PredNotTakenFlag /// 1 if branch should be predicted not taken
44 //===----------------------------------------------------------------------===//
45 /// MOTy - MachineOperandType - This namespace contains an enum that describes
46 /// how the machine operand is used by the instruction: is it read, defined, or
47 /// both? Note that the MachineInstr/Operator class currently uses bool
48 /// arguments to represent this information instead of an enum. Eventually this
49 /// should change over to use this _easier to read_ representation instead.
53 Use, /// This machine operand is only read by the instruction
54 Def, /// This machine operand is only written by the instruction
55 UseAndDef /// This machine operand is read AND written
59 //===----------------------------------------------------------------------===//
60 // class MachineOperand
63 // Representation of each machine instruction operand.
64 // This class is designed so that you can allocate a vector of operands
65 // first and initialize each one later.
67 // E.g, for this VM instruction:
68 // ptr = alloca type, numElements
69 // we generate 2 machine instructions on the SPARC:
71 // mul Constant, Numelements -> Reg
72 // add %sp, Reg -> Ptr
74 // Each instruction has 3 operands, listed above. Of those:
75 // - Reg, NumElements, and Ptr are of operand type MO_Register.
76 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
78 // For the register operands, the virtual register type is as follows:
80 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
81 // MachineInstr* minstr will point to the instruction that computes reg.
83 // - %sp will be of virtual register type MO_MachineReg.
84 // The field regNum identifies the machine register.
86 // - NumElements will be of virtual register type MO_VirtualReg.
87 // The field Value* value identifies the value.
89 // - Ptr will also be of virtual register type MO_VirtualReg.
90 // Again, the field Value* value identifies the value.
92 //===----------------------------------------------------------------------===//
94 struct MachineOperand {
95 enum MachineOperandType {
96 MO_VirtualRegister, // virtual register for *value
97 MO_MachineRegister, // pre-assigned machine register `regNum'
102 MO_MachineBasicBlock, // MachineBasicBlock reference
103 MO_FrameIndex, // Abstract Stack Frame Index
104 MO_ConstantPoolIndex, // Address of indexed Constant in Constant Pool
105 MO_ExternalSymbol, // Name of external global symbol
106 MO_GlobalAddress, // Address of a global value
110 // Bit fields of the flags variable used for different operand properties
112 DEFONLYFLAG = 0x01, // this is a def but not a use of the operand
113 DEFUSEFLAG = 0x02, // this is both a def and a use
114 HIFLAG32 = 0x04, // operand is %hi32(value_or_immedVal)
115 LOFLAG32 = 0x08, // operand is %lo32(value_or_immedVal)
116 HIFLAG64 = 0x10, // operand is %hi64(value_or_immedVal)
117 LOFLAG64 = 0x20, // operand is %lo64(value_or_immedVal)
118 PCRELATIVE = 0x40, // Operand is relative to PC, not a global address
125 Value* value; // BasicBlockVal for a label operand.
126 // ConstantVal for a non-address immediate.
127 // Virtual register for an SSA operand,
128 // including hidden operands required for
129 // the generated machine code.
130 // LLVM global for MO_GlobalAddress.
132 int64_t immedVal; // Constant value for an explicit constant
134 MachineBasicBlock *MBB; // For MO_MachineBasicBlock type
135 std::string *SymbolName; // For MO_ExternalSymbol type
138 char flags; // see bit field definitions above
139 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
140 int regNum; // register number for an explicit register
141 // will be set for a value after reg allocation
146 opType(MO_VirtualRegister),
149 MachineOperand(int64_t ImmVal, MachineOperandType OpTy)
155 MachineOperand(int Reg, MachineOperandType OpTy, MOTy::UseType UseTy)
160 case MOTy::Use: flags = 0; break;
161 case MOTy::Def: flags = DEFONLYFLAG; break;
162 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
163 default: assert(0 && "Invalid value for UseTy!");
167 MachineOperand(Value *V, MachineOperandType OpTy, MOTy::UseType UseTy,
168 bool isPCRelative = false)
169 : value(V), opType(OpTy), regNum(-1) {
171 case MOTy::Use: flags = 0; break;
172 case MOTy::Def: flags = DEFONLYFLAG; break;
173 case MOTy::UseAndDef: flags = DEFUSEFLAG; break;
174 default: assert(0 && "Invalid value for UseTy!");
176 if (isPCRelative) flags |= PCRELATIVE;
179 MachineOperand(MachineBasicBlock *mbb)
180 : MBB(mbb), flags(0), opType(MO_MachineBasicBlock), regNum(-1) {}
182 MachineOperand(const std::string &SymName, bool isPCRelative)
183 : SymbolName(new std::string(SymName)), flags(isPCRelative ? PCRELATIVE :0),
184 opType(MO_ExternalSymbol), regNum(-1) {}
187 MachineOperand(const MachineOperand &M) : immedVal(M.immedVal),
191 if (isExternalSymbol())
192 SymbolName = new std::string(M.getSymbolName());
196 if (isExternalSymbol())
200 const MachineOperand &operator=(const MachineOperand &MO) {
201 if (isExternalSymbol()) // if old operand had a symbol name,
202 delete SymbolName; // release old memory
203 immedVal = MO.immedVal;
207 if (isExternalSymbol())
208 SymbolName = new std::string(MO.getSymbolName());
212 // Accessor methods. Caller is responsible for checking the
213 // operand type before invoking the corresponding accessor.
215 MachineOperandType getType() const { return opType; }
217 /// isPCRelative - This returns the value of the PCRELATIVE flag, which
218 /// indicates whether this operand should be emitted as a PC relative value
219 /// instead of a global address. This is used for operands of the forms:
220 /// MachineBasicBlock, GlobalAddress, ExternalSymbol
222 bool isPCRelative() const { return (flags & PCRELATIVE) != 0; }
225 // This is to finally stop caring whether we have a virtual or machine
226 // register -- an easier interface is to simply call both virtual and machine
227 // registers essentially the same, yet be able to distinguish when
228 // necessary. Thus the instruction selector can just add registers without
229 // abandon, and the register allocator won't be confused.
230 bool isVirtualRegister() const {
231 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
232 && regNum >= MRegisterInfo::FirstVirtualRegister;
234 bool isPhysicalRegister() const {
235 return (opType == MO_VirtualRegister || opType == MO_MachineRegister)
236 && (unsigned)regNum < MRegisterInfo::FirstVirtualRegister;
238 bool isRegister() const { return isVirtualRegister() || isPhysicalRegister();}
239 bool isMachineRegister() const { return !isVirtualRegister(); }
240 bool isMachineBasicBlock() const { return opType == MO_MachineBasicBlock; }
241 bool isPCRelativeDisp() const { return opType == MO_PCRelativeDisp; }
242 bool isImmediate() const {
243 return opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed;
245 bool isFrameIndex() const { return opType == MO_FrameIndex; }
246 bool isConstantPoolIndex() const { return opType == MO_ConstantPoolIndex; }
247 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
248 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
250 Value* getVRegValue() const {
251 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
255 Value* getVRegValueOrNull() const {
256 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
257 isPCRelativeDisp()) ? value : NULL;
259 int getMachineRegNum() const {
260 assert(opType == MO_MachineRegister);
263 int64_t getImmedValue() const { assert(isImmediate()); return immedVal; }
264 void setImmedValue(int64_t ImmVal) { assert(isImmediate()); immedVal=ImmVal; }
266 MachineBasicBlock *getMachineBasicBlock() const {
267 assert(isMachineBasicBlock() && "Can't get MBB in non-MBB operand!");
270 int getFrameIndex() const { assert(isFrameIndex()); return immedVal; }
271 unsigned getConstantPoolIndex() const {
272 assert(isConstantPoolIndex());
276 GlobalValue *getGlobal() const {
277 assert(isGlobalAddress());
278 return (GlobalValue*)value;
281 const std::string &getSymbolName() const {
282 assert(isExternalSymbol());
286 bool opIsUse () const { return (flags & USEDEFMASK) == 0; }
287 bool opIsDefOnly () const { return flags & DEFONLYFLAG; }
288 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
289 bool opHiBits32 () const { return flags & HIFLAG32; }
290 bool opLoBits32 () const { return flags & LOFLAG32; }
291 bool opHiBits64 () const { return flags & HIFLAG64; }
292 bool opLoBits64 () const { return flags & LOFLAG64; }
294 // used to check if a machine register has been allocated to this operand
295 bool hasAllocatedReg() const {
296 return (regNum >= 0 &&
297 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
298 opType == MO_MachineRegister));
301 // used to get the reg number if when one is allocated
302 int getAllocatedRegNum() const {
303 assert(hasAllocatedReg());
307 // ********** TODO: get rid of this duplicate code! ***********
308 unsigned getReg() const {
309 return getAllocatedRegNum();
311 void setReg(unsigned Reg) {
312 assert(hasAllocatedReg() && "This operand cannot have a register number!");
316 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
320 // Construction methods needed for fine-grain control.
321 // These must be accessed via coresponding methods in MachineInstr.
322 void markHi32() { flags |= HIFLAG32; }
323 void markLo32() { flags |= LOFLAG32; }
324 void markHi64() { flags |= HIFLAG64; }
325 void markLo64() { flags |= LOFLAG64; }
327 // Replaces the Value with its corresponding physical register after
328 // register allocation is complete
329 void setRegForValue(int reg) {
330 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
331 opType == MO_MachineRegister);
335 friend class MachineInstr;
339 //===----------------------------------------------------------------------===//
340 // class MachineInstr
343 // Representation of each machine instruction.
345 // MachineOpCode must be an enum, defined separately for each target.
346 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
348 // There are 2 kinds of operands:
350 // (1) Explicit operands of the machine instruction in vector operands[]
352 // (2) "Implicit operands" are values implicitly used or defined by the
353 // machine instruction, such as arguments to a CALL, return value of
354 // a CALL (if any), and return value of a RETURN.
355 //===----------------------------------------------------------------------===//
358 int opCode; // the opcode
359 unsigned opCodeFlags; // flags modifying instrn behavior
360 std::vector<MachineOperand> operands; // the operands
361 unsigned numImplicitRefs; // number of implicit operands
363 // OperandComplete - Return true if it's illegal to add a new operand
364 bool OperandsComplete() const;
366 MachineInstr(const MachineInstr &); // DO NOT IMPLEMENT
367 void operator=(const MachineInstr&); // DO NOT IMPLEMENT
369 MachineInstr(int Opcode, unsigned numOperands);
371 /// MachineInstr ctor - This constructor only does a _reserve_ of the
372 /// operands, not a resize for them. It is expected that if you use this that
373 /// you call add* methods below to fill up the operands, instead of the Set
374 /// methods. Eventually, the "resizing" ctors will be phased out.
376 MachineInstr(int Opcode, unsigned numOperands, bool XX, bool YY);
378 /// MachineInstr ctor - Work exactly the same as the ctor above, except that
379 /// the MachineInstr is created and added to the end of the specified basic
382 MachineInstr(MachineBasicBlock *MBB, int Opcode, unsigned numOps);
387 const int getOpcode() const { return opCode; }
388 const int getOpCode() const { return opCode; }
392 unsigned getOpCodeFlags() const { return opCodeFlags; }
395 // Access to explicit operands of the instruction
397 unsigned getNumOperands() const { return operands.size() - numImplicitRefs; }
399 const MachineOperand& getOperand(unsigned i) const {
400 assert(i < getNumOperands() && "getOperand() out of range!");
403 MachineOperand& getOperand(unsigned i) {
404 assert(i < getNumOperands() && "getOperand() out of range!");
409 // Access to explicit or implicit operands of the instruction
410 // This returns the i'th entry in the operand vector.
411 // That represents the i'th explicit operand or the (i-N)'th implicit operand,
412 // depending on whether i < N or i >= N.
414 const MachineOperand& getExplOrImplOperand(unsigned i) const {
415 assert(i < operands.size() && "getExplOrImplOperand() out of range!");
416 return (i < getNumOperands()? getOperand(i)
417 : getImplicitOp(i - getNumOperands()));
421 // Access to implicit operands of the instruction
423 unsigned getNumImplicitRefs() const{ return numImplicitRefs; }
425 MachineOperand& getImplicitOp(unsigned i) {
426 assert(i < numImplicitRefs && "implicit ref# out of range!");
427 return operands[i + operands.size() - numImplicitRefs];
429 const MachineOperand& getImplicitOp(unsigned i) const {
430 assert(i < numImplicitRefs && "implicit ref# out of range!");
431 return operands[i + operands.size() - numImplicitRefs];
434 Value* getImplicitRef(unsigned i) {
435 return getImplicitOp(i).getVRegValue();
437 const Value* getImplicitRef(unsigned i) const {
438 return getImplicitOp(i).getVRegValue();
441 void addImplicitRef(Value* V, bool isDef = false, bool isDefAndUse = false) {
443 addRegOperand(V, isDef, isDefAndUse);
445 void setImplicitRef(unsigned i, Value* V) {
446 assert(i < getNumImplicitRefs() && "setImplicitRef() out of range!");
447 SetMachineOperandVal(i + getNumOperands(),
448 MachineOperand::MO_VirtualRegister, V);
454 void print(std::ostream &OS, const TargetMachine &TM) const;
456 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
459 // Define iterators to access the Value operands of the Machine Instruction.
460 // Note that these iterators only enumerate the explicit operands.
461 // begin() and end() are defined to produce these iterators...
463 template<class _MI, class _V> class ValOpIterator;
464 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
465 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
468 //===--------------------------------------------------------------------===//
469 // Accessors to add operands when building up machine instructions
472 /// addRegOperand - Add a MO_VirtualRegister operand to the end of the
475 void addRegOperand(Value *V, bool isDef, bool isDefAndUse=false) {
476 assert(!OperandsComplete() &&
477 "Trying to add an operand to a machine instr that is already done!");
478 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
479 !isDef ? MOTy::Use : (isDefAndUse ? MOTy::UseAndDef : MOTy::Def)));
482 void addRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use,
483 bool isPCRelative = false) {
484 assert(!OperandsComplete() &&
485 "Trying to add an operand to a machine instr that is already done!");
486 operands.push_back(MachineOperand(V, MachineOperand::MO_VirtualRegister,
490 void addCCRegOperand(Value *V, MOTy::UseType UTy = MOTy::Use) {
491 assert(!OperandsComplete() &&
492 "Trying to add an operand to a machine instr that is already done!");
493 operands.push_back(MachineOperand(V, MachineOperand::MO_CCRegister, UTy,
498 /// addRegOperand - Add a symbolic virtual register reference...
500 void addRegOperand(int reg, bool isDef) {
501 assert(!OperandsComplete() &&
502 "Trying to add an operand to a machine instr that is already done!");
503 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
504 isDef ? MOTy::Def : MOTy::Use));
507 /// addRegOperand - Add a symbolic virtual register reference...
509 void addRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
510 assert(!OperandsComplete() &&
511 "Trying to add an operand to a machine instr that is already done!");
512 operands.push_back(MachineOperand(reg, MachineOperand::MO_VirtualRegister,
516 /// addPCDispOperand - Add a PC relative displacement operand to the MI
518 void addPCDispOperand(Value *V) {
519 assert(!OperandsComplete() &&
520 "Trying to add an operand to a machine instr that is already done!");
521 operands.push_back(MachineOperand(V, MachineOperand::MO_PCRelativeDisp,
525 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
527 void addMachineRegOperand(int reg, bool isDef) {
528 assert(!OperandsComplete() &&
529 "Trying to add an operand to a machine instr that is already done!");
530 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
531 isDef ? MOTy::Def : MOTy::Use));
534 /// addMachineRegOperand - Add a virtual register operand to this MachineInstr
536 void addMachineRegOperand(int reg, MOTy::UseType UTy = MOTy::Use) {
537 assert(!OperandsComplete() &&
538 "Trying to add an operand to a machine instr that is already done!");
539 operands.push_back(MachineOperand(reg, MachineOperand::MO_MachineRegister,
543 /// addZeroExtImmOperand - Add a zero extended constant argument to the
544 /// machine instruction.
546 void addZeroExtImmOperand(int64_t intValue) {
547 assert(!OperandsComplete() &&
548 "Trying to add an operand to a machine instr that is already done!");
549 operands.push_back(MachineOperand(intValue,
550 MachineOperand::MO_UnextendedImmed));
553 /// addSignExtImmOperand - Add a zero extended constant argument to the
554 /// machine instruction.
556 void addSignExtImmOperand(int64_t intValue) {
557 assert(!OperandsComplete() &&
558 "Trying to add an operand to a machine instr that is already done!");
559 operands.push_back(MachineOperand(intValue,
560 MachineOperand::MO_SignExtendedImmed));
563 void addMachineBasicBlockOperand(MachineBasicBlock *MBB) {
564 assert(!OperandsComplete() &&
565 "Trying to add an operand to a machine instr that is already done!");
566 operands.push_back(MachineOperand(MBB));
569 /// addFrameIndexOperand - Add an abstract frame index to the instruction
571 void addFrameIndexOperand(unsigned Idx) {
572 assert(!OperandsComplete() &&
573 "Trying to add an operand to a machine instr that is already done!");
574 operands.push_back(MachineOperand(Idx, MachineOperand::MO_FrameIndex));
577 /// addConstantPoolndexOperand - Add a constant pool object index to the
580 void addConstantPoolIndexOperand(unsigned I) {
581 assert(!OperandsComplete() &&
582 "Trying to add an operand to a machine instr that is already done!");
583 operands.push_back(MachineOperand(I, MachineOperand::MO_ConstantPoolIndex));
586 void addGlobalAddressOperand(GlobalValue *GV, bool isPCRelative) {
587 assert(!OperandsComplete() &&
588 "Trying to add an operand to a machine instr that is already done!");
589 operands.push_back(MachineOperand((Value*)GV,
590 MachineOperand::MO_GlobalAddress,
591 MOTy::Use, isPCRelative));
594 /// addExternalSymbolOperand - Add an external symbol operand to this instr
596 void addExternalSymbolOperand(const std::string &SymName, bool isPCRelative) {
597 operands.push_back(MachineOperand(SymName, isPCRelative));
600 //===--------------------------------------------------------------------===//
601 // Accessors used to modify instructions in place.
603 // FIXME: Move this stuff to MachineOperand itself!
605 /// replace - Support to rewrite a machine instruction in place: for now,
606 /// simply replace() and then set new operands with Set.*Operand methods
609 void replace(int Opcode, unsigned numOperands);
611 /// setOpcode - Replace the opcode of the current instruction with a new one.
613 void setOpcode(unsigned Op) { opCode = Op; }
615 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
616 /// fewer operand than it started with.
618 void RemoveOperand(unsigned i) {
619 operands.erase(operands.begin()+i);
622 // Access to set the operands when building the machine instruction
624 void SetMachineOperandVal (unsigned i,
625 MachineOperand::MachineOperandType operandType,
628 void SetMachineOperandConst (unsigned i,
629 MachineOperand::MachineOperandType operandType,
632 void SetMachineOperandReg(unsigned i, int regNum);
635 unsigned substituteValue(const Value* oldVal, Value* newVal,
636 bool defsOnly, bool notDefsAndUses,
637 bool& someArgsWereIgnored);
639 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
640 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
641 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
642 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
645 // SetRegForOperand -
646 // SetRegForImplicitRef -
647 // Mark an explicit or implicit operand with its allocated physical register.
649 void SetRegForOperand(unsigned i, int regNum);
650 void SetRegForImplicitRef(unsigned i, int regNum);
653 // Iterator to enumerate machine operands.
655 template<class MITy, class VTy>
656 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
660 void skipToNextVal() {
661 while (i < MI->getNumOperands() &&
662 !( (MI->getOperand(i).getType() == MachineOperand::MO_VirtualRegister ||
663 MI->getOperand(i).getType() == MachineOperand::MO_CCRegister)
664 && MI->getOperand(i).getVRegValue() != 0))
668 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
673 typedef ValOpIterator<MITy, VTy> _Self;
675 inline VTy operator*() const {
676 return MI->getOperand(i).getVRegValue();
679 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
680 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
682 inline VTy operator->() const { return operator*(); }
684 inline bool isUseOnly() const { return MI->getOperand(i).opIsUse(); }
685 inline bool isDefOnly() const { return MI->getOperand(i).opIsDefOnly(); }
686 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
688 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
689 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
691 inline bool operator==(const _Self &y) const {
694 inline bool operator!=(const _Self &y) const {
695 return !operator==(y);
698 static _Self begin(MITy MI) {
701 static _Self end(MITy MI) {
702 return _Self(MI, MI->getNumOperands());
706 // define begin() and end()
707 val_op_iterator begin() { return val_op_iterator::begin(this); }
708 val_op_iterator end() { return val_op_iterator::end(this); }
710 const_val_op_iterator begin() const {
711 return const_val_op_iterator::begin(this);
713 const_val_op_iterator end() const {
714 return const_val_op_iterator::end(this);
719 //===----------------------------------------------------------------------===//
722 std::ostream& operator<<(std::ostream &OS, const MachineInstr &MI);
723 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
724 void PrintMachineInstructions(const Function *F);
726 } // End llvm namespace