1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class --------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the declaration of the MachineInstr class, which is the
11 // basic representation for all target dependent machine instructions used by
14 //===----------------------------------------------------------------------===//
16 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
17 #define LLVM_CODEGEN_MACHINEINSTR_H
19 #include "llvm/ADT/ArrayRef.h"
20 #include "llvm/ADT/DenseMapInfo.h"
21 #include "llvm/ADT/STLExtras.h"
22 #include "llvm/ADT/StringRef.h"
23 #include "llvm/ADT/ilist.h"
24 #include "llvm/ADT/ilist_node.h"
25 #include "llvm/ADT/iterator_range.h"
26 #include "llvm/CodeGen/MachineOperand.h"
27 #include "llvm/IR/DebugInfo.h"
28 #include "llvm/IR/DebugLoc.h"
29 #include "llvm/IR/InlineAsm.h"
30 #include "llvm/MC/MCInstrDesc.h"
31 #include "llvm/Support/ArrayRecycler.h"
32 #include "llvm/Target/TargetOpcodes.h"
36 template <typename T> class SmallVectorImpl;
38 class TargetInstrInfo;
39 class TargetRegisterClass;
40 class TargetRegisterInfo;
41 class MachineFunction;
42 class MachineMemOperand;
44 //===----------------------------------------------------------------------===//
45 /// MachineInstr - Representation of each machine instruction.
47 /// This class isn't a POD type, but it must have a trivial destructor. When a
48 /// MachineFunction is deleted, all the contained MachineInstrs are deallocated
49 /// without having their destructor called.
51 class MachineInstr : public ilist_node<MachineInstr> {
53 typedef MachineMemOperand **mmo_iterator;
55 /// Flags to specify different kinds of comments to output in
56 /// assembly code. These flags carry semantic information not
57 /// otherwise easily derivable from the IR text.
65 FrameSetup = 1 << 0, // Instruction is used as a part of
66 // function frame setup code.
67 BundledPred = 1 << 1, // Instruction has bundled predecessors.
68 BundledSucc = 1 << 2 // Instruction has bundled successors.
71 const MCInstrDesc *MCID; // Instruction descriptor.
72 MachineBasicBlock *Parent; // Pointer to the owning basic block.
74 // Operands are allocated by an ArrayRecycler.
75 MachineOperand *Operands; // Pointer to the first operand.
76 unsigned NumOperands; // Number of operands on instruction.
77 typedef ArrayRecycler<MachineOperand>::Capacity OperandCapacity;
78 OperandCapacity CapOperands; // Capacity of the Operands array.
80 uint8_t Flags; // Various bits of additional
81 // information about machine
84 uint8_t AsmPrinterFlags; // Various bits of information used by
85 // the AsmPrinter to emit helpful
86 // comments. This is *not* semantic
87 // information. Do not use this for
88 // anything other than to convey comment
89 // information to AsmPrinter.
91 uint8_t NumMemRefs; // Information on memory references.
94 DebugLoc debugLoc; // Source line information.
96 MachineInstr(const MachineInstr&) LLVM_DELETED_FUNCTION;
97 void operator=(const MachineInstr&) LLVM_DELETED_FUNCTION;
98 // Use MachineFunction::DeleteMachineInstr() instead.
99 ~MachineInstr() LLVM_DELETED_FUNCTION;
101 // Intrusive list support
102 friend struct ilist_traits<MachineInstr>;
103 friend struct ilist_traits<MachineBasicBlock>;
104 void setParent(MachineBasicBlock *P) { Parent = P; }
106 /// MachineInstr ctor - This constructor creates a copy of the given
107 /// MachineInstr in the given MachineFunction.
108 MachineInstr(MachineFunction &, const MachineInstr &);
110 /// MachineInstr ctor - This constructor create a MachineInstr and add the
111 /// implicit operands. It reserves space for number of operands specified by
112 /// MCInstrDesc. An explicit DebugLoc is supplied.
113 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
114 const DebugLoc dl, bool NoImp = false);
116 // MachineInstrs are pool-allocated and owned by MachineFunction.
117 friend class MachineFunction;
120 const MachineBasicBlock* getParent() const { return Parent; }
121 MachineBasicBlock* getParent() { return Parent; }
123 /// getAsmPrinterFlags - Return the asm printer flags bitvector.
125 uint8_t getAsmPrinterFlags() const { return AsmPrinterFlags; }
127 /// clearAsmPrinterFlags - clear the AsmPrinter bitvector
129 void clearAsmPrinterFlags() { AsmPrinterFlags = 0; }
131 /// getAsmPrinterFlag - Return whether an AsmPrinter flag is set.
133 bool getAsmPrinterFlag(CommentFlag Flag) const {
134 return AsmPrinterFlags & Flag;
137 /// setAsmPrinterFlag - Set a flag for the AsmPrinter.
139 void setAsmPrinterFlag(CommentFlag Flag) {
140 AsmPrinterFlags |= (uint8_t)Flag;
143 /// clearAsmPrinterFlag - clear specific AsmPrinter flags
145 void clearAsmPrinterFlag(CommentFlag Flag) {
146 AsmPrinterFlags &= ~Flag;
149 /// getFlags - Return the MI flags bitvector.
150 uint8_t getFlags() const {
154 /// getFlag - Return whether an MI flag is set.
155 bool getFlag(MIFlag Flag) const {
159 /// setFlag - Set a MI flag.
160 void setFlag(MIFlag Flag) {
161 Flags |= (uint8_t)Flag;
164 void setFlags(unsigned flags) {
165 // Filter out the automatically maintained flags.
166 unsigned Mask = BundledPred | BundledSucc;
167 Flags = (Flags & Mask) | (flags & ~Mask);
170 /// clearFlag - Clear a MI flag.
171 void clearFlag(MIFlag Flag) {
172 Flags &= ~((uint8_t)Flag);
175 /// isInsideBundle - Return true if MI is in a bundle (but not the first MI
178 /// A bundle looks like this before it's finalized:
190 /// In this case, the first MI starts a bundle but is not inside a bundle, the
191 /// next 2 MIs are considered "inside" the bundle.
193 /// After a bundle is finalized, it looks like this:
209 /// The first instruction has the special opcode "BUNDLE". It's not "inside"
210 /// a bundle, but the next three MIs are.
211 bool isInsideBundle() const {
212 return getFlag(BundledPred);
215 /// isBundled - Return true if this instruction part of a bundle. This is true
216 /// if either itself or its following instruction is marked "InsideBundle".
217 bool isBundled() const {
218 return isBundledWithPred() || isBundledWithSucc();
221 /// Return true if this instruction is part of a bundle, and it is not the
222 /// first instruction in the bundle.
223 bool isBundledWithPred() const { return getFlag(BundledPred); }
225 /// Return true if this instruction is part of a bundle, and it is not the
226 /// last instruction in the bundle.
227 bool isBundledWithSucc() const { return getFlag(BundledSucc); }
229 /// Bundle this instruction with its predecessor. This can be an unbundled
230 /// instruction, or it can be the first instruction in a bundle.
231 void bundleWithPred();
233 /// Bundle this instruction with its successor. This can be an unbundled
234 /// instruction, or it can be the last instruction in a bundle.
235 void bundleWithSucc();
237 /// Break bundle above this instruction.
238 void unbundleFromPred();
240 /// Break bundle below this instruction.
241 void unbundleFromSucc();
243 /// getDebugLoc - Returns the debug location id of this MachineInstr.
245 DebugLoc getDebugLoc() const { return debugLoc; }
247 /// getDebugVariable() - Return the debug variable referenced by
248 /// this DBG_VALUE instruction.
249 DIVariable getDebugVariable() const {
250 assert(isDebugValue() && "not a DBG_VALUE");
251 const MDNode *Var = getOperand(getNumOperands() - 1).getMetadata();
252 return DIVariable(Var);
255 /// emitError - Emit an error referring to the source location of this
256 /// instruction. This should only be used for inline assembly that is somehow
257 /// impossible to compile. Other errors should have been handled much
260 /// If this method returns, the caller should try to recover from the error.
262 void emitError(StringRef Msg) const;
264 /// getDesc - Returns the target instruction descriptor of this
266 const MCInstrDesc &getDesc() const { return *MCID; }
268 /// getOpcode - Returns the opcode of this MachineInstr.
270 int getOpcode() const { return MCID->Opcode; }
272 /// Access to explicit operands of the instruction.
274 unsigned getNumOperands() const { return NumOperands; }
276 const MachineOperand& getOperand(unsigned i) const {
277 assert(i < getNumOperands() && "getOperand() out of range!");
280 MachineOperand& getOperand(unsigned i) {
281 assert(i < getNumOperands() && "getOperand() out of range!");
285 /// getNumExplicitOperands - Returns the number of non-implicit operands.
287 unsigned getNumExplicitOperands() const;
289 /// iterator/begin/end - Iterate over all operands of a machine instruction.
290 typedef MachineOperand *mop_iterator;
291 typedef const MachineOperand *const_mop_iterator;
293 mop_iterator operands_begin() { return Operands; }
294 mop_iterator operands_end() { return Operands + NumOperands; }
296 const_mop_iterator operands_begin() const { return Operands; }
297 const_mop_iterator operands_end() const { return Operands + NumOperands; }
299 iterator_range<mop_iterator> operands() {
300 return iterator_range<mop_iterator>(operands_begin(), operands_end());
302 iterator_range<const_mop_iterator> operands() const {
303 return iterator_range<const_mop_iterator>(operands_begin(), operands_end());
305 iterator_range<mop_iterator> explicit_operands() {
306 return iterator_range<mop_iterator>(
307 operands_begin(), operands_begin() + getNumExplicitOperands());
309 iterator_range<const_mop_iterator> explicit_operands() const {
310 return iterator_range<const_mop_iterator>(
311 operands_begin(), operands_begin() + getNumExplicitOperands());
313 iterator_range<mop_iterator> implicit_operands() {
314 return iterator_range<mop_iterator>(explicit_operands().end(),
317 iterator_range<const_mop_iterator> implicit_operands() const {
318 return iterator_range<const_mop_iterator>(explicit_operands().end(),
321 iterator_range<mop_iterator> defs() {
322 return iterator_range<mop_iterator>(
323 operands_begin(), operands_begin() + getDesc().getNumDefs());
325 iterator_range<const_mop_iterator> defs() const {
326 return iterator_range<const_mop_iterator>(
327 operands_begin(), operands_begin() + getDesc().getNumDefs());
329 iterator_range<mop_iterator> uses() {
330 return iterator_range<mop_iterator>(
331 operands_begin() + getDesc().getNumDefs(), operands_end());
333 iterator_range<const_mop_iterator> uses() const {
334 return iterator_range<const_mop_iterator>(
335 operands_begin() + getDesc().getNumDefs(), operands_end());
338 /// Access to memory operands of the instruction
339 mmo_iterator memoperands_begin() const { return MemRefs; }
340 mmo_iterator memoperands_end() const { return MemRefs + NumMemRefs; }
341 bool memoperands_empty() const { return NumMemRefs == 0; }
343 iterator_range<mmo_iterator> memoperands() {
344 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
346 iterator_range<mmo_iterator> memoperands() const {
347 return iterator_range<mmo_iterator>(memoperands_begin(), memoperands_end());
350 /// hasOneMemOperand - Return true if this instruction has exactly one
351 /// MachineMemOperand.
352 bool hasOneMemOperand() const {
353 return NumMemRefs == 1;
356 /// API for querying MachineInstr properties. They are the same as MCInstrDesc
357 /// queries but they are bundle aware.
360 IgnoreBundle, // Ignore bundles
361 AnyInBundle, // Return true if any instruction in bundle has property
362 AllInBundle // Return true if all instructions in bundle have property
365 /// hasProperty - Return true if the instruction (or in the case of a bundle,
366 /// the instructions inside the bundle) has the specified property.
367 /// The first argument is the property being queried.
368 /// The second argument indicates whether the query should look inside
369 /// instruction bundles.
370 bool hasProperty(unsigned MCFlag, QueryType Type = AnyInBundle) const {
371 // Inline the fast path for unbundled or bundle-internal instructions.
372 if (Type == IgnoreBundle || !isBundled() || isBundledWithPred())
373 return getDesc().getFlags() & (1 << MCFlag);
375 // If this is the first instruction in a bundle, take the slow path.
376 return hasPropertyInBundle(1 << MCFlag, Type);
379 /// isVariadic - Return true if this instruction can have a variable number of
380 /// operands. In this case, the variable operands will be after the normal
381 /// operands but before the implicit definitions and uses (if any are
383 bool isVariadic(QueryType Type = IgnoreBundle) const {
384 return hasProperty(MCID::Variadic, Type);
387 /// hasOptionalDef - Set if this instruction has an optional definition, e.g.
388 /// ARM instructions which can set condition code if 's' bit is set.
389 bool hasOptionalDef(QueryType Type = IgnoreBundle) const {
390 return hasProperty(MCID::HasOptionalDef, Type);
393 /// isPseudo - Return true if this is a pseudo instruction that doesn't
394 /// correspond to a real machine instruction.
396 bool isPseudo(QueryType Type = IgnoreBundle) const {
397 return hasProperty(MCID::Pseudo, Type);
400 bool isReturn(QueryType Type = AnyInBundle) const {
401 return hasProperty(MCID::Return, Type);
404 bool isCall(QueryType Type = AnyInBundle) const {
405 return hasProperty(MCID::Call, Type);
408 /// isBarrier - Returns true if the specified instruction stops control flow
409 /// from executing the instruction immediately following it. Examples include
410 /// unconditional branches and return instructions.
411 bool isBarrier(QueryType Type = AnyInBundle) const {
412 return hasProperty(MCID::Barrier, Type);
415 /// isTerminator - Returns true if this instruction part of the terminator for
416 /// a basic block. Typically this is things like return and branch
419 /// Various passes use this to insert code into the bottom of a basic block,
420 /// but before control flow occurs.
421 bool isTerminator(QueryType Type = AnyInBundle) const {
422 return hasProperty(MCID::Terminator, Type);
425 /// isBranch - Returns true if this is a conditional, unconditional, or
426 /// indirect branch. Predicates below can be used to discriminate between
427 /// these cases, and the TargetInstrInfo::AnalyzeBranch method can be used to
428 /// get more information.
429 bool isBranch(QueryType Type = AnyInBundle) const {
430 return hasProperty(MCID::Branch, Type);
433 /// isIndirectBranch - Return true if this is an indirect branch, such as a
434 /// branch through a register.
435 bool isIndirectBranch(QueryType Type = AnyInBundle) const {
436 return hasProperty(MCID::IndirectBranch, Type);
439 /// isConditionalBranch - Return true if this is a branch which may fall
440 /// through to the next instruction or may transfer control flow to some other
441 /// block. The TargetInstrInfo::AnalyzeBranch method can be used to get more
442 /// information about this branch.
443 bool isConditionalBranch(QueryType Type = AnyInBundle) const {
444 return isBranch(Type) & !isBarrier(Type) & !isIndirectBranch(Type);
447 /// isUnconditionalBranch - Return true if this is a branch which always
448 /// transfers control flow to some other block. The
449 /// TargetInstrInfo::AnalyzeBranch method can be used to get more information
450 /// about this branch.
451 bool isUnconditionalBranch(QueryType Type = AnyInBundle) const {
452 return isBranch(Type) & isBarrier(Type) & !isIndirectBranch(Type);
455 /// Return true if this instruction has a predicate operand that
456 /// controls execution. It may be set to 'always', or may be set to other
457 /// values. There are various methods in TargetInstrInfo that can be used to
458 /// control and modify the predicate in this instruction.
459 bool isPredicable(QueryType Type = AllInBundle) const {
460 // If it's a bundle than all bundled instructions must be predicable for this
462 return hasProperty(MCID::Predicable, Type);
465 /// isCompare - Return true if this instruction is a comparison.
466 bool isCompare(QueryType Type = IgnoreBundle) const {
467 return hasProperty(MCID::Compare, Type);
470 /// isMoveImmediate - Return true if this instruction is a move immediate
471 /// (including conditional moves) instruction.
472 bool isMoveImmediate(QueryType Type = IgnoreBundle) const {
473 return hasProperty(MCID::MoveImm, Type);
476 /// isBitcast - Return true if this instruction is a bitcast instruction.
478 bool isBitcast(QueryType Type = IgnoreBundle) const {
479 return hasProperty(MCID::Bitcast, Type);
482 /// isSelect - Return true if this instruction is a select instruction.
484 bool isSelect(QueryType Type = IgnoreBundle) const {
485 return hasProperty(MCID::Select, Type);
488 /// isNotDuplicable - Return true if this instruction cannot be safely
489 /// duplicated. For example, if the instruction has a unique labels attached
490 /// to it, duplicating it would cause multiple definition errors.
491 bool isNotDuplicable(QueryType Type = AnyInBundle) const {
492 return hasProperty(MCID::NotDuplicable, Type);
495 /// hasDelaySlot - Returns true if the specified instruction has a delay slot
496 /// which must be filled by the code generator.
497 bool hasDelaySlot(QueryType Type = AnyInBundle) const {
498 return hasProperty(MCID::DelaySlot, Type);
501 /// canFoldAsLoad - Return true for instructions that can be folded as
502 /// memory operands in other instructions. The most common use for this
503 /// is instructions that are simple loads from memory that don't modify
504 /// the loaded value in any way, but it can also be used for instructions
505 /// that can be expressed as constant-pool loads, such as V_SETALLONES
506 /// on x86, to allow them to be folded when it is beneficial.
507 /// This should only be set on instructions that return a value in their
508 /// only virtual register definition.
509 bool canFoldAsLoad(QueryType Type = IgnoreBundle) const {
510 return hasProperty(MCID::FoldableAsLoad, Type);
513 //===--------------------------------------------------------------------===//
514 // Side Effect Analysis
515 //===--------------------------------------------------------------------===//
517 /// mayLoad - Return true if this instruction could possibly read memory.
518 /// Instructions with this flag set are not necessarily simple load
519 /// instructions, they may load a value and modify it, for example.
520 bool mayLoad(QueryType Type = AnyInBundle) const {
522 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
523 if (ExtraInfo & InlineAsm::Extra_MayLoad)
526 return hasProperty(MCID::MayLoad, Type);
530 /// mayStore - Return true if this instruction could possibly modify memory.
531 /// Instructions with this flag set are not necessarily simple store
532 /// instructions, they may store a modified value based on their operands, or
533 /// may not actually modify anything, for example.
534 bool mayStore(QueryType Type = AnyInBundle) const {
536 unsigned ExtraInfo = getOperand(InlineAsm::MIOp_ExtraInfo).getImm();
537 if (ExtraInfo & InlineAsm::Extra_MayStore)
540 return hasProperty(MCID::MayStore, Type);
543 //===--------------------------------------------------------------------===//
544 // Flags that indicate whether an instruction can be modified by a method.
545 //===--------------------------------------------------------------------===//
547 /// isCommutable - Return true if this may be a 2- or 3-address
548 /// instruction (of the form "X = op Y, Z, ..."), which produces the same
549 /// result if Y and Z are exchanged. If this flag is set, then the
550 /// TargetInstrInfo::commuteInstruction method may be used to hack on the
553 /// Note that this flag may be set on instructions that are only commutable
554 /// sometimes. In these cases, the call to commuteInstruction will fail.
555 /// Also note that some instructions require non-trivial modification to
557 bool isCommutable(QueryType Type = IgnoreBundle) const {
558 return hasProperty(MCID::Commutable, Type);
561 /// isConvertibleTo3Addr - Return true if this is a 2-address instruction
562 /// which can be changed into a 3-address instruction if needed. Doing this
563 /// transformation can be profitable in the register allocator, because it
564 /// means that the instruction can use a 2-address form if possible, but
565 /// degrade into a less efficient form if the source and dest register cannot
566 /// be assigned to the same register. For example, this allows the x86
567 /// backend to turn a "shl reg, 3" instruction into an LEA instruction, which
568 /// is the same speed as the shift but has bigger code size.
570 /// If this returns true, then the target must implement the
571 /// TargetInstrInfo::convertToThreeAddress method for this instruction, which
572 /// is allowed to fail if the transformation isn't valid for this specific
573 /// instruction (e.g. shl reg, 4 on x86).
575 bool isConvertibleTo3Addr(QueryType Type = IgnoreBundle) const {
576 return hasProperty(MCID::ConvertibleTo3Addr, Type);
579 /// usesCustomInsertionHook - Return true if this instruction requires
580 /// custom insertion support when the DAG scheduler is inserting it into a
581 /// machine basic block. If this is true for the instruction, it basically
582 /// means that it is a pseudo instruction used at SelectionDAG time that is
583 /// expanded out into magic code by the target when MachineInstrs are formed.
585 /// If this is true, the TargetLoweringInfo::InsertAtEndOfBasicBlock method
586 /// is used to insert this into the MachineBasicBlock.
587 bool usesCustomInsertionHook(QueryType Type = IgnoreBundle) const {
588 return hasProperty(MCID::UsesCustomInserter, Type);
591 /// hasPostISelHook - Return true if this instruction requires *adjustment*
592 /// after instruction selection by calling a target hook. For example, this
593 /// can be used to fill in ARM 's' optional operand depending on whether
594 /// the conditional flag register is used.
595 bool hasPostISelHook(QueryType Type = IgnoreBundle) const {
596 return hasProperty(MCID::HasPostISelHook, Type);
599 /// isRematerializable - Returns true if this instruction is a candidate for
600 /// remat. This flag is deprecated, please don't use it anymore. If this
601 /// flag is set, the isReallyTriviallyReMaterializable() method is called to
602 /// verify the instruction is really rematable.
603 bool isRematerializable(QueryType Type = AllInBundle) const {
604 // It's only possible to re-mat a bundle if all bundled instructions are
605 // re-materializable.
606 return hasProperty(MCID::Rematerializable, Type);
609 /// isAsCheapAsAMove - Returns true if this instruction has the same cost (or
610 /// less) than a move instruction. This is useful during certain types of
611 /// optimizations (e.g., remat during two-address conversion or machine licm)
612 /// where we would like to remat or hoist the instruction, but not if it costs
613 /// more than moving the instruction into the appropriate register. Note, we
614 /// are not marking copies from and to the same register class with this flag.
615 bool isAsCheapAsAMove(QueryType Type = AllInBundle) const {
616 // Only returns true for a bundle if all bundled instructions are cheap.
617 // FIXME: This probably requires a target hook.
618 return hasProperty(MCID::CheapAsAMove, Type);
621 /// hasExtraSrcRegAllocReq - Returns true if this instruction source operands
622 /// have special register allocation requirements that are not captured by the
623 /// operand register classes. e.g. ARM::STRD's two source registers must be an
624 /// even / odd pair, ARM::STM registers have to be in ascending order.
625 /// Post-register allocation passes should not attempt to change allocations
626 /// for sources of instructions with this flag.
627 bool hasExtraSrcRegAllocReq(QueryType Type = AnyInBundle) const {
628 return hasProperty(MCID::ExtraSrcRegAllocReq, Type);
631 /// hasExtraDefRegAllocReq - Returns true if this instruction def operands
632 /// have special register allocation requirements that are not captured by the
633 /// operand register classes. e.g. ARM::LDRD's two def registers must be an
634 /// even / odd pair, ARM::LDM registers have to be in ascending order.
635 /// Post-register allocation passes should not attempt to change allocations
636 /// for definitions of instructions with this flag.
637 bool hasExtraDefRegAllocReq(QueryType Type = AnyInBundle) const {
638 return hasProperty(MCID::ExtraDefRegAllocReq, Type);
643 CheckDefs, // Check all operands for equality
644 CheckKillDead, // Check all operands including kill / dead markers
645 IgnoreDefs, // Ignore all definitions
646 IgnoreVRegDefs // Ignore virtual register definitions
649 /// isIdenticalTo - Return true if this instruction is identical to (same
650 /// opcode and same operands as) the specified instruction.
651 bool isIdenticalTo(const MachineInstr *Other,
652 MICheckType Check = CheckDefs) const;
654 /// Unlink 'this' from the containing basic block, and return it without
657 /// This function can not be used on bundled instructions, use
658 /// removeFromBundle() to remove individual instructions from a bundle.
659 MachineInstr *removeFromParent();
661 /// Unlink this instruction from its basic block and return it without
664 /// If the instruction is part of a bundle, the other instructions in the
665 /// bundle remain bundled.
666 MachineInstr *removeFromBundle();
668 /// Unlink 'this' from the containing basic block and delete it.
670 /// If this instruction is the header of a bundle, the whole bundle is erased.
671 /// This function can not be used for instructions inside a bundle, use
672 /// eraseFromBundle() to erase individual bundled instructions.
673 void eraseFromParent();
675 /// Unlink 'this' form its basic block and delete it.
677 /// If the instruction is part of a bundle, the other instructions in the
678 /// bundle remain bundled.
679 void eraseFromBundle();
681 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
682 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
684 /// isLabel - Returns true if the MachineInstr represents a label.
686 bool isLabel() const { return isEHLabel() || isGCLabel(); }
687 bool isCFIInstruction() const {
688 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
691 // True if the instruction represents a position in the function.
692 bool isPosition() const { return isLabel() || isCFIInstruction(); }
694 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
695 /// A DBG_VALUE is indirect iff the first operand is a register and
696 /// the second operand is an immediate.
697 bool isIndirectDebugValue() const {
698 return isDebugValue()
699 && getOperand(0).isReg()
700 && getOperand(1).isImm();
703 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
704 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
705 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
706 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
707 bool isMSInlineAsm() const {
708 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
710 bool isStackAligningInlineAsm() const;
711 InlineAsm::AsmDialect getInlineAsmDialect() const;
712 bool isInsertSubreg() const {
713 return getOpcode() == TargetOpcode::INSERT_SUBREG;
715 bool isSubregToReg() const {
716 return getOpcode() == TargetOpcode::SUBREG_TO_REG;
718 bool isRegSequence() const {
719 return getOpcode() == TargetOpcode::REG_SEQUENCE;
721 bool isBundle() const {
722 return getOpcode() == TargetOpcode::BUNDLE;
724 bool isCopy() const {
725 return getOpcode() == TargetOpcode::COPY;
727 bool isFullCopy() const {
728 return isCopy() && !getOperand(0).getSubReg() && !getOperand(1).getSubReg();
730 bool isExtractSubreg() const {
731 return getOpcode() == TargetOpcode::EXTRACT_SUBREG;
734 /// isCopyLike - Return true if the instruction behaves like a copy.
735 /// This does not include native copy instructions.
736 bool isCopyLike() const {
737 return isCopy() || isSubregToReg();
740 /// isIdentityCopy - Return true is the instruction is an identity copy.
741 bool isIdentityCopy() const {
742 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
743 getOperand(0).getSubReg() == getOperand(1).getSubReg();
746 /// isTransient - Return true if this is a transient instruction that is
747 /// either very likely to be eliminated during register allocation (such as
748 /// copy-like instructions), or if this instruction doesn't have an
749 /// execution-time cost.
750 bool isTransient() const {
751 switch(getOpcode()) {
752 default: return false;
753 // Copy-like instructions are usually eliminated during register allocation.
754 case TargetOpcode::PHI:
755 case TargetOpcode::COPY:
756 case TargetOpcode::INSERT_SUBREG:
757 case TargetOpcode::SUBREG_TO_REG:
758 case TargetOpcode::REG_SEQUENCE:
759 // Pseudo-instructions that don't produce any real output.
760 case TargetOpcode::IMPLICIT_DEF:
761 case TargetOpcode::KILL:
762 case TargetOpcode::CFI_INSTRUCTION:
763 case TargetOpcode::EH_LABEL:
764 case TargetOpcode::GC_LABEL:
765 case TargetOpcode::DBG_VALUE:
770 /// Return the number of instructions inside the MI bundle, excluding the
773 /// This is the number of instructions that MachineBasicBlock::iterator
774 /// skips, 0 for unbundled instructions.
775 unsigned getBundleSize() const;
777 /// readsRegister - Return true if the MachineInstr reads the specified
778 /// register. If TargetRegisterInfo is passed, then it also checks if there
779 /// is a read of a super-register.
780 /// This does not count partial redefines of virtual registers as reads:
782 bool readsRegister(unsigned Reg,
783 const TargetRegisterInfo *TRI = nullptr) const {
784 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
787 /// readsVirtualRegister - Return true if the MachineInstr reads the specified
788 /// virtual register. Take into account that a partial define is a
789 /// read-modify-write operation.
790 bool readsVirtualRegister(unsigned Reg) const {
791 return readsWritesVirtualRegister(Reg).first;
794 /// readsWritesVirtualRegister - Return a pair of bools (reads, writes)
795 /// indicating if this instruction reads or writes Reg. This also considers
797 /// If Ops is not null, all operand indices for Reg are added.
798 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
799 SmallVectorImpl<unsigned> *Ops = nullptr) const;
801 /// killsRegister - Return true if the MachineInstr kills the specified
802 /// register. If TargetRegisterInfo is passed, then it also checks if there is
803 /// a kill of a super-register.
804 bool killsRegister(unsigned Reg,
805 const TargetRegisterInfo *TRI = nullptr) const {
806 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
809 /// definesRegister - Return true if the MachineInstr fully defines the
810 /// specified register. If TargetRegisterInfo is passed, then it also checks
811 /// if there is a def of a super-register.
812 /// NOTE: It's ignoring subreg indices on virtual registers.
813 bool definesRegister(unsigned Reg,
814 const TargetRegisterInfo *TRI = nullptr) const {
815 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
818 /// modifiesRegister - Return true if the MachineInstr modifies (fully define
819 /// or partially define) the specified register.
820 /// NOTE: It's ignoring subreg indices on virtual registers.
821 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
822 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
825 /// registerDefIsDead - Returns true if the register is dead in this machine
826 /// instruction. If TargetRegisterInfo is passed, then it also checks
827 /// if there is a dead def of a super-register.
828 bool registerDefIsDead(unsigned Reg,
829 const TargetRegisterInfo *TRI = nullptr) const {
830 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
833 /// findRegisterUseOperandIdx() - Returns the operand index that is a use of
834 /// the specific register or -1 if it is not found. It further tightens
835 /// the search criteria to a use that kills the register if isKill is true.
836 int findRegisterUseOperandIdx(unsigned Reg, bool isKill = false,
837 const TargetRegisterInfo *TRI = nullptr) const;
839 /// findRegisterUseOperand - Wrapper for findRegisterUseOperandIdx, it returns
840 /// a pointer to the MachineOperand rather than an index.
841 MachineOperand *findRegisterUseOperand(unsigned Reg, bool isKill = false,
842 const TargetRegisterInfo *TRI = nullptr) {
843 int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI);
844 return (Idx == -1) ? nullptr : &getOperand(Idx);
847 /// findRegisterDefOperandIdx() - Returns the operand index that is a def of
848 /// the specified register or -1 if it is not found. If isDead is true, defs
849 /// that are not dead are skipped. If Overlap is true, then it also looks for
850 /// defs that merely overlap the specified register. If TargetRegisterInfo is
851 /// non-null, then it also checks if there is a def of a super-register.
852 /// This may also return a register mask operand when Overlap is true.
853 int findRegisterDefOperandIdx(unsigned Reg,
854 bool isDead = false, bool Overlap = false,
855 const TargetRegisterInfo *TRI = nullptr) const;
857 /// findRegisterDefOperand - Wrapper for findRegisterDefOperandIdx, it returns
858 /// a pointer to the MachineOperand rather than an index.
859 MachineOperand *findRegisterDefOperand(unsigned Reg, bool isDead = false,
860 const TargetRegisterInfo *TRI = nullptr) {
861 int Idx = findRegisterDefOperandIdx(Reg, isDead, false, TRI);
862 return (Idx == -1) ? nullptr : &getOperand(Idx);
865 /// findFirstPredOperandIdx() - Find the index of the first operand in the
866 /// operand list that is used to represent the predicate. It returns -1 if
868 int findFirstPredOperandIdx() const;
870 /// findInlineAsmFlagIdx() - Find the index of the flag word operand that
871 /// corresponds to operand OpIdx on an inline asm instruction. Returns -1 if
872 /// getOperand(OpIdx) does not belong to an inline asm operand group.
874 /// If GroupNo is not NULL, it will receive the number of the operand group
875 /// containing OpIdx.
877 /// The flag operand is an immediate that can be decoded with methods like
878 /// InlineAsm::hasRegClassConstraint().
880 int findInlineAsmFlagIdx(unsigned OpIdx, unsigned *GroupNo = nullptr) const;
882 /// getRegClassConstraint - Compute the static register class constraint for
883 /// operand OpIdx. For normal instructions, this is derived from the
884 /// MCInstrDesc. For inline assembly it is derived from the flag words.
886 /// Returns NULL if the static register classs constraint cannot be
889 const TargetRegisterClass*
890 getRegClassConstraint(unsigned OpIdx,
891 const TargetInstrInfo *TII,
892 const TargetRegisterInfo *TRI) const;
894 /// \brief Applies the constraints (def/use) implied by this MI on \p Reg to
895 /// the given \p CurRC.
896 /// If \p ExploreBundle is set and MI is part of a bundle, all the
897 /// instructions inside the bundle will be taken into account. In other words,
898 /// this method accumulates all the constrains of the operand of this MI and
899 /// the related bundle if MI is a bundle or inside a bundle.
901 /// Returns the register class that statisfies both \p CurRC and the
902 /// constraints set by MI. Returns NULL if such a register class does not
905 /// \pre CurRC must not be NULL.
906 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
907 unsigned Reg, const TargetRegisterClass *CurRC,
908 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
909 bool ExploreBundle = false) const;
911 /// \brief Applies the constraints (def/use) implied by the \p OpIdx operand
912 /// to the given \p CurRC.
914 /// Returns the register class that statisfies both \p CurRC and the
915 /// constraints set by \p OpIdx MI. Returns NULL if such a register class
918 /// \pre CurRC must not be NULL.
919 /// \pre The operand at \p OpIdx must be a register.
920 const TargetRegisterClass *
921 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
922 const TargetInstrInfo *TII,
923 const TargetRegisterInfo *TRI) const;
925 /// tieOperands - Add a tie between the register operands at DefIdx and
926 /// UseIdx. The tie will cause the register allocator to ensure that the two
927 /// operands are assigned the same physical register.
929 /// Tied operands are managed automatically for explicit operands in the
930 /// MCInstrDesc. This method is for exceptional cases like inline asm.
931 void tieOperands(unsigned DefIdx, unsigned UseIdx);
933 /// findTiedOperandIdx - Given the index of a tied register operand, find the
934 /// operand it is tied to. Defs are tied to uses and vice versa. Returns the
935 /// index of the tied operand which must exist.
936 unsigned findTiedOperandIdx(unsigned OpIdx) const;
938 /// isRegTiedToUseOperand - Given the index of a register def operand,
939 /// check if the register def is tied to a source operand, due to either
940 /// two-address elimination or inline assembly constraints. Returns the
941 /// first tied use operand index by reference if UseOpIdx is not null.
942 bool isRegTiedToUseOperand(unsigned DefOpIdx,
943 unsigned *UseOpIdx = nullptr) const {
944 const MachineOperand &MO = getOperand(DefOpIdx);
945 if (!MO.isReg() || !MO.isDef() || !MO.isTied())
948 *UseOpIdx = findTiedOperandIdx(DefOpIdx);
952 /// isRegTiedToDefOperand - Return true if the use operand of the specified
953 /// index is tied to a def operand. It also returns the def operand index by
954 /// reference if DefOpIdx is not null.
955 bool isRegTiedToDefOperand(unsigned UseOpIdx,
956 unsigned *DefOpIdx = nullptr) const {
957 const MachineOperand &MO = getOperand(UseOpIdx);
958 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
961 *DefOpIdx = findTiedOperandIdx(UseOpIdx);
965 /// clearKillInfo - Clears kill flags on all operands.
967 void clearKillInfo();
969 /// substituteRegister - Replace all occurrences of FromReg with ToReg:SubIdx,
970 /// properly composing subreg indices where necessary.
971 void substituteRegister(unsigned FromReg, unsigned ToReg, unsigned SubIdx,
972 const TargetRegisterInfo &RegInfo);
974 /// addRegisterKilled - We have determined MI kills a register. Look for the
975 /// operand that uses it and mark it as IsKill. If AddIfNotFound is true,
976 /// add a implicit operand if it's not found. Returns true if the operand
977 /// exists / is added.
978 bool addRegisterKilled(unsigned IncomingReg,
979 const TargetRegisterInfo *RegInfo,
980 bool AddIfNotFound = false);
982 /// clearRegisterKills - Clear all kill flags affecting Reg. If RegInfo is
983 /// provided, this includes super-register kills.
984 void clearRegisterKills(unsigned Reg, const TargetRegisterInfo *RegInfo);
986 /// addRegisterDead - We have determined MI defined a register without a use.
987 /// Look for the operand that defines it and mark it as IsDead. If
988 /// AddIfNotFound is true, add a implicit operand if it's not found. Returns
989 /// true if the operand exists / is added.
990 bool addRegisterDead(unsigned Reg, const TargetRegisterInfo *RegInfo,
991 bool AddIfNotFound = false);
993 /// addRegisterDefined - We have determined MI defines a register. Make sure
994 /// there is an operand defining Reg.
995 void addRegisterDefined(unsigned Reg,
996 const TargetRegisterInfo *RegInfo = nullptr);
998 /// setPhysRegsDeadExcept - Mark every physreg used by this instruction as
999 /// dead except those in the UsedRegs list.
1001 /// On instructions with register mask operands, also add implicit-def
1002 /// operands for all registers in UsedRegs.
1003 void setPhysRegsDeadExcept(ArrayRef<unsigned> UsedRegs,
1004 const TargetRegisterInfo &TRI);
1006 /// isSafeToMove - Return true if it is safe to move this instruction. If
1007 /// SawStore is set to true, it means that there is a store (or call) between
1008 /// the instruction's location and its intended destination.
1009 bool isSafeToMove(const TargetInstrInfo *TII, AliasAnalysis *AA,
1010 bool &SawStore) const;
1012 /// hasOrderedMemoryRef - Return true if this instruction may have an ordered
1013 /// or volatile memory reference, or if the information describing the memory
1014 /// reference is not available. Return false if it is known to have no
1015 /// ordered or volatile memory references.
1016 bool hasOrderedMemoryRef() const;
1018 /// isInvariantLoad - Return true if this instruction is loading from a
1019 /// location whose value is invariant across the function. For example,
1020 /// loading a value from the constant pool or from the argument area of
1021 /// a function if it does not change. This should only return true of *all*
1022 /// loads the instruction does are invariant (if it does multiple loads).
1023 bool isInvariantLoad(AliasAnalysis *AA) const;
1025 /// isConstantValuePHI - If the specified instruction is a PHI that always
1026 /// merges together the same virtual register, return the register, otherwise
1028 unsigned isConstantValuePHI() const;
1030 /// hasUnmodeledSideEffects - Return true if this instruction has side
1031 /// effects that are not modeled by mayLoad / mayStore, etc.
1032 /// For all instructions, the property is encoded in MCInstrDesc::Flags
1033 /// (see MCInstrDesc::hasUnmodeledSideEffects(). The only exception is
1034 /// INLINEASM instruction, in which case the side effect property is encoded
1035 /// in one of its operands (see InlineAsm::Extra_HasSideEffect).
1037 bool hasUnmodeledSideEffects() const;
1039 /// allDefsAreDead - Return true if all the defs of this instruction are dead.
1041 bool allDefsAreDead() const;
1043 /// copyImplicitOps - Copy implicit register operands from specified
1044 /// instruction to this instruction.
1045 void copyImplicitOps(MachineFunction &MF, const MachineInstr *MI);
1048 // Debugging support
1050 void print(raw_ostream &OS, const TargetMachine *TM = nullptr,
1051 bool SkipOpers = false) const;
1054 //===--------------------------------------------------------------------===//
1055 // Accessors used to build up machine instructions.
1057 /// Add the specified operand to the instruction. If it is an implicit
1058 /// operand, it is added to the end of the operand list. If it is an
1059 /// explicit operand it is added at the end of the explicit operand list
1060 /// (before the first implicit operand).
1062 /// MF must be the machine function that was used to allocate this
1065 /// MachineInstrBuilder provides a more convenient interface for creating
1066 /// instructions and adding operands.
1067 void addOperand(MachineFunction &MF, const MachineOperand &Op);
1069 /// Add an operand without providing an MF reference. This only works for
1070 /// instructions that are inserted in a basic block.
1072 /// MachineInstrBuilder and the two-argument addOperand(MF, MO) should be
1074 void addOperand(const MachineOperand &Op);
1076 /// setDesc - Replace the instruction descriptor (thus opcode) of
1077 /// the current instruction with a new one.
1079 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
1081 /// setDebugLoc - Replace current source information with new such.
1082 /// Avoid using this, the constructor argument is preferable.
1084 void setDebugLoc(const DebugLoc dl) { debugLoc = dl; }
1086 /// RemoveOperand - Erase an operand from an instruction, leaving it with one
1087 /// fewer operand than it started with.
1089 void RemoveOperand(unsigned i);
1091 /// addMemOperand - Add a MachineMemOperand to the machine instruction.
1092 /// This function should be used only occasionally. The setMemRefs function
1093 /// is the primary method for setting up a MachineInstr's MemRefs list.
1094 void addMemOperand(MachineFunction &MF, MachineMemOperand *MO);
1096 /// setMemRefs - Assign this MachineInstr's memory reference descriptor
1097 /// list. This does not transfer ownership.
1098 void setMemRefs(mmo_iterator NewMemRefs, mmo_iterator NewMemRefsEnd) {
1099 MemRefs = NewMemRefs;
1100 NumMemRefs = uint8_t(NewMemRefsEnd - NewMemRefs);
1101 assert(NumMemRefs == NewMemRefsEnd - NewMemRefs && "Too many memrefs");
1105 /// getRegInfo - If this instruction is embedded into a MachineFunction,
1106 /// return the MachineRegisterInfo object for the current function, otherwise
1108 MachineRegisterInfo *getRegInfo();
1110 /// untieRegOperand - Break any tie involving OpIdx.
1111 void untieRegOperand(unsigned OpIdx) {
1112 MachineOperand &MO = getOperand(OpIdx);
1113 if (MO.isReg() && MO.isTied()) {
1114 getOperand(findTiedOperandIdx(OpIdx)).TiedTo = 0;
1119 /// addImplicitDefUseOperands - Add all implicit def and use operands to
1120 /// this instruction.
1121 void addImplicitDefUseOperands(MachineFunction &MF);
1123 /// RemoveRegOperandsFromUseLists - Unlink all of the register operands in
1124 /// this instruction from their respective use lists. This requires that the
1125 /// operands already be on their use lists.
1126 void RemoveRegOperandsFromUseLists(MachineRegisterInfo&);
1128 /// AddRegOperandsToUseLists - Add all of the register operands in
1129 /// this instruction from their respective use lists. This requires that the
1130 /// operands not be on their use lists yet.
1131 void AddRegOperandsToUseLists(MachineRegisterInfo&);
1133 /// hasPropertyInBundle - Slow path for hasProperty when we're dealing with a
1135 bool hasPropertyInBundle(unsigned Mask, QueryType Type) const;
1137 /// \brief Implements the logic of getRegClassConstraintEffectForVReg for the
1138 /// this MI and the given operand index \p OpIdx.
1139 /// If the related operand does not constrained Reg, this returns CurRC.
1140 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1141 unsigned OpIdx, unsigned Reg, const TargetRegisterClass *CurRC,
1142 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
1145 /// MachineInstrExpressionTrait - Special DenseMapInfo traits to compare
1146 /// MachineInstr* by *value* of the instruction rather than by pointer value.
1147 /// The hashing and equality testing functions ignore definitions so this is
1148 /// useful for CSE, etc.
1149 struct MachineInstrExpressionTrait : DenseMapInfo<MachineInstr*> {
1150 static inline MachineInstr *getEmptyKey() {
1154 static inline MachineInstr *getTombstoneKey() {
1155 return reinterpret_cast<MachineInstr*>(-1);
1158 static unsigned getHashValue(const MachineInstr* const &MI);
1160 static bool isEqual(const MachineInstr* const &LHS,
1161 const MachineInstr* const &RHS) {
1162 if (RHS == getEmptyKey() || RHS == getTombstoneKey() ||
1163 LHS == getEmptyKey() || LHS == getTombstoneKey())
1165 return LHS->isIdenticalTo(RHS, MachineInstr::IgnoreVRegDefs);
1169 //===----------------------------------------------------------------------===//
1170 // Debugging Support
1172 inline raw_ostream& operator<<(raw_ostream &OS, const MachineInstr &MI) {
1177 } // End llvm namespace