1 //===-- llvm/CodeGen/MachineInstr.h - MachineInstr class ---------*- C++ -*--=//
3 // This file contains the declaration of the MachineInstr class, which is the
4 // basic representation for all target dependant machine instructions used by
7 //===----------------------------------------------------------------------===//
9 #ifndef LLVM_CODEGEN_MACHINEINSTR_H
10 #define LLVM_CODEGEN_MACHINEINSTR_H
12 #include "llvm/Annotation.h"
13 #include "Support/iterator"
14 #include "Support/NonCopyable.h"
19 typedef int MachineOpCode;
20 typedef int OpCodeMask;
22 //---------------------------------------------------------------------------
23 // class MachineOperand
26 // Representation of each machine instruction operand.
27 // This class is designed so that you can allocate a vector of operands
28 // first and initialize each one later.
30 // E.g, for this VM instruction:
31 // ptr = alloca type, numElements
32 // we generate 2 machine instructions on the SPARC:
34 // mul Constant, Numelements -> Reg
35 // add %sp, Reg -> Ptr
37 // Each instruction has 3 operands, listed above. Of those:
38 // - Reg, NumElements, and Ptr are of operand type MO_Register.
39 // - Constant is of operand type MO_SignExtendedImmed on the SPARC.
41 // For the register operands, the virtual register type is as follows:
43 // - Reg will be of virtual register type MO_MInstrVirtualReg. The field
44 // MachineInstr* minstr will point to the instruction that computes reg.
46 // - %sp will be of virtual register type MO_MachineReg.
47 // The field regNum identifies the machine register.
49 // - NumElements will be of virtual register type MO_VirtualReg.
50 // The field Value* value identifies the value.
52 // - Ptr will also be of virtual register type MO_VirtualReg.
53 // Again, the field Value* value identifies the value.
55 //---------------------------------------------------------------------------
57 class MachineOperand {
59 enum MachineOperandType {
60 MO_VirtualRegister, // virtual register for *value
61 MO_MachineRegister, // pre-assigned machine register `regNum'
69 // Bit fields of the flags variable used for different operand properties
70 static const char DEFFLAG = 0x1; // this is a def of the operand
71 static const char DEFUSEFLAG = 0x2; // this is both a def and a use
72 static const char HIFLAG32 = 0x4; // operand is %hi32(value_or_immedVal)
73 static const char LOFLAG32 = 0x8; // operand is %lo32(value_or_immedVal)
74 static const char HIFLAG64 = 0x10; // operand is %hi64(value_or_immedVal)
75 static const char LOFLAG64 = 0x20; // operand is %lo64(value_or_immedVal)
79 Value* value; // BasicBlockVal for a label operand.
80 // ConstantVal for a non-address immediate.
81 // Virtual register for an SSA operand,
82 // including hidden operands required for
83 // the generated machine code.
84 int64_t immedVal; // constant value for an explicit constant
87 MachineOperandType opType:8; // Pack into 8 bits efficiently after flags.
88 char flags; // see bit field definitions above
89 int regNum; // register number for an explicit register
90 // will be set for a value after reg allocation
92 MachineOperand() : immedVal(0), opType(MO_VirtualRegister),
93 flags(0), regNum(-1) {}
94 MachineOperand(const MachineOperand &M)
95 : immedVal(M.immedVal), opType(M.opType), flags(M.flags), regNum(M.regNum) {
99 // Accessor methods. Caller is responsible for checking the
100 // operand type before invoking the corresponding accessor.
102 MachineOperandType getType() const { return opType; }
104 inline Value* getVRegValue () const {
105 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
106 opType == MO_PCRelativeDisp);
109 inline Value* getVRegValueOrNull() const {
110 return (opType == MO_VirtualRegister || opType == MO_CCRegister ||
111 opType == MO_PCRelativeDisp)? value : NULL;
113 inline int getMachineRegNum() const {
114 assert(opType == MO_MachineRegister);
117 inline int64_t getImmedValue () const {
118 assert(opType == MO_SignExtendedImmed || opType == MO_UnextendedImmed);
121 bool opIsDef () const { return flags & DEFFLAG; }
122 bool opIsDefAndUse () const { return flags & DEFUSEFLAG; }
123 bool opHiBits32 () const { return flags & HIFLAG32; }
124 bool opLoBits32 () const { return flags & LOFLAG32; }
125 bool opHiBits64 () const { return flags & HIFLAG64; }
126 bool opLoBits64 () const { return flags & LOFLAG64; }
128 // used to check if a machine register has been allocated to this operand
129 inline bool hasAllocatedReg() const {
130 return (regNum >= 0 &&
131 (opType == MO_VirtualRegister || opType == MO_CCRegister ||
132 opType == MO_MachineRegister));
135 // used to get the reg number if when one is allocated
136 inline int getAllocatedRegNum() const {
137 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
138 opType == MO_MachineRegister);
143 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
147 // Construction methods needed for fine-grain control.
148 // These must be accessed via coresponding methods in MachineInstr.
149 void markDef() { flags |= DEFFLAG; }
150 void markDefAndUse() { flags |= DEFUSEFLAG; }
151 void markHi32() { flags |= HIFLAG32; }
152 void markLo32() { flags |= LOFLAG32; }
153 void markHi64() { flags |= HIFLAG64; }
154 void markLo64() { flags |= LOFLAG64; }
156 // Replaces the Value with its corresponding physical register after
157 // register allocation is complete
158 void setRegForValue(int reg) {
159 assert(opType == MO_VirtualRegister || opType == MO_CCRegister ||
160 opType == MO_MachineRegister);
164 friend class MachineInstr;
168 //---------------------------------------------------------------------------
169 // class MachineInstr
172 // Representation of each machine instruction.
174 // MachineOpCode must be an enum, defined separately for each target.
175 // E.g., It is defined in SparcInstructionSelection.h for the SPARC.
177 // opCodeMask is used to record variants of an instruction.
178 // E.g., each branch instruction on SPARC has 2 flags (i.e., 4 variants):
179 // ANNUL: if 1: Annul delay slot instruction.
180 // PREDICT-NOT-TAKEN: if 1: predict branch not taken.
181 // Instead of creating 4 different opcodes for BNZ, we create a single
182 // opcode and set bits in opCodeMask for each of these flags.
184 // There are 2 kinds of operands:
186 // (1) Explicit operands of the machine instruction in vector operands[]
188 // (2) "Implicit operands" are values implicitly used or defined by the
189 // machine instruction, such as arguments to a CALL, return value of
190 // a CALL (if any), and return value of a RETURN.
191 //---------------------------------------------------------------------------
193 class MachineInstr : public Annotable, // MachineInstrs are annotable
194 public NonCopyable { // Disable copy operations
195 MachineOpCode opCode; // the opcode
196 OpCodeMask opCodeMask; // extra bits for variants of an opcode
197 std::vector<MachineOperand> operands; // the operands
201 bool isDef, isDefAndUse;
203 ImplicitRef(Value *V, bool D, bool DU) : Val(V), isDef(D), isDefAndUse(DU){}
206 // implicitRefs - Values implicitly referenced by this machine instruction
208 std::vector<ImplicitRef> implicitRefs;
210 // regsUsed - all machine registers used for this instruction, including regs
211 // used to save values across the instruction. This is a bitset of registers.
212 std::vector<bool> regsUsed;
214 /*ctor*/ MachineInstr (MachineOpCode _opCode,
215 OpCodeMask _opCodeMask = 0);
216 /*ctor*/ MachineInstr (MachineOpCode _opCode,
217 unsigned numOperands,
218 OpCodeMask _opCodeMask = 0);
219 inline ~MachineInstr () {}
222 // Support to rewrite a machine instruction in place: for now, simply
223 // replace() and then set new operands with Set.*Operand methods below.
225 void replace (MachineOpCode _opCode,
226 unsigned numOperands,
227 OpCodeMask _opCodeMask = 0x0);
232 const MachineOpCode getOpCode() const { return opCode; }
235 // Information about explicit operands of the instruction
237 unsigned getNumOperands() const { return operands.size(); }
239 const MachineOperand& getOperand(unsigned i) const {
240 assert(i < operands.size() && "getOperand() out of range!");
243 MachineOperand& getOperand(unsigned i) {
244 assert(i < operands.size() && "getOperand() out of range!");
248 MachineOperand::MachineOperandType getOperandType(unsigned i) const {
249 return getOperand(i).getType();
252 bool operandIsDefined(unsigned i) const {
253 return getOperand(i).opIsDef();
256 bool operandIsDefinedAndUsed(unsigned i) const {
257 return getOperand(i).opIsDefAndUse();
261 // Information about implicit operands of the instruction
263 unsigned getNumImplicitRefs() const{ return implicitRefs.size();}
265 const Value* getImplicitRef(unsigned i) const {
266 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
267 return implicitRefs[i].Val;
269 Value* getImplicitRef(unsigned i) {
270 assert(i < implicitRefs.size() && "getImplicitRef() out of range!");
271 return implicitRefs[i].Val;
274 bool implicitRefIsDefined(unsigned i) const {
275 assert(i < implicitRefs.size() && "implicitRefIsDefined() out of range!");
276 return implicitRefs[i].isDef;
278 bool implicitRefIsDefinedAndUsed(unsigned i) const {
279 assert(i < implicitRefs.size() && "implicitRefIsDef&Used() out of range!");
280 return implicitRefs[i].isDefAndUse;
283 void addImplicitRef(Value* V, bool isDef=false, bool isDefAndUse=false) {
284 implicitRefs.push_back(ImplicitRef(V, isDef, isDefAndUse));
287 void setImplicitRef(unsigned i, Value* V, bool isDef=false,
288 bool isDefAndUse=false) {
289 assert(i < implicitRefs.size() && "setImplicitRef() out of range!");
290 implicitRefs[i] = ImplicitRef(V, isDef, isDefAndUse);
294 // Information about registers used in this instruction
296 const std::vector<bool> &getRegsUsed() const { return regsUsed; }
298 // insertUsedReg - Add a register to the Used registers set...
299 void insertUsedReg(unsigned Reg) {
300 if (Reg >= regsUsed.size())
301 regsUsed.resize(Reg+1);
302 regsUsed[Reg] = true;
309 friend std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
312 // Define iterators to access the Value operands of the Machine Instruction.
313 // begin() and end() are defined to produce these iterators...
315 template<class _MI, class _V> class ValOpIterator;
316 typedef ValOpIterator<const MachineInstr*,const Value*> const_val_op_iterator;
317 typedef ValOpIterator< MachineInstr*, Value*> val_op_iterator;
320 // Access to set the operands when building the machine instruction
322 void SetMachineOperandVal(unsigned i,
323 MachineOperand::MachineOperandType operandType,
324 Value* V, bool isDef=false, bool isDefAndUse=false);
325 void SetMachineOperandConst(unsigned i,
326 MachineOperand::MachineOperandType operandType,
328 void SetMachineOperandReg(unsigned i, int regNum, bool isDef=false);
330 unsigned substituteValue(const Value* oldVal, Value* newVal,
331 bool defsOnly = true);
333 void setOperandHi32(unsigned i) { operands[i].markHi32(); }
334 void setOperandLo32(unsigned i) { operands[i].markLo32(); }
335 void setOperandHi64(unsigned i) { operands[i].markHi64(); }
336 void setOperandLo64(unsigned i) { operands[i].markLo64(); }
339 // SetRegForOperand - Replaces the Value for the operand with its allocated
340 // physical register after register allocation is complete.
342 void SetRegForOperand(unsigned i, int regNum);
345 // Iterator to enumerate machine operands.
347 template<class MITy, class VTy>
348 class ValOpIterator : public forward_iterator<VTy, ptrdiff_t> {
352 void skipToNextVal() {
353 while (i < MI->getNumOperands() &&
354 !((MI->getOperandType(i) == MachineOperand::MO_VirtualRegister ||
355 MI->getOperandType(i) == MachineOperand::MO_CCRegister)
356 && MI->getOperand(i).getVRegValue() != 0))
360 inline ValOpIterator(MITy mi, unsigned I) : i(I), MI(mi) {
365 typedef ValOpIterator<MITy, VTy> _Self;
367 inline VTy operator*() const {
368 return MI->getOperand(i).getVRegValue();
371 const MachineOperand &getMachineOperand() const { return MI->getOperand(i);}
372 MachineOperand &getMachineOperand() { return MI->getOperand(i);}
374 inline VTy operator->() const { return operator*(); }
376 inline bool isDef() const { return MI->getOperand(i).opIsDef(); }
377 inline bool isDefAndUse() const { return MI->getOperand(i).opIsDefAndUse();}
379 inline _Self& operator++() { i++; skipToNextVal(); return *this; }
380 inline _Self operator++(int) { _Self tmp = *this; ++*this; return tmp; }
382 inline bool operator==(const _Self &y) const {
385 inline bool operator!=(const _Self &y) const {
386 return !operator==(y);
389 static _Self begin(MITy MI) {
392 static _Self end(MITy MI) {
393 return _Self(MI, MI->getNumOperands());
397 // define begin() and end()
398 val_op_iterator begin() { return val_op_iterator::begin(this); }
399 val_op_iterator end() { return val_op_iterator::end(this); }
401 const_val_op_iterator begin() const {
402 return const_val_op_iterator::begin(this);
404 const_val_op_iterator end() const {
405 return const_val_op_iterator::end(this);
409 //---------------------------------------------------------------------------
411 //---------------------------------------------------------------------------
413 std::ostream& operator<<(std::ostream& os, const MachineInstr& minstr);
415 std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
417 void PrintMachineInstructions(const Function *F);