1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariable analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using are sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
41 class LiveVariables : public MachineFunctionPass {
43 /// VarInfo - This represents the regions where a virtual register is live in
44 /// the program. We represent this with three different pieces of
45 /// information: the instruction that uniquely defines the value, the set of
46 /// blocks the instruction is live into and live out of, and the set of
47 /// non-phi instructions that are the last users of the value.
49 /// In the common case where a value is defined and killed in the same block,
50 /// DefInst is the defining inst, there is one killing instruction, and
51 /// AliveBlocks is empty.
53 /// Otherwise, the value is live out of the block. If the value is live
54 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
55 /// the liveness range ends are not included in AliveBlocks, instead being
56 /// captured by the Kills set. In these blocks, the value is live into the
57 /// block (unless the value is defined and killed in the same block) and lives
58 /// until the specified instruction. Note that there cannot ever be a value
59 /// whose Kills set contains two instructions from the same basic block.
61 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
62 /// value in one of its predecessor blocks, it is not listed in the kills set,
63 /// but does include the predecessor block in the AliveBlocks set (unless that
64 /// block also defines the value). This leads to the (perfectly sensical)
65 /// situation where a value is defined in a block, and the last use is a phi
66 /// node in the successor. In this case, DefInst will be the defining
67 /// instruction, AliveBlocks is empty (the value is not live across any
68 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
69 /// because the value must be live to the end of the block, but is not live in
70 /// any successor blocks.
72 /// DefInst - The machine instruction that defines this register.
74 MachineInstr *DefInst;
76 /// AliveBlocks - Set of blocks of which this value is alive completely
77 /// through. This is a bit set which uses the basic block number as an
80 BitVector AliveBlocks;
82 /// NumUses - Number of uses of this register across the entire function.
86 /// Kills - List of MachineInstruction's which are the last use of this
87 /// virtual register (kill it) in their basic block.
89 std::vector<MachineInstr*> Kills;
91 VarInfo() : DefInst(0), NumUses(0) {}
93 /// removeKill - Delete a kill corresponding to the specified
94 /// machine instruction. Returns true if there was a kill
95 /// corresponding to this instruction, false otherwise.
96 bool removeKill(MachineInstr *MI) {
97 for (std::vector<MachineInstr*>::iterator i = Kills.begin(),
98 e = Kills.end(); i != e; ++i)
110 /// VirtRegInfo - This list is a mapping from virtual register number to
111 /// variable information. FirstVirtualRegister is subtracted from the virtual
112 /// register number before indexing into this list.
114 std::vector<VarInfo> VirtRegInfo;
116 /// ReservedRegisters - This vector keeps track of which registers
117 /// are reserved register which are not allocatable by the target machine.
118 /// We can not track liveness for values that are in this set.
120 BitVector ReservedRegisters;
122 private: // Intermediate data structures
125 const MRegisterInfo *RegInfo;
127 // PhysRegInfo - Keep track of which instruction was the last def/use of a
128 // physical register. This is a purely local property, because all physical
129 // register references as presumed dead across basic blocks.
130 std::vector<MachineInstr*> PhysRegInfo;
132 // PhysRegUsed - Keep track whether the physical register has been used after
133 // its last definition. This is local property.
134 BitVector PhysRegUsed;
136 // PhysRegPartDef - Keep track of a list of instructions which "partially"
137 // defined the physical register (e.g. on X86 AX partially defines EAX).
138 // These are turned into use/mod/write if there is a use of the register
139 // later in the same block. This is local property.
140 std::vector<std::vector<MachineInstr*> > PhysRegPartDef;
142 // PhysRegPartUse - Keep track of which instruction was the last partial use
143 // of a physical register (e.g. on X86 a def of EAX followed by a use of AX).
144 // This is a purely local property.
145 std::vector<MachineInstr*> PhysRegPartUse;
147 typedef std::map<const MachineBasicBlock*,
148 std::vector<unsigned> > PHIVarInfoMap;
150 PHIVarInfoMap PHIVarInfo;
153 /// addRegisterKilled - We have determined MI kills a register. Look for the
154 /// operand that uses it and mark it as IsKill.
155 void addRegisterKilled(unsigned IncomingReg, MachineInstr *MI);
157 /// addRegisterDead - We have determined MI defined a register without a use.
158 /// Look for the operand that defines it and mark it as IsDead.
159 void addRegisterDead(unsigned IncomingReg, MachineInstr *MI);
161 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
162 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
164 /// analyzePHINodes - Gather information about the PHI nodes in here. In
165 /// particular, we want to map the variable information of a virtual
166 /// register which is used in a PHI node. We map that to the BB the vreg
168 void analyzePHINodes(const MachineFunction& Fn);
171 virtual bool runOnMachineFunction(MachineFunction &MF);
173 /// KillsRegister - Return true if the specified instruction kills the
174 /// specified register.
175 bool KillsRegister(MachineInstr *MI, unsigned Reg) const;
177 /// RegisterDefIsDead - Return true if the specified instruction defines the
178 /// specified register, but that definition is dead.
179 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
181 /// ModifiesRegister - Return true if the specified instruction modifies the
182 /// specified register.
183 bool ModifiesRegister(MachineInstr *MI, unsigned Reg) const;
185 //===--------------------------------------------------------------------===//
186 // API to update live variable information
188 /// instructionChanged - When the address of an instruction changes, this
189 /// method should be called so that live variables can update its internal
190 /// data structures. This removes the records for OldMI, transfering them to
191 /// the records for NewMI.
192 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
194 /// addVirtualRegisterKilled - Add information about the fact that the
195 /// specified register is killed after being used by the specified
198 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI) {
199 addRegisterKilled(IncomingReg, MI);
200 getVarInfo(IncomingReg).Kills.push_back(MI);
203 /// removeVirtualRegisterKilled - Remove the specified virtual
204 /// register from the live variable information. Returns true if the
205 /// variable was marked as killed by the specified instruction,
207 bool removeVirtualRegisterKilled(unsigned reg,
208 MachineBasicBlock *MBB,
210 if (!getVarInfo(reg).removeKill(MI))
213 bool Removed = false;
214 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
215 MachineOperand &MO = MI->getOperand(i);
216 if (MO.isReg() && MO.isUse() && MO.getReg() == reg) {
223 assert(Removed && "Register is not used by this instruction!");
227 /// removeVirtualRegistersKilled - Remove all killed info for the specified
229 void removeVirtualRegistersKilled(MachineInstr *MI);
231 /// addVirtualRegisterDead - Add information about the fact that the specified
232 /// register is dead after being used by the specified instruction.
234 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI) {
235 addRegisterDead(IncomingReg, MI);
236 getVarInfo(IncomingReg).Kills.push_back(MI);
239 /// removeVirtualRegisterDead - Remove the specified virtual
240 /// register from the live variable information. Returns true if the
241 /// variable was marked dead at the specified instruction, false
243 bool removeVirtualRegisterDead(unsigned reg,
244 MachineBasicBlock *MBB,
246 if (!getVarInfo(reg).removeKill(MI))
249 bool Removed = false;
250 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
251 MachineOperand &MO = MI->getOperand(i);
252 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
258 assert(Removed && "Register is not defined by this instruction!");
262 /// removeVirtualRegistersDead - Remove all of the dead registers for the
263 /// specified instruction from the live variable information.
264 void removeVirtualRegistersDead(MachineInstr *MI);
266 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
267 AU.setPreservesAll();
270 virtual void releaseMemory() {
274 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
276 VarInfo &getVarInfo(unsigned RegIdx);
278 void MarkVirtRegAliveInBlock(VarInfo &VRInfo, MachineBasicBlock *BB);
279 void HandleVirtRegUse(VarInfo &VRInfo, MachineBasicBlock *MBB,
283 } // End llvm namespace