1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/SmallVector.h"
40 class TargetRegisterInfo;
42 class LiveVariables : public MachineFunctionPass {
44 static char ID; // Pass identification, replacement for typeid
45 LiveVariables() : MachineFunctionPass((intptr_t)&ID) {}
47 /// VarInfo - This represents the regions where a virtual register is live in
48 /// the program. We represent this with three different pieces of
49 /// information: the instruction that uniquely defines the value, the set of
50 /// blocks the instruction is live into and live out of, and the set of
51 /// non-phi instructions that are the last users of the value.
53 /// In the common case where a value is defined and killed in the same block,
54 /// DefInst is the defining inst, there is one killing instruction, and
55 /// AliveBlocks is empty.
57 /// Otherwise, the value is live out of the block. If the value is live
58 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
59 /// the liveness range ends are not included in AliveBlocks, instead being
60 /// captured by the Kills set. In these blocks, the value is live into the
61 /// block (unless the value is defined and killed in the same block) and lives
62 /// until the specified instruction. Note that there cannot ever be a value
63 /// whose Kills set contains two instructions from the same basic block.
65 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
66 /// value in one of its predecessor blocks, it is not listed in the kills set,
67 /// but does include the predecessor block in the AliveBlocks set (unless that
68 /// block also defines the value). This leads to the (perfectly sensical)
69 /// situation where a value is defined in a block, and the last use is a phi
70 /// node in the successor. In this case, DefInst will be the defining
71 /// instruction, AliveBlocks is empty (the value is not live across any
72 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
73 /// because the value must be live to the end of the block, but is not live in
74 /// any successor blocks.
76 /// DefInst - The machine instruction that defines this register.
78 MachineInstr *DefInst;
80 /// AliveBlocks - Set of blocks of which this value is alive completely
81 /// through. This is a bit set which uses the basic block number as an
84 BitVector AliveBlocks;
86 /// UsedBlocks - Set of blocks of which this value is actually used. This
87 /// is a bit set which uses the basic block number as an index.
90 /// NumUses - Number of uses of this register across the entire function.
94 /// Kills - List of MachineInstruction's which are the last use of this
95 /// virtual register (kill it) in their basic block.
97 std::vector<MachineInstr*> Kills;
99 VarInfo() : DefInst(0), NumUses(0) {}
101 /// removeKill - Delete a kill corresponding to the specified
102 /// machine instruction. Returns true if there was a kill
103 /// corresponding to this instruction, false otherwise.
104 bool removeKill(MachineInstr *MI) {
105 std::vector<MachineInstr*>::iterator
106 I = std::find(Kills.begin(), Kills.end(), MI);
107 if (I == Kills.end())
117 /// VirtRegInfo - This list is a mapping from virtual register number to
118 /// variable information. FirstVirtualRegister is subtracted from the virtual
119 /// register number before indexing into this list.
121 std::vector<VarInfo> VirtRegInfo;
123 /// ReservedRegisters - This vector keeps track of which registers
124 /// are reserved register which are not allocatable by the target machine.
125 /// We can not track liveness for values that are in this set.
127 BitVector ReservedRegisters;
129 private: // Intermediate data structures
132 const TargetRegisterInfo *TRI;
134 // PhysRegInfo - Keep track of which instruction was the last def/use of a
135 // physical register. This is a purely local property, because all physical
136 // register references are presumed dead across basic blocks.
137 MachineInstr **PhysRegInfo;
139 // PhysRegUsed - Keep track of whether the physical register has been used
140 // after its last definition. This is local property.
143 // PhysRegPartUse - Keep track of which instruction was the last partial use
144 // of a physical register (e.g. on X86 a def of EAX followed by a use of AX).
145 // This is a purely local property.
146 MachineInstr **PhysRegPartUse;
148 // PhysRegPartDef - Keep track of a list of instructions which "partially"
149 // defined the physical register (e.g. on X86 AX partially defines EAX).
150 // These are turned into use/mod/write if there is a use of the register
151 // later in the same block. This is local property.
152 SmallVector<MachineInstr*, 4> *PhysRegPartDef;
154 SmallVector<unsigned, 4> *PHIVarInfo;
156 void addRegisterKills(unsigned Reg, MachineInstr *MI,
157 SmallSet<unsigned, 4> &SubKills);
159 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
160 /// uses. Pay special attention to the sub-register uses which may come below
161 /// the last use of the whole register.
162 bool HandlePhysRegKill(unsigned Reg, const MachineInstr *MI,
163 SmallSet<unsigned, 4> &SubKills);
164 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
165 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
166 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
168 /// analyzePHINodes - Gather information about the PHI nodes in here. In
169 /// particular, we want to map the variable information of a virtual
170 /// register which is used in a PHI node. We map that to the BB the vreg
172 void analyzePHINodes(const MachineFunction& Fn);
175 virtual bool runOnMachineFunction(MachineFunction &MF);
177 /// RegisterDefIsDead - Return true if the specified instruction defines the
178 /// specified register, but that definition is dead.
179 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
181 //===--------------------------------------------------------------------===//
182 // API to update live variable information
184 /// instructionChanged - When the address of an instruction changes, this
185 /// method should be called so that live variables can update its internal
186 /// data structures. This removes the records for OldMI, transfering them to
187 /// the records for NewMI.
188 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
190 /// addVirtualRegisterKilled - Add information about the fact that the
191 /// specified register is killed after being used by the specified
192 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
194 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
195 bool AddIfNotFound = false) {
196 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
197 getVarInfo(IncomingReg).Kills.push_back(MI);
200 /// removeVirtualRegisterKilled - Remove the specified virtual
201 /// register from the live variable information. Returns true if the
202 /// variable was marked as killed by the specified instruction,
204 bool removeVirtualRegisterKilled(unsigned reg,
205 MachineBasicBlock *MBB,
207 if (!getVarInfo(reg).removeKill(MI))
210 bool Removed = false;
211 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
212 MachineOperand &MO = MI->getOperand(i);
213 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
220 assert(Removed && "Register is not used by this instruction!");
224 /// removeVirtualRegistersKilled - Remove all killed info for the specified
226 void removeVirtualRegistersKilled(MachineInstr *MI);
228 /// addVirtualRegisterDead - Add information about the fact that the specified
229 /// register is dead after being used by the specified instruction. If
230 /// AddIfNotFound is true, add a implicit operand if it's not found.
231 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
232 bool AddIfNotFound = false) {
233 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
234 getVarInfo(IncomingReg).Kills.push_back(MI);
237 /// removeVirtualRegisterDead - Remove the specified virtual
238 /// register from the live variable information. Returns true if the
239 /// variable was marked dead at the specified instruction, false
241 bool removeVirtualRegisterDead(unsigned reg,
242 MachineBasicBlock *MBB,
244 if (!getVarInfo(reg).removeKill(MI))
247 bool Removed = false;
248 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
249 MachineOperand &MO = MI->getOperand(i);
250 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
256 assert(Removed && "Register is not defined by this instruction!");
260 /// removeVirtualRegistersDead - Remove all of the dead registers for the
261 /// specified instruction from the live variable information.
262 void removeVirtualRegistersDead(MachineInstr *MI);
264 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
265 AU.setPreservesAll();
268 virtual void releaseMemory() {
272 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
274 VarInfo &getVarInfo(unsigned RegIdx);
276 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
277 MachineBasicBlock *BB);
278 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
279 MachineBasicBlock *BB,
280 std::vector<MachineBasicBlock*> &WorkList);
281 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
285 } // End llvm namespace