1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineBasicBlock.h"
33 #include "llvm/CodeGen/MachineFunctionPass.h"
34 #include "llvm/CodeGen/MachineInstr.h"
35 #include "llvm/ADT/BitVector.h"
36 #include "llvm/ADT/DenseMap.h"
37 #include "llvm/ADT/SmallSet.h"
38 #include "llvm/ADT/SmallVector.h"
39 #include "llvm/ADT/SparseBitVector.h"
43 class MachineRegisterInfo;
44 class TargetRegisterInfo;
46 class LiveVariables : public MachineFunctionPass {
48 static char ID; // Pass identification, replacement for typeid
49 LiveVariables() : MachineFunctionPass(&ID) {}
51 /// VarInfo - This represents the regions where a virtual register is live in
52 /// the program. We represent this with three different pieces of
53 /// information: the set of blocks in which the instruction is live
54 /// throughout, the set of blocks in which the instruction is actually used,
55 /// and the set of non-phi instructions that are the last users of the value.
57 /// In the common case where a value is defined and killed in the same block,
58 /// There is one killing instruction, and AliveBlocks is empty.
60 /// Otherwise, the value is live out of the block. If the value is live
61 /// throughout any blocks, these blocks are listed in AliveBlocks. Blocks
62 /// where the liveness range ends are not included in AliveBlocks, instead
63 /// being captured by the Kills set. In these blocks, the value is live into
64 /// the block (unless the value is defined and killed in the same block) and
65 /// lives until the specified instruction. Note that there cannot ever be a
66 /// value whose Kills set contains two instructions from the same basic block.
68 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
69 /// value in one of its predecessor blocks, it is not listed in the kills set,
70 /// but does include the predecessor block in the AliveBlocks set (unless that
71 /// block also defines the value). This leads to the (perfectly sensical)
72 /// situation where a value is defined in a block, and the last use is a phi
73 /// node in the successor. In this case, AliveBlocks is empty (the value is
74 /// not live across any blocks) and Kills is empty (phi nodes are not
75 /// included). This is sensical because the value must be live to the end of
76 /// the block, but is not live in any successor blocks.
78 /// AliveBlocks - Set of blocks in which this value is alive completely
79 /// through. This is a bit set which uses the basic block number as an
82 SparseBitVector<> AliveBlocks;
84 /// NumUses - Number of uses of this register across the entire function.
88 /// Kills - List of MachineInstruction's which are the last use of this
89 /// virtual register (kill it) in their basic block.
91 std::vector<MachineInstr*> Kills;
93 VarInfo() : NumUses(0) {}
95 /// removeKill - Delete a kill corresponding to the specified
96 /// machine instruction. Returns true if there was a kill
97 /// corresponding to this instruction, false otherwise.
98 bool removeKill(MachineInstr *MI) {
99 std::vector<MachineInstr*>::iterator
100 I = std::find(Kills.begin(), Kills.end(), MI);
101 if (I == Kills.end())
111 /// VirtRegInfo - This list is a mapping from virtual register number to
112 /// variable information. FirstVirtualRegister is subtracted from the virtual
113 /// register number before indexing into this list.
115 std::vector<VarInfo> VirtRegInfo;
117 /// ReservedRegisters - This vector keeps track of which registers
118 /// are reserved register which are not allocatable by the target machine.
119 /// We can not track liveness for values that are in this set.
121 BitVector ReservedRegisters;
123 private: // Intermediate data structures
126 MachineRegisterInfo* MRI;
128 const TargetRegisterInfo *TRI;
130 // PhysRegInfo - Keep track of which instruction was the last def of a
131 // physical register. This is a purely local property, because all physical
132 // register references are presumed dead across basic blocks.
133 MachineInstr **PhysRegDef;
135 // PhysRegInfo - Keep track of which instruction was the last use of a
136 // physical register. This is a purely local property, because all physical
137 // register references are presumed dead across basic blocks.
138 MachineInstr **PhysRegUse;
140 SmallVector<unsigned, 4> *PHIVarInfo;
142 // DistanceMap - Keep track the distance of a MI from the start of the
143 // current basic block.
144 DenseMap<MachineInstr*, unsigned> DistanceMap;
146 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
147 /// uses. Pay special attention to the sub-register uses which may come below
148 /// the last use of the whole register.
149 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
151 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
152 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
153 SmallVector<unsigned, 4> &Defs,
154 SmallVector<unsigned, 4> &SuperDefs);
155 void UpdatePhysRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
156 void UpdateSuperRegDefs(MachineInstr *MI, SmallVector<unsigned, 4> &Defs);
158 /// FindLastPartialDef - Return the last partial def of the specified register.
159 /// Also returns the sub-registers that're defined by the instruction.
160 MachineInstr *FindLastPartialDef(unsigned Reg,
161 SmallSet<unsigned,4> &PartDefRegs);
163 /// hasRegisterUseBelow - Return true if the specified register is used after
164 /// the current instruction and before its next definition.
165 bool hasRegisterUseBelow(unsigned Reg, MachineBasicBlock::iterator I,
166 MachineBasicBlock *MBB);
168 /// analyzePHINodes - Gather information about the PHI nodes in here. In
169 /// particular, we want to map the variable information of a virtual
170 /// register which is used in a PHI node. We map that to the BB the vreg
172 void analyzePHINodes(const MachineFunction& Fn);
175 virtual bool runOnMachineFunction(MachineFunction &MF);
177 /// RegisterDefIsDead - Return true if the specified instruction defines the
178 /// specified register, but that definition is dead.
179 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
181 //===--------------------------------------------------------------------===//
182 // API to update live variable information
184 /// replaceKillInstruction - Update register kill info by replacing a kill
185 /// instruction with a new one.
186 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
187 MachineInstr *NewMI);
189 /// addVirtualRegisterKilled - Add information about the fact that the
190 /// specified register is killed after being used by the specified
191 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
193 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
194 bool AddIfNotFound = false) {
195 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
196 getVarInfo(IncomingReg).Kills.push_back(MI);
199 /// removeVirtualRegisterKilled - Remove the specified kill of the virtual
200 /// register from the live variable information. Returns true if the
201 /// variable was marked as killed by the specified instruction,
203 bool removeVirtualRegisterKilled(unsigned reg, MachineInstr *MI) {
204 if (!getVarInfo(reg).removeKill(MI))
207 bool Removed = false;
208 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
209 MachineOperand &MO = MI->getOperand(i);
210 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
217 assert(Removed && "Register is not used by this instruction!");
221 /// removeVirtualRegistersKilled - Remove all killed info for the specified
223 void removeVirtualRegistersKilled(MachineInstr *MI);
225 /// addVirtualRegisterDead - Add information about the fact that the specified
226 /// register is dead after being used by the specified instruction. If
227 /// AddIfNotFound is true, add a implicit operand if it's not found.
228 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
229 bool AddIfNotFound = false) {
230 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
231 getVarInfo(IncomingReg).Kills.push_back(MI);
234 /// removeVirtualRegisterDead - Remove the specified kill of the virtual
235 /// register from the live variable information. Returns true if the
236 /// variable was marked dead at the specified instruction, false
238 bool removeVirtualRegisterDead(unsigned reg, MachineInstr *MI) {
239 if (!getVarInfo(reg).removeKill(MI))
242 bool Removed = false;
243 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
244 MachineOperand &MO = MI->getOperand(i);
245 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
251 assert(Removed && "Register is not defined by this instruction!");
255 void getAnalysisUsage(AnalysisUsage &AU) const;
257 virtual void releaseMemory() {
261 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
263 VarInfo &getVarInfo(unsigned RegIdx);
265 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
266 MachineBasicBlock *BB);
267 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
268 MachineBasicBlock *BB,
269 std::vector<MachineBasicBlock*> &WorkList);
270 void HandleVirtRegDef(unsigned reg, MachineInstr *MI);
271 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
275 } // End llvm namespace