1 //===-- llvm/CodeGen/LiveVariables.h - Live Variable Analysis ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveVariables analysis pass. For each machine
11 // instruction in the function, this pass calculates the set of registers that
12 // are immediately dead after the instruction (i.e., the instruction calculates
13 // the value, but it is never used) and the set of registers that are used by
14 // the instruction, but are never used after the instruction (i.e., they are
17 // This class computes live variables using a sparse implementation based on
18 // the machine code SSA form. This class computes live variable information for
19 // each virtual and _register allocatable_ physical register in a function. It
20 // uses the dominance properties of SSA form to efficiently compute live
21 // variables for virtual registers, and assumes that physical registers are only
22 // live within a single basic block (allowing it to do a single local analysis
23 // to resolve physical register lifetimes in each basic block). If a physical
24 // register is not register allocatable, it is not tracked. This is useful for
25 // things like the stack pointer and condition codes.
27 //===----------------------------------------------------------------------===//
29 #ifndef LLVM_CODEGEN_LIVEVARIABLES_H
30 #define LLVM_CODEGEN_LIVEVARIABLES_H
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/ADT/BitVector.h"
34 #include "llvm/ADT/SmallSet.h"
35 #include "llvm/ADT/SmallVector.h"
39 class TargetRegisterInfo;
41 class LiveVariables : public MachineFunctionPass {
43 static char ID; // Pass identification, replacement for typeid
44 LiveVariables() : MachineFunctionPass((intptr_t)&ID) {}
46 /// VarInfo - This represents the regions where a virtual register is live in
47 /// the program. We represent this with three different pieces of
48 /// information: the instruction that uniquely defines the value, the set of
49 /// blocks the instruction is live into and live out of, and the set of
50 /// non-phi instructions that are the last users of the value.
52 /// In the common case where a value is defined and killed in the same block,
53 /// DefInst is the defining inst, there is one killing instruction, and
54 /// AliveBlocks is empty.
56 /// Otherwise, the value is live out of the block. If the value is live
57 /// across any blocks, these blocks are listed in AliveBlocks. Blocks where
58 /// the liveness range ends are not included in AliveBlocks, instead being
59 /// captured by the Kills set. In these blocks, the value is live into the
60 /// block (unless the value is defined and killed in the same block) and lives
61 /// until the specified instruction. Note that there cannot ever be a value
62 /// whose Kills set contains two instructions from the same basic block.
64 /// PHI nodes complicate things a bit. If a PHI node is the last user of a
65 /// value in one of its predecessor blocks, it is not listed in the kills set,
66 /// but does include the predecessor block in the AliveBlocks set (unless that
67 /// block also defines the value). This leads to the (perfectly sensical)
68 /// situation where a value is defined in a block, and the last use is a phi
69 /// node in the successor. In this case, DefInst will be the defining
70 /// instruction, AliveBlocks is empty (the value is not live across any
71 /// blocks) and Kills is empty (phi nodes are not included). This is sensical
72 /// because the value must be live to the end of the block, but is not live in
73 /// any successor blocks.
75 /// DefInst - The machine instruction that defines this register.
77 MachineInstr *DefInst;
79 /// AliveBlocks - Set of blocks of which this value is alive completely
80 /// through. This is a bit set which uses the basic block number as an
83 BitVector AliveBlocks;
85 /// UsedBlocks - Set of blocks of which this value is actually used. This
86 /// is a bit set which uses the basic block number as an index.
89 /// NumUses - Number of uses of this register across the entire function.
93 /// Kills - List of MachineInstruction's which are the last use of this
94 /// virtual register (kill it) in their basic block.
96 std::vector<MachineInstr*> Kills;
98 VarInfo() : DefInst(0), NumUses(0) {}
100 /// removeKill - Delete a kill corresponding to the specified
101 /// machine instruction. Returns true if there was a kill
102 /// corresponding to this instruction, false otherwise.
103 bool removeKill(MachineInstr *MI) {
104 std::vector<MachineInstr*>::iterator
105 I = std::find(Kills.begin(), Kills.end(), MI);
106 if (I == Kills.end())
116 /// VirtRegInfo - This list is a mapping from virtual register number to
117 /// variable information. FirstVirtualRegister is subtracted from the virtual
118 /// register number before indexing into this list.
120 std::vector<VarInfo> VirtRegInfo;
122 /// ReservedRegisters - This vector keeps track of which registers
123 /// are reserved register which are not allocatable by the target machine.
124 /// We can not track liveness for values that are in this set.
126 BitVector ReservedRegisters;
128 private: // Intermediate data structures
131 const TargetRegisterInfo *TRI;
133 // PhysRegInfo - Keep track of which instruction was the last def/use of a
134 // physical register. This is a purely local property, because all physical
135 // register references are presumed dead across basic blocks.
136 MachineInstr **PhysRegInfo;
138 // PhysRegUsed - Keep track of whether the physical register has been used
139 // after its last definition. This is local property.
142 // PhysRegPartUse - Keep track of which instruction was the last partial use
143 // of a physical register (e.g. on X86 a def of EAX followed by a use of AX).
144 // This is a purely local property.
145 MachineInstr **PhysRegPartUse;
147 // PhysRegPartDef - Keep track of a list of instructions which "partially"
148 // defined the physical register (e.g. on X86 AX partially defines EAX).
149 // These are turned into use/mod/write if there is a use of the register
150 // later in the same block. This is local property.
151 SmallVector<MachineInstr*, 4> *PhysRegPartDef;
153 SmallVector<unsigned, 4> *PHIVarInfo;
155 void addRegisterKills(unsigned Reg, MachineInstr *MI,
156 SmallSet<unsigned, 4> &SubKills);
158 /// HandlePhysRegKill - Add kills of Reg and its sub-registers to the
159 /// uses. Pay special attention to the sub-register uses which may come below
160 /// the last use of the whole register.
161 bool HandlePhysRegKill(unsigned Reg, const MachineInstr *MI,
162 SmallSet<unsigned, 4> &SubKills);
163 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
164 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
165 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI);
167 /// hasRegisterUseBelow - Return true if the specified register is used after
168 /// the current instruction and before it's next definition.
169 bool hasRegisterUseBelow(unsigned Reg,
170 MachineBasicBlock::iterator I,
171 MachineBasicBlock *MBB);
173 /// analyzePHINodes - Gather information about the PHI nodes in here. In
174 /// particular, we want to map the variable information of a virtual
175 /// register which is used in a PHI node. We map that to the BB the vreg
177 void analyzePHINodes(const MachineFunction& Fn);
180 virtual bool runOnMachineFunction(MachineFunction &MF);
182 /// RegisterDefIsDead - Return true if the specified instruction defines the
183 /// specified register, but that definition is dead.
184 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
186 //===--------------------------------------------------------------------===//
187 // API to update live variable information
189 /// instructionChanged - When the address of an instruction changes, this
190 /// method should be called so that live variables can update its internal
191 /// data structures. This removes the records for OldMI, transfering them to
192 /// the records for NewMI.
193 void instructionChanged(MachineInstr *OldMI, MachineInstr *NewMI);
195 /// addVirtualRegisterKilled - Add information about the fact that the
196 /// specified register is killed after being used by the specified
197 /// instruction. If AddIfNotFound is true, add a implicit operand if it's
199 void addVirtualRegisterKilled(unsigned IncomingReg, MachineInstr *MI,
200 bool AddIfNotFound = false) {
201 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
202 getVarInfo(IncomingReg).Kills.push_back(MI);
205 /// removeVirtualRegisterKilled - Remove the specified virtual
206 /// register from the live variable information. Returns true if the
207 /// variable was marked as killed by the specified instruction,
209 bool removeVirtualRegisterKilled(unsigned reg,
210 MachineBasicBlock *MBB,
212 if (!getVarInfo(reg).removeKill(MI))
215 bool Removed = false;
216 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
217 MachineOperand &MO = MI->getOperand(i);
218 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
225 assert(Removed && "Register is not used by this instruction!");
229 /// removeVirtualRegistersKilled - Remove all killed info for the specified
231 void removeVirtualRegistersKilled(MachineInstr *MI);
233 /// addVirtualRegisterDead - Add information about the fact that the specified
234 /// register is dead after being used by the specified instruction. If
235 /// AddIfNotFound is true, add a implicit operand if it's not found.
236 void addVirtualRegisterDead(unsigned IncomingReg, MachineInstr *MI,
237 bool AddIfNotFound = false) {
238 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
239 getVarInfo(IncomingReg).Kills.push_back(MI);
242 /// removeVirtualRegisterDead - Remove the specified virtual
243 /// register from the live variable information. Returns true if the
244 /// variable was marked dead at the specified instruction, false
246 bool removeVirtualRegisterDead(unsigned reg,
247 MachineBasicBlock *MBB,
249 if (!getVarInfo(reg).removeKill(MI))
252 bool Removed = false;
253 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
254 MachineOperand &MO = MI->getOperand(i);
255 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
261 assert(Removed && "Register is not defined by this instruction!");
265 /// removeVirtualRegistersDead - Remove all of the dead registers for the
266 /// specified instruction from the live variable information.
267 void removeVirtualRegistersDead(MachineInstr *MI);
269 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
270 AU.setPreservesAll();
273 virtual void releaseMemory() {
277 /// getVarInfo - Return the VarInfo structure for the specified VIRTUAL
279 VarInfo &getVarInfo(unsigned RegIdx);
281 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
282 MachineBasicBlock *BB);
283 void MarkVirtRegAliveInBlock(VarInfo& VRInfo, MachineBasicBlock* DefBlock,
284 MachineBasicBlock *BB,
285 std::vector<MachineBasicBlock*> &WorkList);
286 void HandleVirtRegUse(unsigned reg, MachineBasicBlock *MBB,
290 } // End llvm namespace