1 //===---- LiveRangeEdit.h - Basic tools for split and spill -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // The LiveRangeEdit class represents changes done to a virtual register when it
11 // is spilled or split.
13 // The parent register is never changed. Instead, a number of new virtual
14 // registers are created and added to the newRegs vector.
16 //===----------------------------------------------------------------------===//
18 #ifndef LLVM_CODEGEN_LIVERANGEEDIT_H
19 #define LLVM_CODEGEN_LIVERANGEEDIT_H
21 #include "llvm/ADT/ArrayRef.h"
22 #include "llvm/ADT/SetVector.h"
23 #include "llvm/ADT/SmallPtrSet.h"
24 #include "llvm/CodeGen/LiveInterval.h"
25 #include "llvm/Target/TargetMachine.h"
31 class MachineBlockFrequencyInfo;
32 class MachineLoopInfo;
37 /// Callback methods for LiveRangeEdit owners.
39 virtual void anchor();
41 /// Called immediately before erasing a dead machine instruction.
42 virtual void LRE_WillEraseInstruction(MachineInstr *MI) {}
44 /// Called when a virtual register is no longer used. Return false to defer
45 /// its deletion from LiveIntervals.
46 virtual bool LRE_CanEraseVirtReg(unsigned) { return true; }
48 /// Called before shrinking the live range of a virtual register.
49 virtual void LRE_WillShrinkVirtReg(unsigned) {}
51 /// Called after cloning a virtual register.
52 /// This is used for new registers representing connected components of Old.
53 virtual void LRE_DidCloneVirtReg(unsigned New, unsigned Old) {}
55 virtual ~Delegate() {}
60 SmallVectorImpl<unsigned> &NewRegs;
61 MachineRegisterInfo &MRI;
64 const TargetInstrInfo &TII;
65 Delegate *const TheDelegate;
67 /// FirstNew - Index of the first register added to NewRegs.
68 const unsigned FirstNew;
70 /// ScannedRemattable - true when remattable values have been identified.
71 bool ScannedRemattable;
73 /// Remattable - Values defined by remattable instructions as identified by
74 /// tii.isTriviallyReMaterializable().
75 SmallPtrSet<const VNInfo*,4> Remattable;
77 /// Rematted - Values that were actually rematted, and so need to have their
78 /// live range trimmed or entirely removed.
79 SmallPtrSet<const VNInfo*,4> Rematted;
81 /// scanRemattable - Identify the Parent values that may rematerialize.
82 void scanRemattable(AliasAnalysis *aa);
84 /// allUsesAvailableAt - Return true if all registers used by OrigMI at
85 /// OrigIdx are also available with the same value at UseIdx.
86 bool allUsesAvailableAt(const MachineInstr *OrigMI, SlotIndex OrigIdx,
87 SlotIndex UseIdx) const;
89 /// foldAsLoad - If LI has a single use and a single def that can be folded as
90 /// a load, eliminate the register by folding the def into the use.
91 bool foldAsLoad(LiveInterval *LI, SmallVectorImpl<MachineInstr*> &Dead);
93 typedef SetVector<LiveInterval*,
94 SmallVector<LiveInterval*, 8>,
95 SmallPtrSet<LiveInterval*, 8> > ToShrinkSet;
96 /// Helper for eliminateDeadDefs.
97 void eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink);
100 /// Create a LiveRangeEdit for breaking down parent into smaller pieces.
101 /// @param parent The register being spilled or split.
102 /// @param newRegs List to receive any new registers created. This needn't be
103 /// empty initially, any existing registers are ignored.
104 /// @param MF The MachineFunction the live range edit is taking place in.
105 /// @param lis The collection of all live intervals in this function.
106 /// @param vrm Map of virtual registers to physical registers for this
107 /// function. If NULL, no virtual register map updates will
108 /// be done. This could be the case if called before Regalloc.
109 LiveRangeEdit(LiveInterval *parent,
110 SmallVectorImpl<unsigned> &newRegs,
114 Delegate *delegate = 0)
115 : Parent(parent), NewRegs(newRegs),
116 MRI(MF.getRegInfo()), LIS(lis), VRM(vrm),
117 TII(*MF.getTarget().getInstrInfo()),
118 TheDelegate(delegate),
119 FirstNew(newRegs.size()),
120 ScannedRemattable(false) {}
122 LiveInterval &getParent() const {
123 assert(Parent && "No parent LiveInterval");
126 unsigned getReg() const { return getParent().reg; }
128 /// Iterator for accessing the new registers added by this edit.
129 typedef SmallVectorImpl<unsigned>::const_iterator iterator;
130 iterator begin() const { return NewRegs.begin()+FirstNew; }
131 iterator end() const { return NewRegs.end(); }
132 unsigned size() const { return NewRegs.size()-FirstNew; }
133 bool empty() const { return size() == 0; }
134 unsigned get(unsigned idx) const { return NewRegs[idx+FirstNew]; }
136 ArrayRef<unsigned> regs() const {
137 return makeArrayRef(NewRegs).slice(FirstNew);
140 /// createFrom - Create a new virtual register based on OldReg.
141 LiveInterval &createFrom(unsigned OldReg);
143 /// create - Create a new register with the same class and original slot as
145 LiveInterval &create() {
146 return createFrom(getReg());
149 /// anyRematerializable - Return true if any parent values may be
150 /// rematerializable.
151 /// This function must be called before any rematerialization is attempted.
152 bool anyRematerializable(AliasAnalysis*);
154 /// checkRematerializable - Manually add VNI to the list of rematerializable
155 /// values if DefMI may be rematerializable.
156 bool checkRematerializable(VNInfo *VNI, const MachineInstr *DefMI,
159 /// Remat - Information needed to rematerialize at a specific location.
161 VNInfo *ParentVNI; // parent_'s value at the remat location.
162 MachineInstr *OrigMI; // Instruction defining ParentVNI.
163 explicit Remat(VNInfo *ParentVNI) : ParentVNI(ParentVNI), OrigMI(0) {}
166 /// canRematerializeAt - Determine if ParentVNI can be rematerialized at
167 /// UseIdx. It is assumed that parent_.getVNINfoAt(UseIdx) == ParentVNI.
168 /// When cheapAsAMove is set, only cheap remats are allowed.
169 bool canRematerializeAt(Remat &RM,
173 /// rematerializeAt - Rematerialize RM.ParentVNI into DestReg by inserting an
174 /// instruction into MBB before MI. The new instruction is mapped, but
175 /// liveness is not updated.
176 /// Return the SlotIndex of the new instruction.
177 SlotIndex rematerializeAt(MachineBasicBlock &MBB,
178 MachineBasicBlock::iterator MI,
181 const TargetRegisterInfo&,
184 /// markRematerialized - explicitly mark a value as rematerialized after doing
186 void markRematerialized(const VNInfo *ParentVNI) {
187 Rematted.insert(ParentVNI);
190 /// didRematerialize - Return true if ParentVNI was rematerialized anywhere.
191 bool didRematerialize(const VNInfo *ParentVNI) const {
192 return Rematted.count(ParentVNI);
195 /// eraseVirtReg - Notify the delegate that Reg is no longer in use, and try
196 /// to erase it from LIS.
197 void eraseVirtReg(unsigned Reg);
199 /// eliminateDeadDefs - Try to delete machine instructions that are now dead
200 /// (allDefsAreDead returns true). This may cause live intervals to be trimmed
201 /// and further dead efs to be eliminated.
202 /// RegsBeingSpilled lists registers currently being spilled by the register
203 /// allocator. These registers should not be split into new intervals
204 /// as currently those new intervals are not guaranteed to spill.
205 void eliminateDeadDefs(SmallVectorImpl<MachineInstr*> &Dead,
206 ArrayRef<unsigned> RegsBeingSpilled = None);
208 /// calculateRegClassAndHint - Recompute register class and hint for each new
210 void calculateRegClassAndHint(MachineFunction&,
211 const MachineLoopInfo&,
212 const MachineBlockFrequencyInfo&);