1 //===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the LiveInterval analysis pass. Given some numbering of
11 // each the machine instructions (in this implemention depth-first order) an
12 // interval [i, j) is said to be a live interval for register v if there is no
13 // instruction with number j' > j such that v is live at j' and there is no
14 // instruction with number i' < i such that v is live at i'. In this
15 // implementation intervals can have holes, i.e. an interval might look like
16 // [1,20), [50,65), [1000,1001).
18 //===----------------------------------------------------------------------===//
20 #ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
21 #define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
23 #include "llvm/Target/TargetRegisterInfo.h"
24 #include "llvm/CodeGen/MachineBasicBlock.h"
25 #include "llvm/CodeGen/MachineFunctionPass.h"
26 #include "llvm/CodeGen/LiveInterval.h"
27 #include "llvm/CodeGen/SlotIndexes.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/IndexedMap.h"
30 #include "llvm/ADT/SmallPtrSet.h"
31 #include "llvm/ADT/SmallVector.h"
32 #include "llvm/Support/Allocator.h"
41 class MachineDominatorTree;
42 class MachineLoopInfo;
43 class TargetRegisterInfo;
44 class MachineRegisterInfo;
45 class TargetInstrInfo;
46 class TargetRegisterClass;
49 class LiveIntervals : public MachineFunctionPass {
51 MachineRegisterInfo* MRI;
52 const TargetMachine* TM;
53 const TargetRegisterInfo* TRI;
54 const TargetInstrInfo* TII;
58 MachineDominatorTree *DomTree;
59 LiveRangeCalc *LRCalc;
61 /// Special pool allocator for VNInfo's (LiveInterval val#).
63 VNInfo::Allocator VNInfoAllocator;
65 /// Live interval pointers for all the virtual registers.
66 IndexedMap<LiveInterval*, VirtReg2IndexFunctor> VirtRegIntervals;
68 /// AllocatableRegs - A bit vector of allocatable registers.
69 BitVector AllocatableRegs;
71 /// ReservedRegs - A bit vector of reserved registers.
72 BitVector ReservedRegs;
74 /// RegMaskSlots - Sorted list of instructions with register mask operands.
75 /// Always use the 'r' slot, RegMasks are normal clobbers, not early
77 SmallVector<SlotIndex, 8> RegMaskSlots;
79 /// RegMaskBits - This vector is parallel to RegMaskSlots, it holds a
80 /// pointer to the corresponding register mask. This pointer can be
83 /// MI = Indexes->getInstructionFromIndex(RegMaskSlot[N]);
84 /// unsigned OpNum = findRegMaskOperand(MI);
85 /// RegMaskBits[N] = MI->getOperand(OpNum).getRegMask();
87 /// This is kept in a separate vector partly because some standard
88 /// libraries don't support lower_bound() with mixed objects, partly to
89 /// improve locality when searching in RegMaskSlots.
90 /// Also see the comment in LiveInterval::find().
91 SmallVector<const uint32_t*, 8> RegMaskBits;
93 /// For each basic block number, keep (begin, size) pairs indexing into the
94 /// RegMaskSlots and RegMaskBits arrays.
95 /// Note that basic block numbers may not be layout contiguous, that's why
96 /// we can't just keep track of the first register mask in each basic
98 SmallVector<std::pair<unsigned, unsigned>, 8> RegMaskBlocks;
100 /// RegUnitIntervals - Keep a live interval for each register unit as a way
101 /// of tracking fixed physreg interference.
102 SmallVector<LiveInterval*, 0> RegUnitIntervals;
105 static char ID; // Pass identification, replacement for typeid
107 virtual ~LiveIntervals();
109 // Calculate the spill weight to assign to a single instruction.
110 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
112 LiveInterval &getInterval(unsigned Reg) {
113 LiveInterval *LI = VirtRegIntervals[Reg];
114 assert(LI && "Interval does not exist for virtual register");
118 const LiveInterval &getInterval(unsigned Reg) const {
119 return const_cast<LiveIntervals*>(this)->getInterval(Reg);
122 bool hasInterval(unsigned Reg) const {
123 return VirtRegIntervals.inBounds(Reg) && VirtRegIntervals[Reg];
126 /// isAllocatable - is the physical register reg allocatable in the current
128 bool isAllocatable(unsigned reg) const {
129 return AllocatableRegs.test(reg);
132 /// isReserved - is the physical register reg reserved in the current
134 bool isReserved(unsigned reg) const {
135 return ReservedRegs.test(reg);
138 // Interval creation.
139 LiveInterval &getOrCreateInterval(unsigned Reg) {
140 if (!hasInterval(Reg)) {
141 VirtRegIntervals.grow(Reg);
142 VirtRegIntervals[Reg] = createInterval(Reg);
144 return getInterval(Reg);
148 void removeInterval(unsigned Reg) {
149 delete VirtRegIntervals[Reg];
150 VirtRegIntervals[Reg] = 0;
153 /// addLiveRangeToEndOfBlock - Given a register and an instruction,
154 /// adds a live range from that instruction to the end of its MBB.
155 LiveRange addLiveRangeToEndOfBlock(unsigned reg,
156 MachineInstr* startInst);
158 /// shrinkToUses - After removing some uses of a register, shrink its live
159 /// range to just the remaining uses. This method does not compute reaching
160 /// defs for new uses, and it doesn't remove dead defs.
161 /// Dead PHIDef values are marked as unused.
162 /// New dead machine instructions are added to the dead vector.
163 /// Return true if the interval may have been separated into multiple
164 /// connected components.
165 bool shrinkToUses(LiveInterval *li,
166 SmallVectorImpl<MachineInstr*> *dead = 0);
168 SlotIndexes *getSlotIndexes() const {
172 AliasAnalysis *getAliasAnalysis() const {
176 /// isNotInMIMap - returns true if the specified machine instr has been
177 /// removed or was never entered in the map.
178 bool isNotInMIMap(const MachineInstr* Instr) const {
179 return !Indexes->hasIndex(Instr);
182 /// Returns the base index of the given instruction.
183 SlotIndex getInstructionIndex(const MachineInstr *instr) const {
184 return Indexes->getInstructionIndex(instr);
187 /// Returns the instruction associated with the given index.
188 MachineInstr* getInstructionFromIndex(SlotIndex index) const {
189 return Indexes->getInstructionFromIndex(index);
192 /// Return the first index in the given basic block.
193 SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
194 return Indexes->getMBBStartIdx(mbb);
197 /// Return the last index in the given basic block.
198 SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
199 return Indexes->getMBBEndIdx(mbb);
202 bool isLiveInToMBB(const LiveInterval &li,
203 const MachineBasicBlock *mbb) const {
204 return li.liveAt(getMBBStartIdx(mbb));
207 bool isLiveOutOfMBB(const LiveInterval &li,
208 const MachineBasicBlock *mbb) const {
209 return li.liveAt(getMBBEndIdx(mbb).getPrevSlot());
212 MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
213 return Indexes->getMBBFromIndex(index);
216 SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
217 return Indexes->insertMachineInstrInMaps(MI);
220 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
221 Indexes->removeMachineInstrFromMaps(MI);
224 void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
225 Indexes->replaceMachineInstrInMaps(MI, NewMI);
228 bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
229 SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
230 return Indexes->findLiveInMBBs(Start, End, MBBs);
233 VNInfo::Allocator& getVNInfoAllocator() { return VNInfoAllocator; }
235 virtual void getAnalysisUsage(AnalysisUsage &AU) const;
236 virtual void releaseMemory();
238 /// runOnMachineFunction - pass entry point
239 virtual bool runOnMachineFunction(MachineFunction&);
241 /// print - Implement the dump method.
242 virtual void print(raw_ostream &O, const Module* = 0) const;
244 /// intervalIsInOneMBB - If LI is confined to a single basic block, return
245 /// a pointer to that block. If LI is live in to or out of any block,
247 MachineBasicBlock *intervalIsInOneMBB(const LiveInterval &LI) const;
249 /// addKillFlags - Add kill flags to any instruction that kills a virtual
253 /// handleMove - call this method to notify LiveIntervals that
254 /// instruction 'mi' has been moved within a basic block. This will update
255 /// the live intervals for all operands of mi. Moves between basic blocks
256 /// are not supported.
257 void handleMove(MachineInstr* MI);
259 /// moveIntoBundle - Update intervals for operands of MI so that they
260 /// begin/end on the SlotIndex for BundleStart.
262 /// Requires MI and BundleStart to have SlotIndexes, and assumes
263 /// existing liveness is accurate. BundleStart should be the first
264 /// instruction in the Bundle.
265 void handleMoveIntoBundle(MachineInstr* MI, MachineInstr* BundleStart);
267 // Register mask functions.
269 // Machine instructions may use a register mask operand to indicate that a
270 // large number of registers are clobbered by the instruction. This is
271 // typically used for calls.
273 // For compile time performance reasons, these clobbers are not recorded in
274 // the live intervals for individual physical registers. Instead,
275 // LiveIntervalAnalysis maintains a sorted list of instructions with
276 // register mask operands.
278 /// getRegMaskSlots - Returns a sorted array of slot indices of all
279 /// instructions with register mask operands.
280 ArrayRef<SlotIndex> getRegMaskSlots() const { return RegMaskSlots; }
282 /// getRegMaskSlotsInBlock - Returns a sorted array of slot indices of all
283 /// instructions with register mask operands in the basic block numbered
285 ArrayRef<SlotIndex> getRegMaskSlotsInBlock(unsigned MBBNum) const {
286 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
287 return getRegMaskSlots().slice(P.first, P.second);
290 /// getRegMaskBits() - Returns an array of register mask pointers
291 /// corresponding to getRegMaskSlots().
292 ArrayRef<const uint32_t*> getRegMaskBits() const { return RegMaskBits; }
294 /// getRegMaskBitsInBlock - Returns an array of mask pointers corresponding
295 /// to getRegMaskSlotsInBlock(MBBNum).
296 ArrayRef<const uint32_t*> getRegMaskBitsInBlock(unsigned MBBNum) const {
297 std::pair<unsigned, unsigned> P = RegMaskBlocks[MBBNum];
298 return getRegMaskBits().slice(P.first, P.second);
301 /// checkRegMaskInterference - Test if LI is live across any register mask
302 /// instructions, and compute a bit mask of physical registers that are not
303 /// clobbered by any of them.
305 /// Returns false if LI doesn't cross any register mask instructions. In
306 /// that case, the bit vector is not filled in.
307 bool checkRegMaskInterference(LiveInterval &LI,
308 BitVector &UsableRegs);
310 // Register unit functions.
312 // Fixed interference occurs when MachineInstrs use physregs directly
313 // instead of virtual registers. This typically happens when passing
314 // arguments to a function call, or when instructions require operands in
317 // Each physreg has one or more register units, see MCRegisterInfo. We
318 // track liveness per register unit to handle aliasing registers more
321 /// getRegUnit - Return the live range for Unit.
322 /// It will be computed if it doesn't exist.
323 LiveInterval &getRegUnit(unsigned Unit) {
324 LiveInterval *LI = RegUnitIntervals[Unit];
326 // Compute missing ranges on demand.
327 RegUnitIntervals[Unit] = LI = new LiveInterval(Unit, HUGE_VALF);
328 computeRegUnitInterval(LI);
333 /// getCachedRegUnit - Return the live range for Unit if it has already
334 /// been computed, or NULL if it hasn't been computed yet.
335 LiveInterval *getCachedRegUnit(unsigned Unit) {
336 return RegUnitIntervals[Unit];
340 /// computeIntervals - Compute live intervals.
341 void computeIntervals();
343 /// Compute live intervals for all virtual registers.
344 void computeVirtRegs();
346 /// Compute RegMaskSlots and RegMaskBits.
347 void computeRegMasks();
349 /// handleRegisterDef - update intervals for a register def
350 /// (calls handleVirtualRegisterDef)
351 void handleRegisterDef(MachineBasicBlock *MBB,
352 MachineBasicBlock::iterator MI,
354 MachineOperand& MO, unsigned MOIdx);
356 /// isPartialRedef - Return true if the specified def at the specific index
357 /// is partially re-defining the specified live interval. A common case of
358 /// this is a definition of the sub-register.
359 bool isPartialRedef(SlotIndex MIIdx, MachineOperand &MO,
360 LiveInterval &interval);
362 /// handleVirtualRegisterDef - update intervals for a virtual
364 void handleVirtualRegisterDef(MachineBasicBlock *MBB,
365 MachineBasicBlock::iterator MI,
366 SlotIndex MIIdx, MachineOperand& MO,
368 LiveInterval& interval);
370 static LiveInterval* createInterval(unsigned Reg);
372 void printInstrs(raw_ostream &O) const;
373 void dumpInstrs() const;
375 void computeLiveInRegUnits();
376 void computeRegUnitInterval(LiveInterval*);
377 void computeVirtRegInterval(LiveInterval*);
381 } // End llvm namespace