1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
18 #include "llvm/ADT/SmallSet.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 class MachineBasicBlock;
27 class MachineConstantPool;
28 class MachineFunction;
29 class MachineFrameInfo;
30 class MachineModuleInfo;
31 class MachineRegisterInfo;
33 class TargetInstrInfo;
36 class TargetRegisterClass;
38 /// FastISel - This is a fast-path instruction selection class that
39 /// generates poor code and doesn't support illegal types or non-trivial
40 /// lowering, but runs quickly.
43 MachineBasicBlock *MBB;
44 DenseMap<const Value *, unsigned> LocalValueMap;
45 DenseMap<const Value *, unsigned> &ValueMap;
46 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
47 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
49 SmallSet<Instruction*, 8> &CatchInfoLost;
52 MachineModuleInfo *MMI;
53 MachineRegisterInfo &MRI;
54 MachineFrameInfo &MFI;
55 MachineConstantPool &MCP;
56 const TargetMachine &TM;
58 const TargetInstrInfo &TII;
59 const TargetLowering &TLI;
62 /// startNewBlock - Set the current block, to which generated
63 /// machine instructions will be appended, and clear the local
66 void startNewBlock(MachineBasicBlock *mbb) {
68 LocalValueMap.clear();
71 /// setCurrentBlock - Set the current block, to which generated
72 /// machine instructions will be appended.
74 void setCurrentBlock(MachineBasicBlock *mbb) {
78 /// SelectInstruction - Do "fast" instruction selection for the given
79 /// LLVM IR instruction, and append generated machine instructions to
80 /// the current block. Return true if selection was successful.
82 bool SelectInstruction(Instruction *I);
84 /// SelectInstruction - Do "fast" instruction selection for the given
85 /// LLVM IR operator (Instruction or ConstantExpr), and append
86 /// generated machine instructions to the current block. Return true
87 /// if selection was successful.
89 bool SelectOperator(User *I, unsigned Opcode);
91 /// TargetSelectInstruction - This method is called by target-independent
92 /// code when the normal FastISel process fails to select an instruction.
93 /// This gives targets a chance to emit code for anything that doesn't
94 /// fit into FastISel's framework. It returns true if it was successful.
97 TargetSelectInstruction(Instruction *I) = 0;
99 /// getRegForValue - Create a virtual register and arrange for it to
100 /// be assigned the value for the given LLVM value.
101 unsigned getRegForValue(Value *V);
103 /// lookUpRegForValue - Look up the value to see if its value is already
104 /// cached in a register. It may be defined by instructions across blocks or
106 unsigned lookUpRegForValue(Value *V);
108 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
109 /// takes care of truncating or sign-extending the given getelementptr
111 unsigned getRegForGEPIndex(Value *V);
116 FastISel(MachineFunction &mf,
117 MachineModuleInfo *mmi,
118 DenseMap<const Value *, unsigned> &vm,
119 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
120 DenseMap<const AllocaInst *, int> &am
122 , SmallSet<Instruction*, 8> &cil
126 /// FastEmit_r - This method is called by target-independent code
127 /// to request that an instruction with the given type and opcode
129 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
130 MVT::SimpleValueType RetVT,
131 ISD::NodeType Opcode);
133 /// FastEmit_r - This method is called by target-independent code
134 /// to request that an instruction with the given type, opcode, and
135 /// register operand be emitted.
137 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
138 MVT::SimpleValueType RetVT,
139 ISD::NodeType Opcode, unsigned Op0);
141 /// FastEmit_rr - This method is called by target-independent code
142 /// to request that an instruction with the given type, opcode, and
143 /// register operands be emitted.
145 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
146 MVT::SimpleValueType RetVT,
147 ISD::NodeType Opcode,
148 unsigned Op0, unsigned Op1);
150 /// FastEmit_ri - This method is called by target-independent code
151 /// to request that an instruction with the given type, opcode, and
152 /// register and immediate operands be emitted.
154 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
155 MVT::SimpleValueType RetVT,
156 ISD::NodeType Opcode,
157 unsigned Op0, uint64_t Imm);
159 /// FastEmit_rf - This method is called by target-independent code
160 /// to request that an instruction with the given type, opcode, and
161 /// register and floating-point immediate operands be emitted.
163 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
164 MVT::SimpleValueType RetVT,
165 ISD::NodeType Opcode,
166 unsigned Op0, ConstantFP *FPImm);
168 /// FastEmit_rri - This method is called by target-independent code
169 /// to request that an instruction with the given type, opcode, and
170 /// register and immediate operands be emitted.
172 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
173 MVT::SimpleValueType RetVT,
174 ISD::NodeType Opcode,
175 unsigned Op0, unsigned Op1, uint64_t Imm);
177 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
178 /// to emit an instruction with an immediate operand using FastEmit_ri.
179 /// If that fails, it materializes the immediate into a register and try
180 /// FastEmit_rr instead.
181 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
182 ISD::NodeType Opcode,
183 unsigned Op0, uint64_t Imm,
184 MVT::SimpleValueType ImmType);
186 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
187 /// to emit an instruction with an immediate operand using FastEmit_rf.
188 /// If that fails, it materializes the immediate into a register and try
189 /// FastEmit_rr instead.
190 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
191 ISD::NodeType Opcode,
192 unsigned Op0, ConstantFP *FPImm,
193 MVT::SimpleValueType ImmType);
195 /// FastEmit_i - This method is called by target-independent code
196 /// to request that an instruction with the given type, opcode, and
197 /// immediate operand be emitted.
198 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
199 MVT::SimpleValueType RetVT,
200 ISD::NodeType Opcode,
203 /// FastEmit_f - This method is called by target-independent code
204 /// to request that an instruction with the given type, opcode, and
205 /// floating-point immediate operand be emitted.
206 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
207 MVT::SimpleValueType RetVT,
208 ISD::NodeType Opcode,
211 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
212 /// result register in the given register class.
214 unsigned FastEmitInst_(unsigned MachineInstOpcode,
215 const TargetRegisterClass *RC);
217 /// FastEmitInst_r - Emit a MachineInstr with one register operand
218 /// and a result register in the given register class.
220 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
221 const TargetRegisterClass *RC,
224 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
225 /// and a result register in the given register class.
227 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
228 const TargetRegisterClass *RC,
229 unsigned Op0, unsigned Op1);
231 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
232 /// and a result register in the given register class.
234 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
235 const TargetRegisterClass *RC,
236 unsigned Op0, uint64_t Imm);
238 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
239 /// and a result register in the given register class.
241 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
242 const TargetRegisterClass *RC,
243 unsigned Op0, ConstantFP *FPImm);
245 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
246 /// an immediate, and a result register in the given register class.
248 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
249 const TargetRegisterClass *RC,
250 unsigned Op0, unsigned Op1, uint64_t Imm);
252 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
253 /// operand, and a result register in the given register class.
254 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
255 const TargetRegisterClass *RC,
258 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
259 /// from a specified index of a superregister.
260 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
262 /// FastEmitBranch - Emit an unconditional branch to the given block,
263 /// unless it is the immediate (fall-through) successor, and update
265 void FastEmitBranch(MachineBasicBlock *MBB);
267 void UpdateValueMap(Value* I, unsigned Reg);
269 unsigned createResultReg(const TargetRegisterClass *RC);
271 /// TargetMaterializeConstant - Emit a constant in a register using
272 /// target-specific logic, such as constant pool loads.
273 virtual unsigned TargetMaterializeConstant(Constant* C) {
277 /// TargetMaterializeAlloca - Emit an alloca address in a register using
278 /// target-specific logic.
279 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
284 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
286 bool SelectGetElementPtr(User *I);
288 bool SelectCall(User *I);
290 bool SelectBitCast(User *I);
292 bool SelectCast(User *I, ISD::NodeType Opcode);