1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
21 #include "llvm/CodeGen/ValueTypes.h"
28 class MachineBasicBlock;
29 class MachineConstantPool;
30 class MachineFunction;
31 class MachineFrameInfo;
32 class MachineRegisterInfo;
34 class TargetInstrInfo;
37 class TargetRegisterClass;
39 /// FastISel - This is a fast-path instruction selection class that
40 /// generates poor code and doesn't support illegal types or non-trivial
41 /// lowering, but runs quickly.
44 MachineBasicBlock *MBB;
45 DenseMap<const Value *, unsigned> LocalValueMap;
46 DenseMap<const Value *, unsigned> &ValueMap;
47 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
48 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
50 SmallSet<Instruction*, 8> &CatchInfoLost;
53 MachineRegisterInfo &MRI;
54 MachineFrameInfo &MFI;
55 MachineConstantPool &MCP;
57 const TargetMachine &TM;
59 const TargetInstrInfo &TII;
60 const TargetLowering &TLI;
63 /// startNewBlock - Set the current block to which generated machine
64 /// instructions will be appended, and clear the local CSE map.
66 void startNewBlock(MachineBasicBlock *mbb) {
68 LocalValueMap.clear();
71 /// setCurrentBlock - Set the current block to which generated machine
72 /// instructions will be appended.
74 void setCurrentBlock(MachineBasicBlock *mbb) {
78 /// setCurDebugLoc - Set the current debug location information, which is used
79 /// when creating a machine instruction.
81 void setCurDebugLoc(DebugLoc dl) { DL = dl; }
83 /// getCurDebugLoc() - Return current debug location information.
84 DebugLoc getCurDebugLoc() const { return DL; }
86 /// SelectInstruction - Do "fast" instruction selection for the given
87 /// LLVM IR instruction, and append generated machine instructions to
88 /// the current block. Return true if selection was successful.
90 bool SelectInstruction(Instruction *I);
92 /// SelectOperator - Do "fast" instruction selection for the given
93 /// LLVM IR operator (Instruction or ConstantExpr), and append
94 /// generated machine instructions to the current block. Return true
95 /// if selection was successful.
97 bool SelectOperator(User *I, unsigned Opcode);
99 /// getRegForValue - Create a virtual register and arrange for it to
100 /// be assigned the value for the given LLVM value.
101 unsigned getRegForValue(Value *V);
103 /// lookUpRegForValue - Look up the value to see if its value is already
104 /// cached in a register. It may be defined by instructions across blocks or
106 unsigned lookUpRegForValue(Value *V);
108 /// getRegForGEPIndex - This is a wrapper around getRegForValue that also
109 /// takes care of truncating or sign-extending the given getelementptr
111 unsigned getRegForGEPIndex(Value *V);
116 FastISel(MachineFunction &mf,
117 DenseMap<const Value *, unsigned> &vm,
118 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
119 DenseMap<const AllocaInst *, int> &am
121 , SmallSet<Instruction*, 8> &cil
125 /// TargetSelectInstruction - This method is called by target-independent
126 /// code when the normal FastISel process fails to select an instruction.
127 /// This gives targets a chance to emit code for anything that doesn't
128 /// fit into FastISel's framework. It returns true if it was successful.
131 TargetSelectInstruction(Instruction *I) = 0;
133 /// FastEmit_r - This method is called by target-independent code
134 /// to request that an instruction with the given type and opcode
136 virtual unsigned FastEmit_(MVT VT,
140 /// FastEmit_r - This method is called by target-independent code
141 /// to request that an instruction with the given type, opcode, and
142 /// register operand be emitted.
144 virtual unsigned FastEmit_r(MVT VT,
146 unsigned Opcode, unsigned Op0);
148 /// FastEmit_rr - This method is called by target-independent code
149 /// to request that an instruction with the given type, opcode, and
150 /// register operands be emitted.
152 virtual unsigned FastEmit_rr(MVT VT,
155 unsigned Op0, unsigned Op1);
157 /// FastEmit_ri - This method is called by target-independent code
158 /// to request that an instruction with the given type, opcode, and
159 /// register and immediate operands be emitted.
161 virtual unsigned FastEmit_ri(MVT VT,
164 unsigned Op0, uint64_t Imm);
166 /// FastEmit_rf - This method is called by target-independent code
167 /// to request that an instruction with the given type, opcode, and
168 /// register and floating-point immediate operands be emitted.
170 virtual unsigned FastEmit_rf(MVT VT,
173 unsigned Op0, ConstantFP *FPImm);
175 /// FastEmit_rri - This method is called by target-independent code
176 /// to request that an instruction with the given type, opcode, and
177 /// register and immediate operands be emitted.
179 virtual unsigned FastEmit_rri(MVT VT,
182 unsigned Op0, unsigned Op1, uint64_t Imm);
184 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
185 /// to emit an instruction with an immediate operand using FastEmit_ri.
186 /// If that fails, it materializes the immediate into a register and try
187 /// FastEmit_rr instead.
188 unsigned FastEmit_ri_(MVT VT,
190 unsigned Op0, uint64_t Imm,
193 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
194 /// to emit an instruction with an immediate operand using FastEmit_rf.
195 /// If that fails, it materializes the immediate into a register and try
196 /// FastEmit_rr instead.
197 unsigned FastEmit_rf_(MVT VT,
199 unsigned Op0, ConstantFP *FPImm,
202 /// FastEmit_i - This method is called by target-independent code
203 /// to request that an instruction with the given type, opcode, and
204 /// immediate operand be emitted.
205 virtual unsigned FastEmit_i(MVT VT,
210 /// FastEmit_f - This method is called by target-independent code
211 /// to request that an instruction with the given type, opcode, and
212 /// floating-point immediate operand be emitted.
213 virtual unsigned FastEmit_f(MVT VT,
218 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
219 /// result register in the given register class.
221 unsigned FastEmitInst_(unsigned MachineInstOpcode,
222 const TargetRegisterClass *RC);
224 /// FastEmitInst_r - Emit a MachineInstr with one register operand
225 /// and a result register in the given register class.
227 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
228 const TargetRegisterClass *RC,
231 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
232 /// and a result register in the given register class.
234 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
235 const TargetRegisterClass *RC,
236 unsigned Op0, unsigned Op1);
238 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
239 /// and a result register in the given register class.
241 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
242 const TargetRegisterClass *RC,
243 unsigned Op0, uint64_t Imm);
245 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
246 /// and a result register in the given register class.
248 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
249 const TargetRegisterClass *RC,
250 unsigned Op0, ConstantFP *FPImm);
252 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
253 /// an immediate, and a result register in the given register class.
255 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
256 const TargetRegisterClass *RC,
257 unsigned Op0, unsigned Op1, uint64_t Imm);
259 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
260 /// operand, and a result register in the given register class.
261 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
262 const TargetRegisterClass *RC,
265 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
266 /// from a specified index of a superregister to a specified type.
267 unsigned FastEmitInst_extractsubreg(MVT RetVT,
268 unsigned Op0, uint32_t Idx);
270 /// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
271 /// with all but the least significant bit set to zero.
272 unsigned FastEmitZExtFromI1(MVT VT,
275 /// FastEmitBranch - Emit an unconditional branch to the given block,
276 /// unless it is the immediate (fall-through) successor, and update
278 void FastEmitBranch(MachineBasicBlock *MBB);
280 unsigned UpdateValueMap(Value* I, unsigned Reg);
282 unsigned createResultReg(const TargetRegisterClass *RC);
284 /// TargetMaterializeConstant - Emit a constant in a register using
285 /// target-specific logic, such as constant pool loads.
286 virtual unsigned TargetMaterializeConstant(Constant* C) {
290 /// TargetMaterializeAlloca - Emit an alloca address in a register using
291 /// target-specific logic.
292 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
297 bool SelectBinaryOp(User *I, unsigned ISDOpcode);
299 bool SelectFNeg(User *I);
301 bool SelectGetElementPtr(User *I);
303 bool SelectCall(User *I);
305 bool SelectBitCast(User *I);
307 bool SelectCast(User *I, unsigned Opcode);