1 //===-- FastISel.h - Definition of the FastISel class ---------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the FastISel class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_CODEGEN_FASTISEL_H
15 #define LLVM_CODEGEN_FASTISEL_H
17 #include "llvm/BasicBlock.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/CodeGen/SelectionDAGNodes.h"
25 class MachineBasicBlock;
26 class MachineConstantPool;
27 class MachineFunction;
28 class MachineFrameInfo;
29 class MachineModuleInfo;
30 class MachineRegisterInfo;
32 class TargetInstrInfo;
35 class TargetRegisterClass;
37 /// FastISel - This is a fast-path instruction selection class that
38 /// generates poor code and doesn't support illegal types or non-trivial
39 /// lowering, but runs quickly.
42 MachineBasicBlock *MBB;
43 DenseMap<const Value *, unsigned> LocalValueMap;
44 DenseMap<const Value *, unsigned> &ValueMap;
45 DenseMap<const BasicBlock *, MachineBasicBlock *> &MBBMap;
46 DenseMap<const AllocaInst *, int> &StaticAllocaMap;
48 MachineModuleInfo *MMI;
49 MachineRegisterInfo &MRI;
50 MachineFrameInfo &MFI;
51 MachineConstantPool &MCP;
52 const TargetMachine &TM;
54 const TargetInstrInfo &TII;
55 const TargetLowering &TLI;
58 /// startNewBlock - Set the current block, to which generated
59 /// machine instructions will be appended, and clear the local
62 void startNewBlock(MachineBasicBlock *mbb) {
64 LocalValueMap.clear();
67 /// setCurrentBlock - Set the current block, to which generated
68 /// machine instructions will be appended.
70 void setCurrentBlock(MachineBasicBlock *mbb) {
74 /// SelectInstruction - Do "fast" instruction selection for the given
75 /// LLVM IR instruction, and append generated machine instructions to
76 /// the current block. Return true if selection was successful.
78 bool SelectInstruction(Instruction *I);
80 /// SelectInstruction - Do "fast" instruction selection for the given
81 /// LLVM IR operator (Instruction or ConstantExpr), and append
82 /// generated machine instructions to the current block. Return true
83 /// if selection was successful.
85 bool SelectOperator(User *I, unsigned Opcode);
87 /// TargetSelectInstruction - This method is called by target-independent
88 /// code when the normal FastISel process fails to select an instruction.
89 /// This gives targets a chance to emit code for anything that doesn't
90 /// fit into FastISel's framework. It returns true if it was successful.
93 TargetSelectInstruction(Instruction *I) = 0;
95 /// getRegForValue - Create a virtual register and arrange for it to
96 /// be assigned the value for the given LLVM value.
97 unsigned getRegForValue(Value *V);
99 /// lookUpRegForValue - Look up the value to see if its value is already
100 /// cached in a register. It may be defined by instructions across blocks or
102 unsigned lookUpRegForValue(Value *V);
107 FastISel(MachineFunction &mf,
108 MachineModuleInfo *mmi,
109 DenseMap<const Value *, unsigned> &vm,
110 DenseMap<const BasicBlock *, MachineBasicBlock *> &bm,
111 DenseMap<const AllocaInst *, int> &am);
113 /// FastEmit_r - This method is called by target-independent code
114 /// to request that an instruction with the given type and opcode
116 virtual unsigned FastEmit_(MVT::SimpleValueType VT,
117 MVT::SimpleValueType RetVT,
118 ISD::NodeType Opcode);
120 /// FastEmit_r - This method is called by target-independent code
121 /// to request that an instruction with the given type, opcode, and
122 /// register operand be emitted.
124 virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
125 MVT::SimpleValueType RetVT,
126 ISD::NodeType Opcode, unsigned Op0);
128 /// FastEmit_rr - This method is called by target-independent code
129 /// to request that an instruction with the given type, opcode, and
130 /// register operands be emitted.
132 virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
133 MVT::SimpleValueType RetVT,
134 ISD::NodeType Opcode,
135 unsigned Op0, unsigned Op1);
137 /// FastEmit_ri - This method is called by target-independent code
138 /// to request that an instruction with the given type, opcode, and
139 /// register and immediate operands be emitted.
141 virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
142 MVT::SimpleValueType RetVT,
143 ISD::NodeType Opcode,
144 unsigned Op0, uint64_t Imm);
146 /// FastEmit_rf - This method is called by target-independent code
147 /// to request that an instruction with the given type, opcode, and
148 /// register and floating-point immediate operands be emitted.
150 virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
151 MVT::SimpleValueType RetVT,
152 ISD::NodeType Opcode,
153 unsigned Op0, ConstantFP *FPImm);
155 /// FastEmit_rri - This method is called by target-independent code
156 /// to request that an instruction with the given type, opcode, and
157 /// register and immediate operands be emitted.
159 virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
160 MVT::SimpleValueType RetVT,
161 ISD::NodeType Opcode,
162 unsigned Op0, unsigned Op1, uint64_t Imm);
164 /// FastEmit_ri_ - This method is a wrapper of FastEmit_ri. It first tries
165 /// to emit an instruction with an immediate operand using FastEmit_ri.
166 /// If that fails, it materializes the immediate into a register and try
167 /// FastEmit_rr instead.
168 unsigned FastEmit_ri_(MVT::SimpleValueType VT,
169 ISD::NodeType Opcode,
170 unsigned Op0, uint64_t Imm,
171 MVT::SimpleValueType ImmType);
173 /// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
174 /// to emit an instruction with an immediate operand using FastEmit_rf.
175 /// If that fails, it materializes the immediate into a register and try
176 /// FastEmit_rr instead.
177 unsigned FastEmit_rf_(MVT::SimpleValueType VT,
178 ISD::NodeType Opcode,
179 unsigned Op0, ConstantFP *FPImm,
180 MVT::SimpleValueType ImmType);
182 /// FastEmit_i - This method is called by target-independent code
183 /// to request that an instruction with the given type, opcode, and
184 /// immediate operand be emitted.
185 virtual unsigned FastEmit_i(MVT::SimpleValueType VT,
186 MVT::SimpleValueType RetVT,
187 ISD::NodeType Opcode,
190 /// FastEmit_f - This method is called by target-independent code
191 /// to request that an instruction with the given type, opcode, and
192 /// floating-point immediate operand be emitted.
193 virtual unsigned FastEmit_f(MVT::SimpleValueType VT,
194 MVT::SimpleValueType RetVT,
195 ISD::NodeType Opcode,
198 /// FastEmitInst_ - Emit a MachineInstr with no operands and a
199 /// result register in the given register class.
201 unsigned FastEmitInst_(unsigned MachineInstOpcode,
202 const TargetRegisterClass *RC);
204 /// FastEmitInst_r - Emit a MachineInstr with one register operand
205 /// and a result register in the given register class.
207 unsigned FastEmitInst_r(unsigned MachineInstOpcode,
208 const TargetRegisterClass *RC,
211 /// FastEmitInst_rr - Emit a MachineInstr with two register operands
212 /// and a result register in the given register class.
214 unsigned FastEmitInst_rr(unsigned MachineInstOpcode,
215 const TargetRegisterClass *RC,
216 unsigned Op0, unsigned Op1);
218 /// FastEmitInst_ri - Emit a MachineInstr with two register operands
219 /// and a result register in the given register class.
221 unsigned FastEmitInst_ri(unsigned MachineInstOpcode,
222 const TargetRegisterClass *RC,
223 unsigned Op0, uint64_t Imm);
225 /// FastEmitInst_rf - Emit a MachineInstr with two register operands
226 /// and a result register in the given register class.
228 unsigned FastEmitInst_rf(unsigned MachineInstOpcode,
229 const TargetRegisterClass *RC,
230 unsigned Op0, ConstantFP *FPImm);
232 /// FastEmitInst_rri - Emit a MachineInstr with two register operands,
233 /// an immediate, and a result register in the given register class.
235 unsigned FastEmitInst_rri(unsigned MachineInstOpcode,
236 const TargetRegisterClass *RC,
237 unsigned Op0, unsigned Op1, uint64_t Imm);
239 /// FastEmitInst_i - Emit a MachineInstr with a single immediate
240 /// operand, and a result register in the given register class.
241 unsigned FastEmitInst_i(unsigned MachineInstrOpcode,
242 const TargetRegisterClass *RC,
245 /// FastEmitInst_extractsubreg - Emit a MachineInstr for an extract_subreg
246 /// from a specified index of a superregister.
247 unsigned FastEmitInst_extractsubreg(unsigned Op0, uint32_t Idx);
249 /// FastEmitBranch - Emit an unconditional branch to the given block,
250 /// unless it is the immediate (fall-through) successor, and update
252 void FastEmitBranch(MachineBasicBlock *MBB);
254 void UpdateValueMap(Value* I, unsigned Reg);
256 unsigned createResultReg(const TargetRegisterClass *RC);
258 /// TargetMaterializeConstant - Emit a constant in a register using
259 /// target-specific logic, such as constant pool loads.
260 virtual unsigned TargetMaterializeConstant(Constant* C) {
264 /// TargetMaterializeAlloca - Emit an alloca address in a register using
265 /// target-specific logic.
266 virtual unsigned TargetMaterializeAlloca(AllocaInst* C) {
271 bool SelectBinaryOp(User *I, ISD::NodeType ISDOpcode);
273 bool SelectGetElementPtr(User *I);
275 bool SelectCall(User *I);
277 bool SelectBitCast(User *I);
279 bool SelectCast(User *I, ISD::NodeType Opcode);