1 #ifndef _LINUX_SPI_CPCAP_H
2 #define _LINUX_SPI_CPCAP_H
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
21 #include <linux/ioctl.h>
23 #include <linux/workqueue.h>
24 #include <linux/completion.h>
25 #include <linux/power_supply.h>
26 #include <linux/platform_device.h>
29 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD
30 #include <linux/rtc.h>
33 #define CPCAP_DEV_NAME "cpcap"
34 #define CPCAP_NUM_REG_CPCAP (CPCAP_REG_END - CPCAP_REG_START + 1)
36 #define CPCAP_IRQ_INT1_INDEX 0
37 #define CPCAP_IRQ_INT2_INDEX 16
38 #define CPCAP_IRQ_INT3_INDEX 32
39 #define CPCAP_IRQ_INT4_INDEX 48
40 #define CPCAP_IRQ_INT5_INDEX 64
42 #define CPCAP_HWCFG_NUM 2 /* The number of hardware config words. */
44 * Tell the uC to setup the secondary standby bits for the regulators used.
46 #define CPCAP_HWCFG0_SEC_STBY_SW1 0x0001
47 #define CPCAP_HWCFG0_SEC_STBY_SW2 0x0002
48 #define CPCAP_HWCFG0_SEC_STBY_SW3 0x0004
49 #define CPCAP_HWCFG0_SEC_STBY_SW4 0x0008
50 #define CPCAP_HWCFG0_SEC_STBY_SW5 0x0010
51 #define CPCAP_HWCFG0_SEC_STBY_VAUDIO 0x0020
52 #define CPCAP_HWCFG0_SEC_STBY_VCAM 0x0040
53 #define CPCAP_HWCFG0_SEC_STBY_VCSI 0x0080
54 #define CPCAP_HWCFG0_SEC_STBY_VDAC 0x0100
55 #define CPCAP_HWCFG0_SEC_STBY_VDIG 0x0200
56 #define CPCAP_HWCFG0_SEC_STBY_VHVIO 0x0400
57 #define CPCAP_HWCFG0_SEC_STBY_VPLL 0x0800
58 #define CPCAP_HWCFG0_SEC_STBY_VRF1 0x1000
59 #define CPCAP_HWCFG0_SEC_STBY_VRF2 0x2000
60 #define CPCAP_HWCFG0_SEC_STBY_VRFREF 0x4000
61 #define CPCAP_HWCFG0_SEC_STBY_VSDIO 0x8000
63 #define CPCAP_HWCFG1_SEC_STBY_VWLAN1 0x0001
64 #define CPCAP_HWCFG1_SEC_STBY_VWLAN2 0x0002
65 #define CPCAP_HWCFG1_SEC_STBY_VSIM 0x0004
66 #define CPCAP_HWCFG1_SEC_STBY_VSIMCARD 0x0008
67 #define CPCAP_HWCFG1_SOFT_RESET_HOST 0x0010
69 #define CPCAP_WHISPER_MODE_PU 0x00000001
70 #define CPCAP_WHISPER_ENABLE_UART 0x00000002
71 #define CPCAP_WHISPER_ACCY_MASK 0xF8000000
72 #define CPCAP_WHISPER_ACCY_SHFT 27
73 #define CPCAP_WHISPER_ID_SIZE 16
74 #define CPCAP_WHISPER_PROP_SIZE 7
76 enum cpcap_regulator_id {
102 * Enumeration of all registers in the cpcap. Note that the register
103 * numbers on the CPCAP IC are not contiguous. The values of the enums below
104 * are not the actual register numbers.
107 CPCAP_REG_START, /* Start of CPCAP registers. */
109 CPCAP_REG_INT1 = CPCAP_REG_START, /* Interrupt 1 */
110 CPCAP_REG_INT2, /* Interrupt 2 */
111 CPCAP_REG_INT3, /* Interrupt 3 */
112 CPCAP_REG_INT4, /* Interrupt 4 */
113 CPCAP_REG_INTM1, /* Interrupt Mask 1 */
114 CPCAP_REG_INTM2, /* Interrupt Mask 2 */
115 CPCAP_REG_INTM3, /* Interrupt Mask 3 */
116 CPCAP_REG_INTM4, /* Interrupt Mask 4 */
117 CPCAP_REG_INTS1, /* Interrupt Sense 1 */
118 CPCAP_REG_INTS2, /* Interrupt Sense 2 */
119 CPCAP_REG_INTS3, /* Interrupt Sense 3 */
120 CPCAP_REG_INTS4, /* Interrupt Sense 4 */
121 CPCAP_REG_ASSIGN1, /* Resource Assignment 1 */
122 CPCAP_REG_ASSIGN2, /* Resource Assignment 2 */
123 CPCAP_REG_ASSIGN3, /* Resource Assignment 3 */
124 CPCAP_REG_ASSIGN4, /* Resource Assignment 4 */
125 CPCAP_REG_ASSIGN5, /* Resource Assignment 5 */
126 CPCAP_REG_ASSIGN6, /* Resource Assignment 6 */
127 CPCAP_REG_VERSC1, /* Version Control 1 */
128 CPCAP_REG_VERSC2, /* Version Control 2 */
130 CPCAP_REG_MI1, /* Macro Interrupt 1 */
131 CPCAP_REG_MIM1, /* Macro Interrupt Mask 1 */
132 CPCAP_REG_MI2, /* Macro Interrupt 2 */
133 CPCAP_REG_MIM2, /* Macro Interrupt Mask 2 */
134 CPCAP_REG_UCC1, /* UC Control 1 */
135 CPCAP_REG_UCC2, /* UC Control 2 */
136 CPCAP_REG_PC1, /* Power Cut 1 */
137 CPCAP_REG_PC2, /* Power Cut 2 */
138 CPCAP_REG_BPEOL, /* BP and EOL */
139 CPCAP_REG_PGC, /* Power Gate and Control */
140 CPCAP_REG_MT1, /* Memory Transfer 1 */
141 CPCAP_REG_MT2, /* Memory Transfer 2 */
142 CPCAP_REG_MT3, /* Memory Transfer 3 */
143 CPCAP_REG_PF, /* Print Format */
145 CPCAP_REG_SCC, /* System Clock Control */
146 CPCAP_REG_SW1, /* Stop Watch 1 */
147 CPCAP_REG_SW2, /* Stop Watch 2 */
148 CPCAP_REG_UCTM, /* UC Turbo Mode */
149 CPCAP_REG_TOD1, /* Time of Day 1 */
150 CPCAP_REG_TOD2, /* Time of Day 2 */
151 CPCAP_REG_TODA1, /* Time of Day Alarm 1 */
152 CPCAP_REG_TODA2, /* Time of Day Alarm 2 */
153 CPCAP_REG_DAY, /* Day */
154 CPCAP_REG_DAYA, /* Day Alarm */
155 CPCAP_REG_VAL1, /* Validity 1 */
156 CPCAP_REG_VAL2, /* Validity 2 */
158 CPCAP_REG_SDVSPLL, /* Switcher DVS and PLL */
159 CPCAP_REG_SI2CC1, /* Switcher I2C Control 1 */
160 CPCAP_REG_Si2CC2, /* Switcher I2C Control 2 */
161 CPCAP_REG_S1C1, /* Switcher 1 Control 1 */
162 CPCAP_REG_S1C2, /* Switcher 1 Control 2 */
163 CPCAP_REG_S2C1, /* Switcher 2 Control 1 */
164 CPCAP_REG_S2C2, /* Switcher 2 Control 2 */
165 CPCAP_REG_S3C, /* Switcher 3 Control */
166 CPCAP_REG_S4C1, /* Switcher 4 Control 1 */
167 CPCAP_REG_S4C2, /* Switcher 4 Control 2 */
168 CPCAP_REG_S5C, /* Switcher 5 Control */
169 CPCAP_REG_S6C, /* Switcher 6 Control */
170 CPCAP_REG_VCAMC, /* VCAM Control */
171 CPCAP_REG_VCSIC, /* VCSI Control */
172 CPCAP_REG_VDACC, /* VDAC Control */
173 CPCAP_REG_VDIGC, /* VDIG Control */
174 CPCAP_REG_VFUSEC, /* VFUSE Control */
175 CPCAP_REG_VHVIOC, /* VHVIO Control */
176 CPCAP_REG_VSDIOC, /* VSDIO Control */
177 CPCAP_REG_VPLLC, /* VPLL Control */
178 CPCAP_REG_VRF1C, /* VRF1 Control */
179 CPCAP_REG_VRF2C, /* VRF2 Control */
180 CPCAP_REG_VRFREFC, /* VRFREF Control */
181 CPCAP_REG_VWLAN1C, /* VWLAN1 Control */
182 CPCAP_REG_VWLAN2C, /* VWLAN2 Control */
183 CPCAP_REG_VSIMC, /* VSIM Control */
184 CPCAP_REG_VVIBC, /* VVIB Control */
185 CPCAP_REG_VUSBC, /* VUSB Control */
186 CPCAP_REG_VUSBINT1C, /* VUSBINT1 Control */
187 CPCAP_REG_VUSBINT2C, /* VUSBINT2 Control */
188 CPCAP_REG_URT, /* Useroff Regulator Trigger */
189 CPCAP_REG_URM1, /* Useroff Regulator Mask 1 */
190 CPCAP_REG_URM2, /* Useroff Regulator Mask 2 */
192 CPCAP_REG_VAUDIOC, /* VAUDIO Control */
193 CPCAP_REG_CC, /* Codec Control */
194 CPCAP_REG_CDI, /* Codec Digital Interface */
195 CPCAP_REG_SDAC, /* Stereo DAC */
196 CPCAP_REG_SDACDI, /* Stereo DAC Digital Interface */
197 CPCAP_REG_TXI, /* TX Inputs */
198 CPCAP_REG_TXMP, /* TX MIC PGA's */
199 CPCAP_REG_RXOA, /* RX Output Amplifiers */
200 CPCAP_REG_RXVC, /* RX Volume Control */
201 CPCAP_REG_RXCOA, /* RX Codec to Output Amps */
202 CPCAP_REG_RXSDOA, /* RX Stereo DAC to Output Amps */
203 CPCAP_REG_RXEPOA, /* RX External PGA to Output Amps */
204 CPCAP_REG_RXLL, /* RX Low Latency */
205 CPCAP_REG_A2LA, /* A2 Loudspeaker Amplifier */
206 CPCAP_REG_MIPIS1, /* MIPI Slimbus 1 */
207 CPCAP_REG_MIPIS2, /* MIPI Slimbus 2 */
208 CPCAP_REG_MIPIS3, /* MIPI Slimbus 3. */
209 CPCAP_REG_LVAB, /* LMR Volume and A4 Balanced. */
211 CPCAP_REG_CCC1, /* Coulomb Counter Control 1 */
212 CPCAP_REG_CRM, /* Charger and Reverse Mode */
213 CPCAP_REG_CCCC2, /* Coincell and Coulomb Ctr Ctrl 2 */
214 CPCAP_REG_CCS1, /* Coulomb Counter Sample 1 */
215 CPCAP_REG_CCS2, /* Coulomb Counter Sample 2 */
216 CPCAP_REG_CCA1, /* Coulomb Counter Accumulator 1 */
217 CPCAP_REG_CCA2, /* Coulomb Counter Accumulator 2 */
218 CPCAP_REG_CCM, /* Coulomb Counter Mode */
219 CPCAP_REG_CCO, /* Coulomb Counter Offset */
220 CPCAP_REG_CCI, /* Coulomb Counter Integrator */
222 CPCAP_REG_ADCC1, /* A/D Converter Configuration 1 */
223 CPCAP_REG_ADCC2, /* A/D Converter Configuration 2 */
224 CPCAP_REG_ADCD0, /* A/D Converter Data 0 */
225 CPCAP_REG_ADCD1, /* A/D Converter Data 1 */
226 CPCAP_REG_ADCD2, /* A/D Converter Data 2 */
227 CPCAP_REG_ADCD3, /* A/D Converter Data 3 */
228 CPCAP_REG_ADCD4, /* A/D Converter Data 4 */
229 CPCAP_REG_ADCD5, /* A/D Converter Data 5 */
230 CPCAP_REG_ADCD6, /* A/D Converter Data 6 */
231 CPCAP_REG_ADCD7, /* A/D Converter Data 7 */
232 CPCAP_REG_ADCAL1, /* A/D Converter Calibration 1 */
233 CPCAP_REG_ADCAL2, /* A/D Converter Calibration 2 */
235 CPCAP_REG_USBC1, /* USB Control 1 */
236 CPCAP_REG_USBC2, /* USB Control 2 */
237 CPCAP_REG_USBC3, /* USB Control 3 */
238 CPCAP_REG_UVIDL, /* ULPI Vendor ID Low */
239 CPCAP_REG_UVIDH, /* ULPI Vendor ID High */
240 CPCAP_REG_UPIDL, /* ULPI Product ID Low */
241 CPCAP_REG_UPIDH, /* ULPI Product ID High */
242 CPCAP_REG_UFC1, /* ULPI Function Control 1 */
243 CPCAP_REG_UFC2, /* ULPI Function Control 2 */
244 CPCAP_REG_UFC3, /* ULPI Function Control 3 */
245 CPCAP_REG_UIC1, /* ULPI Interface Control 1 */
246 CPCAP_REG_UIC2, /* ULPI Interface Control 2 */
247 CPCAP_REG_UIC3, /* ULPI Interface Control 3 */
248 CPCAP_REG_USBOTG1, /* USB OTG Control 1 */
249 CPCAP_REG_USBOTG2, /* USB OTG Control 2 */
250 CPCAP_REG_USBOTG3, /* USB OTG Control 3 */
251 CPCAP_REG_UIER1, /* USB Interrupt Enable Rising 1 */
252 CPCAP_REG_UIER2, /* USB Interrupt Enable Rising 2 */
253 CPCAP_REG_UIER3, /* USB Interrupt Enable Rising 3 */
254 CPCAP_REG_UIEF1, /* USB Interrupt Enable Falling 1 */
255 CPCAP_REG_UIEF2, /* USB Interrupt Enable Falling 1 */
256 CPCAP_REG_UIEF3, /* USB Interrupt Enable Falling 1 */
257 CPCAP_REG_UIS, /* USB Interrupt Status */
258 CPCAP_REG_UIL, /* USB Interrupt Latch */
259 CPCAP_REG_USBD, /* USB Debug */
260 CPCAP_REG_SCR1, /* Scratch 1 */
261 CPCAP_REG_SCR2, /* Scratch 2 */
262 CPCAP_REG_SCR3, /* Scratch 3 */
263 CPCAP_REG_VMC, /* Video Mux Control */
264 CPCAP_REG_OWDC, /* One Wire Device Control */
265 CPCAP_REG_GPIO0, /* GPIO 0 Control */
266 CPCAP_REG_GPIO1, /* GPIO 1 Control */
267 CPCAP_REG_GPIO2, /* GPIO 2 Control */
268 CPCAP_REG_GPIO3, /* GPIO 3 Control */
269 CPCAP_REG_GPIO4, /* GPIO 4 Control */
270 CPCAP_REG_GPIO5, /* GPIO 5 Control */
271 CPCAP_REG_GPIO6, /* GPIO 6 Control */
273 CPCAP_REG_MDLC, /* Main Display Lighting Control */
274 CPCAP_REG_KLC, /* Keypad Lighting Control */
275 CPCAP_REG_ADLC, /* Aux Display Lighting Control */
276 CPCAP_REG_REDC, /* Red Triode Control */
277 CPCAP_REG_GREENC, /* Green Triode Control */
278 CPCAP_REG_BLUEC, /* Blue Triode Control */
279 CPCAP_REG_CFC, /* Camera Flash Control */
280 CPCAP_REG_ABC, /* Adaptive Boost Control */
281 CPCAP_REG_BLEDC, /* Bluetooth LED Control */
282 CPCAP_REG_CLEDC, /* Camera Privacy LED Control */
284 CPCAP_REG_OW1C, /* One Wire 1 Command */
285 CPCAP_REG_OW1D, /* One Wire 1 Data */
286 CPCAP_REG_OW1I, /* One Wire 1 Interrupt */
287 CPCAP_REG_OW1IE, /* One Wire 1 Interrupt Enable */
288 CPCAP_REG_OW1, /* One Wire 1 Control */
289 CPCAP_REG_OW2C, /* One Wire 2 Command */
290 CPCAP_REG_OW2D, /* One Wire 2 Data */
291 CPCAP_REG_OW2I, /* One Wire 2 Interrupt */
292 CPCAP_REG_OW2IE, /* One Wire 2 Interrupt Enable */
293 CPCAP_REG_OW2, /* One Wire 2 Control */
294 CPCAP_REG_OW3C, /* One Wire 3 Command */
295 CPCAP_REG_OW3D, /* One Wire 3 Data */
296 CPCAP_REG_OW3I, /* One Wire 3 Interrupt */
297 CPCAP_REG_OW3IE, /* One Wire 3 Interrupt Enable */
298 CPCAP_REG_OW3, /* One Wire 3 Control */
299 CPCAP_REG_GCAIC, /* GCAI Clock Control */
300 CPCAP_REG_GCAIM, /* GCAI GPIO Mode */
301 CPCAP_REG_LGDIR, /* LMR GCAI GPIO Direction */
302 CPCAP_REG_LGPU, /* LMR GCAI GPIO Pull-up */
303 CPCAP_REG_LGPIN, /* LMR GCAI GPIO Pin */
304 CPCAP_REG_LGMASK, /* LMR GCAI GPIO Mask */
305 CPCAP_REG_LDEB, /* LMR Debounce Settings */
306 CPCAP_REG_LGDET, /* LMR GCAI Detach Detect */
307 CPCAP_REG_LMISC, /* LMR Misc Bits */
308 CPCAP_REG_LMACE, /* LMR Mace IC Support */
310 CPCAP_REG_TEST, /* Test */
311 CPCAP_REG_ST_TEST1, /* ST Test 1 */
313 CPCAP_REG_END = CPCAP_REG_ST_TEST1, /* End of CPCAP registers. */
315 CPCAP_REG_MAX /* The largest valid register value. */
318 CPCAP_REG_SIZE = CPCAP_REG_MAX + 1,
319 CPCAP_REG_UNUSED = CPCAP_REG_MAX + 2,
323 CPCAP_IOCTL_NUM_TEST__START,
324 CPCAP_IOCTL_NUM_TEST_READ_REG,
325 CPCAP_IOCTL_NUM_TEST_WRITE_REG,
326 CPCAP_IOCTL_NUM_TEST__END,
328 CPCAP_IOCTL_NUM_ADC__START,
329 CPCAP_IOCTL_NUM_ADC_PHASE,
330 CPCAP_IOCTL_NUM_ADC__END,
332 CPCAP_IOCTL_NUM_BATT__START,
333 CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE,
334 CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC,
335 CPCAP_IOCTL_NUM_BATT_ATOD_SYNC,
336 CPCAP_IOCTL_NUM_BATT_ATOD_READ,
337 CPCAP_IOCTL_NUM_BATT__END,
339 CPCAP_IOCTL_NUM_UC__START,
340 CPCAP_IOCTL_NUM_UC_MACRO_START,
341 CPCAP_IOCTL_NUM_UC_MACRO_STOP,
342 CPCAP_IOCTL_NUM_UC_GET_VENDOR,
343 CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE,
344 CPCAP_IOCTL_NUM_UC__END,
346 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD
347 CPCAP_IOCTL_NUM_RTC__START,
348 CPCAP_IOCTL_NUM_RTC_COUNT,
349 CPCAP_IOCTL_NUM_RTC__END,
352 CPCAP_IOCTL_NUM_ACCY__START,
353 CPCAP_IOCTL_NUM_ACCY_WHISPER,
354 CPCAP_IOCTL_NUM_ACCY__END,
358 CPCAP_IRQ__START, /* 1st supported interrupt event */
359 CPCAP_IRQ_HSCLK = CPCAP_IRQ_INT1_INDEX, /* High Speed Clock */
360 CPCAP_IRQ_PRIMAC, /* Primary Macro */
361 CPCAP_IRQ_SECMAC, /* Secondary Macro */
362 CPCAP_IRQ_LOWBPL, /* Low Battery Low Threshold */
363 CPCAP_IRQ_SEC2PRI, /* 2nd Macro to Primary Processor */
364 CPCAP_IRQ_LOWBPH, /* Low Battery High Threshold */
365 CPCAP_IRQ_EOL, /* End of Life */
366 CPCAP_IRQ_TS, /* Touchscreen */
367 CPCAP_IRQ_ADCDONE, /* ADC Conversion Complete */
368 CPCAP_IRQ_HS, /* Headset */
369 CPCAP_IRQ_MB2, /* Mic Bias2 */
370 CPCAP_IRQ_VBUSOV, /* Overvoltage Detected */
371 CPCAP_IRQ_RVRS_CHRG, /* Reverse Charge */
372 CPCAP_IRQ_CHRG_DET, /* Charger Detected */
373 CPCAP_IRQ_IDFLOAT, /* ID Float */
374 CPCAP_IRQ_IDGND, /* ID Ground */
376 CPCAP_IRQ_SE1 = CPCAP_IRQ_INT2_INDEX, /* SE1 Detector */
377 CPCAP_IRQ_SESSEND, /* Session End */
378 CPCAP_IRQ_SESSVLD, /* Session Valid */
379 CPCAP_IRQ_VBUSVLD, /* VBUS Valid */
380 CPCAP_IRQ_CHRG_CURR1, /* Charge Current Monitor (20mA) */
381 CPCAP_IRQ_CHRG_CURR2, /* Charge Current Monitor (250mA) */
382 CPCAP_IRQ_RVRS_MODE, /* Reverse Current Limit */
383 CPCAP_IRQ_ON, /* On Signal */
384 CPCAP_IRQ_ON2, /* On 2 Signal */
385 CPCAP_IRQ_CLK, /* 32k Clock Transition */
386 CPCAP_IRQ_1HZ, /* 1Hz Tick */
387 CPCAP_IRQ_PTT, /* Push To Talk */
388 CPCAP_IRQ_SE0CONN, /* SE0 Condition */
389 CPCAP_IRQ_CHRG_SE1B, /* CHRG_SE1B Pin */
390 CPCAP_IRQ_UART_ECHO_OVERRUN, /* UART Buffer Overflow */
391 CPCAP_IRQ_EXTMEMHD, /* External MEMHOLD */
393 CPCAP_IRQ_WARM = CPCAP_IRQ_INT3_INDEX, /* Warm Start */
394 CPCAP_IRQ_SYSRSTR, /* System Restart */
395 CPCAP_IRQ_SOFTRST, /* Soft Reset */
396 CPCAP_IRQ_DIEPWRDWN, /* Die Temperature Powerdown */
397 CPCAP_IRQ_DIETEMPH, /* Die Temperature High */
398 CPCAP_IRQ_PC, /* Power Cut */
399 CPCAP_IRQ_OFLOWSW, /* Stopwatch Overflow */
400 CPCAP_IRQ_TODA, /* TOD Alarm */
401 CPCAP_IRQ_OPT_SEL_DTCH, /* Detach Detect */
402 CPCAP_IRQ_OPT_SEL_STATE, /* State Change */
403 CPCAP_IRQ_ONEWIRE1, /* Onewire 1 Block */
404 CPCAP_IRQ_ONEWIRE2, /* Onewire 2 Block */
405 CPCAP_IRQ_ONEWIRE3, /* Onewire 3 Block */
406 CPCAP_IRQ_UCRESET, /* Microcontroller Reset */
407 CPCAP_IRQ_PWRGOOD, /* BP Turn On */
408 CPCAP_IRQ_USBDPLLCLK, /* USB DPLL Status */
410 CPCAP_IRQ_DPI = CPCAP_IRQ_INT4_INDEX, /* DP Line */
411 CPCAP_IRQ_DMI, /* DM Line */
412 CPCAP_IRQ_UCBUSY, /* Microcontroller Busy */
413 CPCAP_IRQ_GCAI_CURR1, /* Charge Current Monitor (65mA) */
414 CPCAP_IRQ_GCAI_CURR2, /* Charge Current Monitor (600mA) */
415 CPCAP_IRQ_SB_MAX_RETRANSMIT_ERR,/* SLIMbus Retransmit Error */
416 CPCAP_IRQ_BATTDETB, /* Battery Presence Detected */
417 CPCAP_IRQ_PRIHALT, /* Primary Microcontroller Halt */
418 CPCAP_IRQ_SECHALT, /* Secondary Microcontroller Halt */
419 CPCAP_IRQ_CC_CAL, /* CC Calibration */
421 CPCAP_IRQ_UC_PRIROMR = CPCAP_IRQ_INT5_INDEX, /* Prim ROM Rd Macro Int */
422 CPCAP_IRQ_UC_PRIRAMW, /* Primary RAM Write Macro Int */
423 CPCAP_IRQ_UC_PRIRAMR, /* Primary RAM Read Macro Int */
424 CPCAP_IRQ_UC_USEROFF, /* USEROFF Macro Interrupt */
425 CPCAP_IRQ_UC_PRIMACRO_4, /* Primary Macro 4 Interrupt */
426 CPCAP_IRQ_UC_PRIMACRO_5, /* Primary Macro 5 Interrupt */
427 CPCAP_IRQ_UC_PRIMACRO_6, /* Primary Macro 6 Interrupt */
428 CPCAP_IRQ_UC_PRIMACRO_7, /* Primary Macro 7 Interrupt */
429 CPCAP_IRQ_UC_PRIMACRO_8, /* Primary Macro 8 Interrupt */
430 CPCAP_IRQ_UC_PRIMACRO_9, /* Primary Macro 9 Interrupt */
431 CPCAP_IRQ_UC_PRIMACRO_10, /* Primary Macro 10 Interrupt */
432 CPCAP_IRQ_UC_PRIMACRO_11, /* Primary Macro 11 Interrupt */
433 CPCAP_IRQ_UC_PRIMACRO_12, /* Primary Macro 12 Interrupt */
434 CPCAP_IRQ_UC_PRIMACRO_13, /* Primary Macro 13 Interrupt */
435 CPCAP_IRQ_UC_PRIMACRO_14, /* Primary Macro 14 Interrupt */
436 CPCAP_IRQ_UC_PRIMACRO_15, /* Primary Macro 15 Interrupt */
437 CPCAP_IRQ__NUM /* Number of allocated events */
440 enum cpcap_adc_bank0 {
441 CPCAP_ADC_AD0_BATTDETB,
446 CPCAP_ADC_CHG_ISENSE,
453 enum cpcap_adc_bank1 {
466 enum cpcap_adc_format {
467 CPCAP_ADC_FORMAT_RAW,
468 CPCAP_ADC_FORMAT_PHASED,
469 CPCAP_ADC_FORMAT_CONVERTED,
472 enum cpcap_adc_timing {
473 CPCAP_ADC_TIMING_IMM,
475 CPCAP_ADC_TIMING_OUT,
478 enum cpcap_adc_type {
479 CPCAP_ADC_TYPE_BANK_0,
480 CPCAP_ADC_TYPE_BANK_1,
481 CPCAP_ADC_TYPE_BATT_PI,
510 enum cpcap_revision {
511 CPCAP_REVISION_1_0 = 0x08,
512 CPCAP_REVISION_1_1 = 0x09,
513 CPCAP_REVISION_2_0 = 0x10,
514 CPCAP_REVISION_2_1 = 0x11,
517 enum cpcap_batt_usb_model {
518 CPCAP_BATT_USB_MODEL_NONE,
519 CPCAP_BATT_USB_MODEL_USB,
520 CPCAP_BATT_USB_MODEL_FACTORY,
523 struct cpcap_spi_init_data {
528 struct cpcap_adc_ato {
529 unsigned short ato_in;
530 unsigned short atox_in;
531 unsigned short adc_ps_factor_in;
532 unsigned short atox_ps_factor_in;
533 unsigned short ato_out;
534 unsigned short atox_out;
535 unsigned short adc_ps_factor_out;
536 unsigned short atox_ps_factor_out;
539 struct cpcap_batt_data {
548 struct cpcap_batt_ac_data {
552 struct cpcap_batt_usb_data {
555 enum cpcap_batt_usb_model model;
558 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD
559 struct cpcap_rtc_time_cnt {
560 struct rtc_time time;
561 unsigned short count;
567 struct cpcap_platform_data {
568 struct cpcap_spi_init_data *init;
570 unsigned short *regulator_mode_values;
571 unsigned short *regulator_off_mode_values;
572 struct regulator_init_data *regulator_init;
573 struct cpcap_adc_ato *adc_ato;
574 void (*ac_changed)(struct power_supply *,
575 struct cpcap_batt_ac_data *);
576 void (*batt_changed)(struct power_supply *,
577 struct cpcap_batt_data *);
578 void (*usb_changed)(struct power_supply *,
579 struct cpcap_batt_usb_data *);
580 u16 hwcfg[CPCAP_HWCFG_NUM];
583 struct cpcap_whisper_pdata {
584 unsigned int data_gpio;
585 unsigned int pwr_gpio;
586 unsigned char uartmux;
589 struct cpcap_adc_request {
590 enum cpcap_adc_format format;
591 enum cpcap_adc_timing timing;
592 enum cpcap_adc_type type;
594 int result[CPCAP_ADC_BANK0_NUM];
595 void (*callback)(struct cpcap_device *, void *);
596 void *callback_param;
598 /* Used in case of sync requests */
599 struct completion completion;
603 struct cpcap_adc_us_request {
604 enum cpcap_adc_format format;
605 enum cpcap_adc_timing timing;
606 enum cpcap_adc_type type;
608 int result[CPCAP_ADC_BANK0_NUM];
611 struct cpcap_adc_phase {
612 signed char offset_batti;
613 unsigned char slope_batti;
614 signed char offset_chrgi;
615 unsigned char slope_chrgi;
616 signed char offset_battp;
617 unsigned char slope_battp;
618 signed char offset_bp;
619 unsigned char slope_bp;
620 signed char offset_battt;
621 unsigned char slope_battt;
622 signed char offset_chrgv;
623 unsigned char slope_chrgv;
626 struct cpcap_regacc {
628 unsigned short value;
632 struct cpcap_whisper_request {
634 char dock_id[CPCAP_WHISPER_ID_SIZE];
635 char dock_prop[CPCAP_WHISPER_PROP_SIZE];
639 * Gets the contents of the specified cpcap register.
641 * INPUTS: The register number in the cpcap driver's format.
643 * OUTPUTS: The command writes the register data back to user space at the
644 * location specified, or it may return an error code.
646 #ifdef CONFIG_RTC_INTF_CPCAP_SECCLKD
647 #define CPCAP_IOCTL_GET_RTC_TIME_COUNTER \
648 _IOR(0, CPCAP_IOCTL_NUM_RTC_COUNT, struct cpcap_rtc_time_cnt)
651 #define CPCAP_IOCTL_TEST_READ_REG \
652 _IOWR(0, CPCAP_IOCTL_NUM_TEST_READ_REG, struct cpcap_regacc*)
655 * Writes the specifed cpcap register.
657 * This function writes the specified cpcap register with the specified
660 * INPUTS: The register number in the cpcap driver's format and the data to
661 * write to that register.
663 * OUTPUTS: The command has no output other than the returned error code for
666 #define CPCAP_IOCTL_TEST_WRITE_REG \
667 _IOWR(0, CPCAP_IOCTL_NUM_TEST_WRITE_REG, struct cpcap_regacc*)
669 #define CPCAP_IOCTL_ADC_PHASE \
670 _IOWR(0, CPCAP_IOCTL_NUM_ADC_PHASE, struct cpcap_adc_phase*)
672 #define CPCAP_IOCTL_BATT_DISPLAY_UPDATE \
673 _IOW(0, CPCAP_IOCTL_NUM_BATT_DISPLAY_UPDATE, struct cpcap_batt_data*)
675 #define CPCAP_IOCTL_BATT_ATOD_ASYNC \
676 _IOW(0, CPCAP_IOCTL_NUM_BATT_ATOD_ASYNC, struct cpcap_adc_us_request*)
678 #define CPCAP_IOCTL_BATT_ATOD_SYNC \
679 _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_SYNC, struct cpcap_adc_us_request*)
681 #define CPCAP_IOCTL_BATT_ATOD_READ \
682 _IOWR(0, CPCAP_IOCTL_NUM_BATT_ATOD_READ, struct cpcap_adc_us_request*)
685 #define CPCAP_IOCTL_UC_MACRO_START \
686 _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_START, enum cpcap_macro)
688 #define CPCAP_IOCTL_UC_MACRO_STOP \
689 _IOWR(0, CPCAP_IOCTL_NUM_UC_MACRO_STOP, enum cpcap_macro)
691 #define CPCAP_IOCTL_UC_GET_VENDOR \
692 _IOWR(0, CPCAP_IOCTL_NUM_UC_GET_VENDOR, enum cpcap_vendor)
694 #define CPCAP_IOCTL_UC_SET_TURBO_MODE \
695 _IOW(0, CPCAP_IOCTL_NUM_UC_SET_TURBO_MODE, unsigned short)
697 #define CPCAP_IOCTL_ACCY_WHISPER \
698 _IOW(0, CPCAP_IOCTL_NUM_ACCY_WHISPER, struct cpcap_whisper_request*)
701 struct cpcap_device {
702 struct spi_device *spi;
703 enum cpcap_vendor vendor;
704 enum cpcap_revision revision;
706 struct platform_device *regulator_pdev[CPCAP_NUM_REGULATORS];
712 void (*h2w_new_state)(int);
715 static inline void cpcap_set_keydata(struct cpcap_device *cpcap, void *data)
717 cpcap->keydata = data;
720 static inline void *cpcap_get_keydata(struct cpcap_device *cpcap)
722 return cpcap->keydata;
725 int cpcap_regacc_write(struct cpcap_device *cpcap, enum cpcap_reg reg,
726 unsigned short value, unsigned short mask);
728 int cpcap_regacc_read(struct cpcap_device *cpcap, enum cpcap_reg reg,
729 unsigned short *value_ptr);
731 int cpcap_regacc_init(struct cpcap_device *cpcap);
733 void cpcap_broadcast_key_event(struct cpcap_device *cpcap,
734 unsigned int code, int value);
736 int cpcap_irq_init(struct cpcap_device *cpcap);
738 void cpcap_irq_shutdown(struct cpcap_device *cpcap);
740 int cpcap_irq_register(struct cpcap_device *cpcap, enum cpcap_irqs irq,
741 void (*cb_func) (enum cpcap_irqs, void *), void *data);
743 int cpcap_irq_free(struct cpcap_device *cpcap, enum cpcap_irqs irq);
745 int cpcap_irq_get_data(struct cpcap_device *cpcap, enum cpcap_irqs irq,
748 int cpcap_irq_clear(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
750 int cpcap_irq_mask(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
752 int cpcap_irq_unmask(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
754 int cpcap_irq_mask_get(struct cpcap_device *cpcap, enum cpcap_irqs int_event);
756 int cpcap_irq_sense(struct cpcap_device *cpcap, enum cpcap_irqs int_event,
757 unsigned char clear);
760 int cpcap_irq_suspend(struct cpcap_device *cpcap);
762 int cpcap_irq_resume(struct cpcap_device *cpcap);
765 int cpcap_adc_sync_read(struct cpcap_device *cpcap,
766 struct cpcap_adc_request *request);
768 int cpcap_adc_async_read(struct cpcap_device *cpcap,
769 struct cpcap_adc_request *request);
771 void cpcap_adc_phase(struct cpcap_device *cpcap, struct cpcap_adc_phase *phase);
773 void cpcap_batt_set_ac_prop(struct cpcap_device *cpcap, int online);
775 void cpcap_batt_set_usb_prop_online(struct cpcap_device *cpcap, int online,
776 enum cpcap_batt_usb_model model);
778 void cpcap_batt_set_usb_prop_curr(struct cpcap_device *cpcap,
781 int cpcap_uc_start(struct cpcap_device *cpcap, enum cpcap_macro macro);
783 int cpcap_uc_stop(struct cpcap_device *cpcap, enum cpcap_macro macro);
785 unsigned char cpcap_uc_status(struct cpcap_device *cpcap,
786 enum cpcap_macro macro);
788 int cpcap_accy_whisper(struct cpcap_device *cpcap,
789 struct cpcap_whisper_request *req);
791 void cpcap_accy_whisper_spdif_set_state(int state);
793 #define cpcap_driver_register platform_driver_register
794 #define cpcap_driver_unregister platform_driver_unregister
796 int cpcap_device_register(struct platform_device *pdev);
797 int cpcap_device_unregister(struct platform_device *pdev);
800 #endif /* __KERNEL__ */
801 #endif /* _LINUX_SPI_CPCAP_H */