1 #ifndef __MACH_ROCKCHIP_PMU_H
2 #define __MACH_ROCKCHIP_PMU_H
4 #define RK3188_PMU_WAKEUP_CFG0 0x00
5 #define RK3188_PMU_WAKEUP_CFG1 0x04
6 #define RK3188_PMU_PWRDN_CON 0x08
7 #define RK3188_PMU_PWRDN_ST 0x0c
8 #define RK3188_PMU_INT_CON 0x10
9 #define RK3188_PMU_INT_ST 0x14
10 #define RK3188_PMU_MISC_CON 0x18
11 #define RK3188_PMU_OSC_CNT 0x1c
12 #define RK3188_PMU_PLL_CNT 0x20
13 #define RK3188_PMU_PMU_CNT 0x24
14 #define RK3188_PMU_DDRIO_PWRON_CNT 0x28
15 #define RK3188_PMU_WAKEUP_RST_CLR_CNT 0x2c
16 #define RK3188_PMU_SCU_PWRDWN_CNT 0x30
17 #define RK3188_PMU_SCU_PWRUP_CNT 0x34
18 #define RK3188_PMU_MISC_CON1 0x38
19 #define RK3188_PMU_GPIO0_CON 0x3c
20 #define RK3188_PMU_SYS_REG0 0x40
21 #define RK3188_PMU_SYS_REG1 0x44
22 #define RK3188_PMU_SYS_REG2 0x48
23 #define RK3188_PMU_SYS_REG3 0x4c
24 #define RK3188_PMU_STOP_INT_DLY 0x60
25 #define RK3188_PMU_GPIO0A_PULL 0x64
26 #define RK3188_PMU_GPIO0B_PULL 0x68
28 #define RK3288_PMU_WAKEUP_CFG0 0x00
29 #define RK3288_PMU_WAKEUP_CFG1 0x04
30 #define RK3288_PMU_PWRDN_CON 0x08
31 #define RK3288_PMU_PWRDN_ST 0x0c
32 #define RK3288_PMU_IDLE_REQ 0x10
33 #define RK3288_PMU_IDLE_ST 0x14
34 #define RK3288_PMU_PWRMODE_CON 0x18
35 #define RK3288_PMU_PWR_STATE 0x1c
36 #define RK3288_PMU_OSC_CNT 0x20
37 #define RK3288_PMU_PLL_CNT 0x24
38 #define RK3288_PMU_STABL_CNT 0x28
39 #define RK3288_PMU_DDR0IO_PWRON_CNT 0x2c
40 #define RK3288_PMU_DDR1IO_PWRON_CNT 0x30
41 #define RK3288_PMU_CORE_PWRDWN_CNT 0x34
42 #define RK3288_PMU_CORE_PWRUP_CNT 0x38
43 #define RK3288_PMU_GPU_PWRDWN_CNT 0x3c
44 #define RK3288_PMU_GPU_PWRUP_CNT 0x40
45 #define RK3288_PMU_WAKEUP_RST_CLR_CNT 0x44
46 #define RK3288_PMU_SFT_CON 0x48
47 #define RK3288_PMU_DDR_SREF_ST 0x4c
48 #define RK3288_PMU_INT_CON 0x50
49 #define RK3288_PMU_INT_ST 0x54
50 #define RK3288_PMU_BOOT_ADDR_SEL 0x58
51 #define RK3288_PMU_GRF_CON 0x5c
52 #define RK3288_PMU_GPIO_SR 0x60
53 #define RK3288_PMU_GPIO0_A_PULL 0x64
54 #define RK3288_PMU_GPIO0_B_PULL 0x68
55 #define RK3288_PMU_GPIO0_C_PULL 0x6c
56 #define RK3288_PMU_GPIO0_A_DRV 0x70
57 #define RK3288_PMU_GPIO0_B_DRV 0x74
58 #define RK3288_PMU_GPIO0_C_DRV 0x78
59 #define RK3288_PMU_GPIO_OP 0x7c
60 #define RK3288_PMU_GPIO0_SEL18 0x80
61 #define RK3288_PMU_GPIO0_A_IOMUX 0x84
62 #define RK3288_PMU_GPIO0_B_IOMUX 0x88
63 #define RK3288_PMU_GPIO0_C_IOMUX 0x8c
64 #define RK3288_PMU_PWRMODE_CON1 0x90
65 #define RK3288_PMU_SYS_REG0 0x94
66 #define RK3288_PMU_SYS_REG1 0x98
67 #define RK3288_PMU_SYS_REG2 0x9c
68 #define RK3288_PMU_SYS_REG3 0xa0
70 #define RK312X_PMU_WAKEUP_CFG 0x00
71 #define RK312X_PMU_PWRDN_CON 0x04
72 #define RK312X_PMU_PWRDN_ST 0x08
73 #define RK312X_PMU_IDLE_REQ 0x0C
74 #define RK312X_PMU_IDLE_ST 0x10
75 #define RK312X_PMU_PWRMODE_CON 0x14
76 #define RK312X_PMU_PWR_STATE 0x18
77 #define RK312X_PMU_OSC_CNT 0x1C
78 #define RK312X_PMU_CORE_PWRDWN_CNT 0x20
79 #define RK312X_PMU_CORE_PWRUP_CNT 0x24
80 #define RK312X_PMU_SFT_CON 0x28
81 #define RK312X_PMU_DDR_SREF_ST 0x2C
82 #define RK312X_PMU_INT_CON 0x30
83 #define RK312X_PMU_INT_ST 0x34
84 #define RK312X_PMU_SYS_REG0 0x38
85 #define RK312X_PMU_SYS_REG1 0x3C
86 #define RK312X_PMU_SYS_REG2 0x40
87 #define RK312X_PMU_SYS_REG3 0x44
89 #define RK3368_PMU_PWRDN_CON 0x0c
90 #define RK3368_PMU_PWRDN_ST 0x10
91 #define RK3368_PMU_IDLE_REQ 0x3c
92 #define RK3368_PMU_IDLE_ST 0x40
94 enum pmu_power_domain {
131 struct rockchip_pmu_operations {
132 int (*set_power_domain)(enum pmu_power_domain pd, bool on);
133 bool (*power_domain_is_on)(enum pmu_power_domain pd);
134 int (*set_idle_request)(enum pmu_idle_req req, bool idle);
137 extern struct rockchip_pmu_operations rockchip_pmu_ops;