include/linux/rockchip/pmu.h

   1 #ifndef __MACH_ROCKCHIP_PMU_H
   2 #define __MACH_ROCKCHIP_PMU_H
   3
   4 #define RK312x_PMU_SYS_REG0             0x38
   5 #define RK312x_PMU_SYS_REG1             0x3c
   6
   7 #define RK3188_PMU_WAKEUP_CFG0          0x00
   8 #define RK3188_PMU_WAKEUP_CFG1          0x04
   9 #define RK3188_PMU_PWRDN_CON            0x08
  10 #define RK3188_PMU_PWRDN_ST             0x0c
  11 #define RK3188_PMU_INT_CON              0x10
  12 #define RK3188_PMU_INT_ST               0x14
  13 #define RK3188_PMU_MISC_CON             0x18
  14 #define RK3188_PMU_OSC_CNT              0x1c
  15 #define RK3188_PMU_PLL_CNT              0x20
  16 #define RK3188_PMU_PMU_CNT              0x24
  17 #define RK3188_PMU_DDRIO_PWRON_CNT      0x28
  18 #define RK3188_PMU_WAKEUP_RST_CLR_CNT   0x2c
  19 #define RK3188_PMU_SCU_PWRDWN_CNT       0x30
  20 #define RK3188_PMU_SCU_PWRUP_CNT        0x34
  21 #define RK3188_PMU_MISC_CON1            0x38
  22 #define RK3188_PMU_GPIO0_CON            0x3c
  23 #define RK3188_PMU_SYS_REG0             0x40
  24 #define RK3188_PMU_SYS_REG1             0x44
  25 #define RK3188_PMU_SYS_REG2             0x48
  26 #define RK3188_PMU_SYS_REG3             0x4c
  27 #define RK3188_PMU_STOP_INT_DLY         0x60
  28 #define RK3188_PMU_GPIO0A_PULL          0x64
  29 #define RK3188_PMU_GPIO0B_PULL          0x68
  30
  31 #define RK3288_PMU_WAKEUP_CFG0          0x00
  32 #define RK3288_PMU_WAKEUP_CFG1          0x04
  33 #define RK3288_PMU_PWRDN_CON            0x08
  34 #define RK3288_PMU_PWRDN_ST             0x0c
  35 #define RK3288_PMU_IDLE_REQ             0x10
  36 #define RK3288_PMU_IDLE_ST              0x14
  37 #define RK3288_PMU_PWRMODE_CON          0x18
  38 #define RK3288_PMU_PWR_STATE            0x1c
  39 #define RK3288_PMU_OSC_CNT              0x20
  40 #define RK3288_PMU_PLL_CNT              0x24
  41 #define RK3288_PMU_STABL_CNT            0x28
  42 #define RK3288_PMU_DDR0IO_PWRON_CNT     0x2c
  43 #define RK3288_PMU_DDR1IO_PWRON_CNT     0x30
  44 #define RK3288_PMU_CORE_PWRDWN_CNT      0x34
  45 #define RK3288_PMU_CORE_PWRUP_CNT       0x38
  46 #define RK3288_PMU_GPU_PWRDWN_CNT       0x3c
  47 #define RK3288_PMU_GPU_PWRUP_CNT        0x40
  48 #define RK3288_PMU_WAKEUP_RST_CLR_CNT   0x44
  49 #define RK3288_PMU_SFT_CON              0x48
  50 #define RK3288_PMU_DDR_SREF_ST          0x4c
  51 #define RK3288_PMU_INT_CON              0x50
  52 #define RK3288_PMU_INT_ST               0x54
  53 #define RK3288_PMU_BOOT_ADDR_SEL        0x58
  54 #define RK3288_PMU_GRF_CON              0x5c
  55 #define RK3288_PMU_GPIO_SR              0x60
  56 #define RK3288_PMU_GPIO0_A_PULL         0x64
  57 #define RK3288_PMU_GPIO0_B_PULL         0x68
  58 #define RK3288_PMU_GPIO0_C_PULL         0x6c
  59 #define RK3288_PMU_GPIO0_A_DRV          0x70
  60 #define RK3288_PMU_GPIO0_B_DRV          0x74
  61 #define RK3288_PMU_GPIO0_C_DRV          0x78
  62 #define RK3288_PMU_GPIO_OP              0x7c
  63 #define RK3288_PMU_GPIO0_SEL18          0x80
  64 #define RK3288_PMU_GPIO0_A_IOMUX        0x84
  65 #define RK3288_PMU_GPIO0_B_IOMUX        0x88
  66 #define RK3288_PMU_GPIO0_C_IOMUX        0x8c
  67 #define RK3288_PMU_PWRMODE_CON1        0x90
  68 #define RK3288_PMU_SYS_REG0             0x94
  69 #define RK3288_PMU_SYS_REG1             0x98
  70 #define RK3288_PMU_SYS_REG2             0x9c
  71 #define RK3288_PMU_SYS_REG3             0xa0
  72
  73 #define RK312X_PMU_WAKEUP_CFG           0x00
  74 #define RK312X_PMU_PWRDN_CON                    0x04
  75 #define RK312X_PMU_PWRDN_ST                     0x08
  76 #define RK312X_PMU_IDLE_REQ                     0x0C
  77 #define RK312X_PMU_IDLE_ST                              0x10
  78 #define RK312X_PMU_PWRMODE_CON          0x14
  79 #define RK312X_PMU_PWR_STATE                    0x18
  80 #define RK312X_PMU_OSC_CNT                      0x1C
  81 #define RK312X_PMU_CORE_PWRDWN_CNT      0x20
  82 #define RK312X_PMU_CORE_PWRUP_CNT       0x24
  83 #define RK312X_PMU_SFT_CON                      0x28
  84 #define RK312X_PMU_DDR_SREF_ST          0x2C
  85 #define RK312X_PMU_INT_CON                      0x30
  86 #define RK312X_PMU_INT_ST                               0x34
  87 #define RK312X_PMU_SYS_REG0                     0x38
  88 #define RK312X_PMU_SYS_REG1                     0x3C
  89 #define RK312X_PMU_SYS_REG2                     0x40
  90 #define RK312X_PMU_SYS_REG3                     0x44
  91
  92
  93 enum pmu_power_domain {
  94         PD_BCPU,
  95         PD_BDSP,
  96         PD_BUS,
  97         PD_CPU_0,
  98         PD_CPU_1,
  99         PD_CPU_2,
 100         PD_CPU_3,
 101         PD_CS,
 102         PD_GPU,
 103         PD_HEVC,
 104         PD_PERI,
 105         PD_SCU,
 106         PD_VIDEO,
 107         PD_VIO,
 108 };
 109
 110 enum pmu_idle_req {
 111         IDLE_REQ_ALIVE,
 112         IDLE_REQ_AP2BP,
 113         IDLE_REQ_BP2AP,
 114         IDLE_REQ_BUS,
 115         IDLE_REQ_CORE,
 116         IDLE_REQ_CPUP,
 117         IDLE_REQ_DMA,
 118         IDLE_REQ_GPU,
 119         IDLE_REQ_HEVC,
 120         IDLE_REQ_PERI,
 121         IDLE_REQ_VIDEO,
 122         IDLE_REQ_VIO,
 123         IDLE_REQ_SYS,
 124         IDLE_REQ_MSCH,
 125         IDLE_REQ_CRYPTO,
 126 };
 127
 128 struct rockchip_pmu_operations {
 129         int (*set_power_domain)(enum pmu_power_domain pd, bool on);
 130         bool (*power_domain_is_on)(enum pmu_power_domain pd);
 131         int (*set_idle_request)(enum pmu_idle_req req, bool idle);
 132 };
 133
 134 extern struct rockchip_pmu_operations rockchip_pmu_ops;
 135
 136 #endif