fixed: rk3288 sleep
[firefly-linux-kernel-4.4.55.git] / include / linux / rockchip / iomap.h
1 #ifndef __MACH_ROCKCHIP_IOMAP_H
2 #define __MACH_ROCKCHIP_IOMAP_H
3
4 #ifndef __ASSEMBLY__
5 #include <asm/io.h>
6 #endif
7
8 #define RK_IO_ADDRESS(x)                IOMEM(0xFED00000 + x)
9
10 #define RK_CRU_VIRT                     RK_IO_ADDRESS(0x00000000)
11 #define RK_GRF_VIRT                     RK_IO_ADDRESS(0x00010000)
12 #define RK_SGRF_VIRT                    (RK_GRF_VIRT + 0x1000)
13 #define RK_PMU_VIRT                     RK_IO_ADDRESS(0x00020000)
14 #define RK_ROM_VIRT                     RK_IO_ADDRESS(0x00030000)
15 #define RK_EFUSE_VIRT                   RK_IO_ADDRESS(0x00040000)
16 #define RK_GPIO_VIRT(n)                 RK_IO_ADDRESS(0x00050000 + (n) * 0x1000)
17 #define RK_DEBUG_UART_VIRT              RK_IO_ADDRESS(0x00060000)
18 #define RK_CPU_AXI_BUS_VIRT             RK_IO_ADDRESS(0x00070000)
19 #define RK_TIMER_VIRT                   RK_IO_ADDRESS(0x00080000)
20 #define RK_GIC_VIRT                      RK_IO_ADDRESS(0x00090000)
21 #define RK_BOOTRAM_VIRT           RK_IO_ADDRESS(0x000a0000)
22 #define RK_DDR_VIRT                     RK_IO_ADDRESS(0x000d0000)
23
24
25 #define RK3188_CRU_PHYS                 0x20000000
26 #define RK3188_CRU_SIZE                 SZ_4K
27 #define RK3188_GRF_PHYS                 0x20008000
28 #define RK3188_GRF_SIZE                 SZ_4K
29 #define RK3188_PMU_PHYS                 0x20004000
30 #define RK3188_PMU_SIZE                 SZ_4K
31 #define RK3188_ROM_PHYS                 0x10120000
32 #define RK3188_ROM_SIZE                 SZ_16K
33 #define RK3188_EFUSE_PHYS               0x20010000
34 #define RK3188_EFUSE_SIZE               SZ_4K
35 #define RK3188_GPIO0_PHYS               0x2000a000
36 #define RK3188_GPIO1_PHYS               0x2003c000
37 #define RK3188_GPIO2_PHYS               0x2003e000
38 #define RK3188_GPIO3_PHYS               0x20080000
39 #define RK3188_GPIO_SIZE                SZ_4K
40 #define RK3188_CPU_AXI_BUS_PHYS         0x10128000
41 #define RK3188_CPU_AXI_BUS_SIZE         SZ_32K
42 #define RK3188_TIMER0_PHYS              0x20038000
43 #define RK3188_TIMER3_PHYS              0x2000e000
44 #define RK3188_TIMER_SIZE               SZ_4K
45 #define RK3188_DDR_PCTL_PHYS            0x20020000
46 #define RK3188_DDR_PCTL_SIZE            SZ_4K
47 #define RK3188_DDR_PUBL_PHYS            0x20040000
48 #define RK3188_DDR_PUBL_SIZE            SZ_4K
49 #define RK3188_UART0_PHYS               0x10124000
50 #define RK3188_UART1_PHYS               0x10126000
51 #define RK3188_UART2_PHYS               0x20064000
52 #define RK3188_UART3_PHYS               0x20068000
53 #define RK3188_UART_SIZE                SZ_4K
54
55 #define RK3288_CRU_PHYS                 0xFF760000
56 #define RK3288_CRU_SIZE                 SZ_4K
57 #define RK3288_GRF_PHYS                 0xFF770000
58 #define RK3288_GRF_SIZE                 SZ_4K
59 #define RK3288_SGRF_PHYS                0xFF740000
60 #define RK3288_SGRF_SIZE                SZ_4K
61 #define RK3288_PMU_PHYS                 0xFF730000
62 #define RK3288_PMU_SIZE                 SZ_4K
63 #define RK3288_ROM_PHYS                 0xFFFD0000
64 #define RK3288_ROM_SIZE                 (SZ_16K + SZ_4K)
65 #define RK3288_EFUSE_PHYS               0xFFB40000
66 #define RK3288_EFUSE_SIZE               SZ_4K
67 #define RK3288_GPIO0_PHYS               0xFF750000
68 #define RK3288_GPIO1_PHYS               0xFF780000
69 #define RK3288_GPIO2_PHYS               0xFF790000
70 #define RK3288_GPIO3_PHYS               0xFF7A0000
71 #define RK3288_GPIO4_PHYS               0xFF7B0000
72 #define RK3288_GPIO5_PHYS               0xFF7C0000
73 #define RK3288_GPIO6_PHYS               0xFF7D0000
74 #define RK3288_GPIO7_PHYS               0xFF7E0000
75 #define RK3288_GPIO8_PHYS               0xFF7F0000
76 #define RK3288_GPIO_SIZE                SZ_4K
77 #define RK3288_SERVICE_CORE_PHYS        0XFFA80000
78 #define RK3288_SERVICE_CORE_SIZE        SZ_4K
79 #define RK3288_SERVICE_DMAC_PHYS        0XFFA90000
80 #define RK3288_SERVICE_DMAC_SIZE        SZ_4K
81 #define RK3288_SERVICE_GPU_PHYS         0XFFAA0000
82 #define RK3288_SERVICE_GPU_SIZE         SZ_4K
83 #define RK3288_SERVICE_PERI_PHYS        0XFFAB0000
84 #define RK3288_SERVICE_PERI_SIZE        SZ_4K
85 #define RK3288_SERVICE_BUS_PHYS         0XFFAC0000
86 #define RK3288_SERVICE_BUS_SIZE         SZ_16K
87 #define RK3288_SERVICE_VIO_PHYS         0XFFAD0000
88 #define RK3288_SERVICE_VIO_SIZE         SZ_4K
89 #define RK3288_SERVICE_VIDEO_PHYS       0XFFAE0000
90 #define RK3288_SERVICE_VIDEO_SIZE       SZ_4K
91 #define RK3288_SERVICE_HEVC_PHYS        0XFFAF0000
92 #define RK3288_SERVICE_HEVC_SIZE        SZ_4K
93 #define RK3288_TIMER0_PHYS              0xFF6B0000
94 #define RK3288_TIMER6_PHYS              0xFF810000
95 #define RK3288_TIMER_SIZE               SZ_4K
96 #define RK3288_DDR_PCTL0_PHYS           0xFF610000
97 #define RK3288_DDR_PCTL1_PHYS           0xFF630000
98 #define RK3288_DDR_PCTL_SIZE            SZ_4K
99 #define RK3288_DDR_PUBL0_PHYS           0xFF620000
100 #define RK3288_DDR_PUBL1_PHYS           0xFF640000
101 #define RK3288_DDR_PUBL_SIZE            SZ_4K
102 #define RK3288_UART_BT_PHYS             0xFF180000
103 #define RK3288_UART_BB_PHYS             0xFF190000
104 #define RK3288_UART_DBG_PHYS            0xFF690000
105 #define RK3288_UART_GPS_PHYS            0xFF1B0000
106 #define RK3288_UART_EXP_PHYS            0xFF1C0000
107 #define RK3288_UART_SIZE                SZ_4K
108
109 #define RK3288_GIC_DIST_PHYS            0xffc01000
110 #define RK3288_GIC_DIST_SIZE                SZ_4K
111 #define RK3288_GIC_CPU_PHYS            0xffc02000
112 #define RK3288_GIC_CPU_SIZE                SZ_4K
113
114 #define RK3288_BOOTRAM_PHYS            0xff720000
115 #define RK3288_BOOTRAM_SIZE            SZ_4K
116
117
118 #endif