1 #ifndef __MACH_ROCKCHIP_GRF_H
2 #define __MACH_ROCKCHIP_GRF_H
4 #define RK3188_GRF_GPIO0L_DIR 0x0000
5 #define RK3188_GRF_GPIO0H_DIR 0x0004
6 #define RK3188_GRF_GPIO1L_DIR 0x0008
7 #define RK3188_GRF_GPIO1H_DIR 0x000c
8 #define RK3188_GRF_GPIO2L_DIR 0x0010
9 #define RK3188_GRF_GPIO2H_DIR 0x0014
10 #define RK3188_GRF_GPIO3L_DIR 0x0018
11 #define RK3188_GRF_GPIO3H_DIR 0x001c
12 #define RK3188_GRF_GPIO0L_DO 0x0020
13 #define RK3188_GRF_GPIO0H_DO 0x0024
14 #define RK3188_GRF_GPIO1L_DO 0x0028
15 #define RK3188_GRF_GPIO1H_DO 0x002c
16 #define RK3188_GRF_GPIO2L_DO 0x0030
17 #define RK3188_GRF_GPIO2H_DO 0x0034
18 #define RK3188_GRF_GPIO3L_DO 0x0038
19 #define RK3188_GRF_GPIO3H_DO 0x003c
20 #define RK3188_GRF_GPIO0L_EN 0x0040
21 #define RK3188_GRF_GPIO0H_EN 0x0044
22 #define RK3188_GRF_GPIO1L_EN 0x0048
23 #define RK3188_GRF_GPIO1H_EN 0x004c
24 #define RK3188_GRF_GPIO2L_EN 0x0050
25 #define RK3188_GRF_GPIO2H_EN 0x0054
26 #define RK3188_GRF_GPIO3L_EN 0x0058
27 #define RK3188_GRF_GPIO3H_EN 0x005c
29 #define RK3188_GRF_GPIO0C_IOMUX 0x0068
30 #define RK3188_GRF_GPIO0D_IOMUX 0x006c
31 #define RK3188_GRF_GPIO1A_IOMUX 0x0070
32 #define RK3188_GRF_GPIO1B_IOMUX 0x0074
33 #define RK3188_GRF_GPIO1C_IOMUX 0x0078
34 #define RK3188_GRF_GPIO1D_IOMUX 0x007c
35 #define RK3188_GRF_GPIO2A_IOMUX 0x0080
36 #define RK3188_GRF_GPIO2B_IOMUX 0x0084
37 #define RK3188_GRF_GPIO2C_IOMUX 0x0088
38 #define RK3188_GRF_GPIO2D_IOMUX 0x008c
39 #define RK3188_GRF_GPIO3A_IOMUX 0x0090
40 #define RK3188_GRF_GPIO3B_IOMUX 0x0094
41 #define RK3188_GRF_GPIO3C_IOMUX 0x0098
42 #define RK3188_GRF_GPIO3D_IOMUX 0x009c
43 #define RK3188_GRF_SOC_CON0 0x00a0
44 #define RK3188_GRF_SOC_CON1 0x00a4
45 #define RK3188_GRF_SOC_CON2 0x00a8
46 #define RK3188_GRF_SOC_STATUS0 0x00ac
47 #define RK3188_GRF_DMAC1_CON0 0x00b0
48 #define RK3188_GRF_DMAC1_CON1 0x00b4
49 #define RK3188_GRF_DMAC1_CON2 0x00b8
50 #define RK3188_GRF_DMAC2_CON0 0x00bc
51 #define RK3188_GRF_DMAC2_CON1 0x00c0
52 #define RK3188_GRF_DMAC2_CON2 0x00c4
53 #define RK3188_GRF_DMAC2_CON3 0x00c8
54 #define RK3188_GRF_CPU_CON0 0x00cc
55 #define RK3188_GRF_CPU_CON1 0x00d0
56 #define RK3188_GRF_CPU_CON2 0x00d4
57 #define RK3188_GRF_CPU_CON3 0x00d8
58 #define RK3188_GRF_CPU_CON4 0x00dc
59 #define RK3188_GRF_CPU_CON5 0x00e0
61 #define RK3188_GRF_DDRC_CON0 0x00ec
62 #define RK3188_GRF_DDRC_STAT 0x00f0
63 #define RK3188_GRF_IO_CON0 0x00f4
64 #define RK3188_GRF_IO_CON1 0x00f8
65 #define RK3188_GRF_IO_CON2 0x00fc
66 #define RK3188_GRF_IO_CON3 0x0100
67 #define RK3188_GRF_IO_CON4 0x0104
68 #define RK3188_GRF_SOC_STATUS1 0x0108
69 #define RK3188_GRF_UOC0_CON0 0x010c
70 #define RK3188_GRF_UOC0_CON1 0x0110
71 #define RK3188_GRF_UOC0_CON2 0x0114
72 #define RK3188_GRF_UOC0_CON3 0x0118
73 #define RK3188_GRF_UOC1_CON0 0x011c
74 #define RK3188_GRF_UOC1_CON1 0x0120
75 #define RK3188_GRF_UOC1_CON2 0x0124
76 #define RK3188_GRF_UOC1_CON3 0x0128
77 #define RK3188_GRF_UOC2_CON0 0x012c
78 #define RK3188_GRF_UOC2_CON1 0x0130
80 #define RK3188_GRF_UOC3_CON0 0x0138
81 #define RK3188_GRF_UOC3_CON1 0x013c
82 #define RK3188_GRF_HSIC_STAT 0x0140
83 #define RK3188_GRF_OS_REG0 0x0144
84 #define RK3188_GRF_OS_REG1 0x0148
85 #define RK3188_GRF_OS_REG2 0x014c
86 #define RK3188_GRF_OS_REG3 0x0150
87 #define RK3188_GRF_OS_REG4 0x0154
88 #define RK3188_GRF_OS_REG5 0x0158
89 #define RK3188_GRF_OS_REG6 0x015c
90 #define RK3188_GRF_OS_REG7 0x0160
91 #define RK3188_GRF_GPIO0B_PULL 0x0164
92 #define RK3188_GRF_GPIO0C_PULL 0x0168
93 #define RK3188_GRF_GPIO0D_PULL 0x016c
94 #define RK3188_GRF_GPIO1A_PULL 0x0170
95 #define RK3188_GRF_GPIO1B_PULL 0x0174
96 #define RK3188_GRF_GPIO1C_PULL 0x0178
97 #define RK3188_GRF_GPIO1D_PULL 0x017c
98 #define RK3188_GRF_GPIO2A_PULL 0x0180
99 #define RK3188_GRF_GPIO2B_PULL 0x0184
100 #define RK3188_GRF_GPIO2C_PULL 0x0188
101 #define RK3188_GRF_GPIO2D_PULL 0x018c
102 #define RK3188_GRF_GPIO3A_PULL 0x0190
103 #define RK3188_GRF_GPIO3B_PULL 0x0194
104 #define RK3188_GRF_GPIO3C_PULL 0x0198
105 #define RK3188_GRF_GPIO3D_PULL 0x019c
106 #define RK3188_GRF_FLASH_DATA_PULL 0x01a0
107 #define RK3188_GRF_FLASH_CMD_PULL 0x01a4
109 #define RK3288_GRF_GPIO1D_IOMUX 0x000c
110 #define RK3288_GRF_GPIO2A_IOMUX 0x0010
111 #define RK3288_GRF_GPIO2B_IOMUX 0x0014
112 #define RK3288_GRF_GPIO2C_IOMUX 0x0018
114 #define RK3288_GRF_GPIO3A_IOMUX 0x0020
115 #define RK3288_GRF_GPIO3B_IOMUX 0x0024
116 #define RK3288_GRF_GPIO3C_IOMUX 0x0028
117 #define RK3288_GRF_GPIO3DL_IOMUX 0x002c
118 #define RK3288_GRF_GPIO3DH_IOMUX 0x0030
119 #define RK3288_GRF_GPIO4AL_IOMUX 0x0034
120 #define RK3288_GRF_GPIO4AH_IOMUX 0x0038
121 #define RK3288_GRF_GPIO4BL_IOMUX 0x003c
123 #define RK3288_GRF_GPIO4C_IOMUX 0x0044
124 #define RK3288_GRF_GPIO4D_IOMUX 0x0048
126 #define RK3288_GRF_GPIO5B_IOMUX 0x0050
127 #define RK3288_GRF_GPIO5C_IOMUX 0x0054
129 #define RK3288_GRF_GPIO6A_IOMUX 0x005c
130 #define RK3288_GRF_GPIO6B_IOMUX 0x0060
131 #define RK3288_GRF_GPIO6C_IOMUX 0x0064
133 #define RK3288_GRF_GPIO7A_IOMUX 0x006c
134 #define RK3288_GRF_GPIO7B_IOMUX 0x0070
135 #define RK3288_GRF_GPIO7CL_IOMUX 0x0074
136 #define RK3288_GRF_GPIO7CH_IOMUX 0x0078
138 #define RK3288_GRF_GPIO8A_IOMUX 0x0080
139 #define RK3288_GRF_GPIO8B_IOMUX 0x0084
141 #define RK3288_GRF_GPIO1H_SR 0x0104
142 #define RK3288_GRF_GPIO2L_SR 0x0108
143 #define RK3288_GRF_GPIO2H_SR 0x010c
144 #define RK3288_GRF_GPIO3L_SR 0x0110
145 #define RK3288_GRF_GPIO3H_SR 0x0114
146 #define RK3288_GRF_GPIO4L_SR 0x0118
147 #define RK3288_GRF_GPIO4H_SR 0x011c
148 #define RK3288_GRF_GPIO5L_SR 0x0120
149 #define RK3288_GRF_GPIO5H_SR 0x0124
150 #define RK3288_GRF_GPIO6L_SR 0x0128
151 #define RK3288_GRF_GPIO6H_SR 0x012c
152 #define RK3288_GRF_GPIO7L_SR 0x0130
153 #define RK3288_GRF_GPIO7H_SR 0x0134
154 #define RK3288_GRF_GPIO8L_SR 0x0138
156 #define RK3288_GRF_GPIO1D_P 0x014c
157 #define RK3288_GRF_GPIO2A_P 0x0150
158 #define RK3288_GRF_GPIO2B_P 0x0154
159 #define RK3288_GRF_GPIO2C_P 0x0158
161 #define RK3288_GRF_GPIO3A_P 0x0160
162 #define RK3288_GRF_GPIO3B_P 0x0164
163 #define RK3288_GRF_GPIO3C_P 0x0168
164 #define RK3288_GRF_GPIO3D_P 0x016c
165 #define RK3288_GRF_GPIO4A_P 0x0170
166 #define RK3288_GRF_GPIO4B_P 0x0174
167 #define RK3288_GRF_GPIO4C_P 0x0178
168 #define RK3288_GRF_GPIO4D_P 0x017c
170 #define RK3288_GRF_GPIO5B_P 0x0184
171 #define RK3288_GRF_GPIO5C_P 0x0188
173 #define RK3288_GRF_GPIO6A_P 0x0190
174 #define RK3288_GRF_GPIO6B_P 0x0194
175 #define RK3288_GRF_GPIO6C_P 0x0198
177 #define RK3288_GRF_GPIO7A_P 0x01a0
178 #define RK3288_GRF_GPIO7B_P 0x01a4
179 #define RK3288_GRF_GPIO7C_P 0x01a8
181 #define RK3288_GRF_GPIO8A_P 0x01b0
182 #define RK3288_GRF_GPIO8B_P 0x01b4
184 #define RK3288_GRF_GPIO1D_E 0x01cc
185 #define RK3288_GRF_GPIO2A_E 0x01d0
186 #define RK3288_GRF_GPIO2B_E 0x01d4
187 #define RK3288_GRF_GPIO2C_E 0x01d8
189 #define RK3288_GRF_GPIO3A_E 0x01e0
190 #define RK3288_GRF_GPIO3B_E 0x01e4
191 #define RK3288_GRF_GPIO3C_E 0x01e8
192 #define RK3288_GRF_GPIO3D_E 0x01ec
193 #define RK3288_GRF_GPIO4A_E 0x01f0
194 #define RK3288_GRF_GPIO4B_E 0x01f4
195 #define RK3288_GRF_GPIO4C_E 0x01f8
196 #define RK3288_GRF_GPIO4D_E 0x01fc
198 #define RK3288_GRF_GPIO5B_E 0x0204
199 #define RK3288_GRF_GPIO5C_E 0x0208
201 #define RK3288_GRF_GPIO6A_E 0x0210
202 #define RK3288_GRF_GPIO6B_E 0x0214
203 #define RK3288_GRF_GPIO6C_E 0x0218
205 #define RK3288_GRF_GPIO7A_E 0x0220
206 #define RK3288_GRF_GPIO7B_E 0x0224
207 #define RK3288_GRF_GPIO7C_E 0x0228
209 #define RK3288_GRF_GPIO8A_E 0x0230
210 #define RK3288_GRF_GPIO8B_E 0x0234
212 #define RK3288_GRF_GPIO_SMT 0x0240
213 #define RK3288_GRF_SOC_CON0 0x0244
214 #define RK3288_GRF_SOC_CON1 0x0248
215 #define RK3288_GRF_SOC_CON2 0x024c
216 #define RK3288_GRF_SOC_CON3 0x0250
217 #define RK3288_GRF_SOC_CON4 0x0254
218 #define RK3288_GRF_SOC_CON5 0x0258
219 #define RK3288_GRF_SOC_CON6 0x025c
220 #define RK3288_GRF_SOC_CON7 0x0260
221 #define RK3288_GRF_SOC_CON8 0x0264
222 #define RK3288_GRF_SOC_CON9 0x0268
223 #define RK3288_GRF_SOC_CON10 0x026c
224 #define RK3288_GRF_SOC_CON11 0x0270
225 #define RK3288_GRF_SOC_CON12 0x0274
226 #define RK3288_GRF_SOC_CON13 0x0278
227 #define RK3288_GRF_SOC_CON14 0x027c
228 #define RK3288_GRF_SOC_STATUS0 0x0280
229 #define RK3288_GRF_SOC_STATUS1 0x0284
230 #define RK3288_GRF_SOC_STATUS2 0x0288
231 #define RK3288_GRF_SOC_STATUS3 0x028c
232 #define RK3288_GRF_SOC_STATUS4 0x0290
233 #define RK3288_GRF_SOC_STATUS5 0x0294
234 #define RK3288_GRF_SOC_STATUS6 0x0298
235 #define RK3288_GRF_SOC_STATUS7 0x029c
236 #define RK3288_GRF_SOC_STATUS8 0x02a0
237 #define RK3288_GRF_SOC_STATUS9 0x02a4
238 #define RK3288_GRF_SOC_STATUS10 0x02a8
239 #define RK3288_GRF_SOC_STATUS11 0x02ac
240 #define RK3288_GRF_SOC_STATUS12 0x02b0
241 #define RK3288_GRF_SOC_STATUS13 0x02b4
242 #define RK3288_GRF_SOC_STATUS14 0x02b8
243 #define RK3288_GRF_SOC_STATUS15 0x02bc
244 #define RK3288_GRF_SOC_STATUS16 0x02c0
245 #define RK3288_GRF_SOC_STATUS17 0x02c4
246 #define RK3288_GRF_SOC_STATUS18 0x02c8
247 #define RK3288_GRF_SOC_STATUS19 0x02cc
248 #define RK3288_GRF_SOC_STATUS20 0x02d0
249 #define RK3288_GRF_SOC_STATUS21 0x02d4
251 #define RK3288_GRF_PERIDMAC_CON0 0x02e0
252 #define RK3288_GRF_PERIDMAC_CON1 0x02e4
253 #define RK3288_GRF_PERIDMAC_CON2 0x02e8
254 #define RK3288_GRF_PERIDMAC_CON3 0x02ec
255 #define RK3288_GRF_DDRC0_CON0 0x02f0
256 #define RK3288_GRF_DDRC1_CON0 0x02f4
257 #define RK3288_GRF_CPU_CON0 0x02f8
258 #define RK3288_GRF_CPU_CON1 0x02fc
259 #define RK3288_GRF_CPU_CON2 0x0300
260 #define RK3288_GRF_CPU_CON3 0x0304
261 #define RK3288_GRF_CPU_CON4 0x0308
263 #define RK3288_GRF_CPU_STATUS0 0x0318
265 #define RK3288_GRF_UOC0_CON0 0x0320
266 #define RK3288_GRF_UOC0_CON1 0x0324
267 #define RK3288_GRF_UOC0_CON2 0x0328
268 #define RK3288_GRF_UOC0_CON3 0x032c
269 #define RK3288_GRF_UOC0_CON4 0x0330
270 #define RK3288_GRF_UOC1_CON0 0x0334
271 #define RK3288_GRF_UOC1_CON1 0x0338
272 #define RK3288_GRF_UOC1_CON2 0x033c
273 #define RK3288_GRF_UOC1_CON3 0x0340
274 #define RK3288_GRF_UOC1_CON4 0x0344
275 #define RK3288_GRF_UOC2_CON0 0x0348
276 #define RK3288_GRF_UOC2_CON1 0x034c
277 #define RK3288_GRF_UOC2_CON2 0x0350
278 #define RK3288_GRF_UOC2_CON3 0x0354
279 #define RK3288_GRF_UOC3_CON0 0x0358
280 #define RK3288_GRF_UOC3_CON1 0x035c
281 #define RK3288_GRF_UOC4_CON0 0x0360
282 #define RK3288_GRF_UOC4_CON1 0x0364
283 #define RK3288_GRF_PVTM_CON0 0x0368
284 #define RK3288_GRF_PVTM_CON1 0x036c
285 #define RK3288_GRF_PVTM_CON2 0x0370
286 #define RK3288_GRF_PVTM_STATUS0 0x0374
287 #define RK3288_GRF_PVTM_STATUS1 0x0378
288 #define RK3288_GRF_PVTM_STATUS2 0x037c
289 #define RK3288_GRF_IO_VSEL 0x0380
290 #define RK3288_GRF_SARADC_TESTBIT 0x0384
291 #define RK3288_GRF_TSADC_TESTBIT_L 0x0388
292 #define RK3288_GRF_TSADC_TESTBIT_H 0x038c
293 #define RK3288_GRF_OS_REG0 0x0390
294 #define RK3288_GRF_OS_REG1 0x0394
295 #define RK3288_GRF_OS_REG2 0x0398
296 #define RK3288_GRF_OS_REG3 0x039c
298 #define RK3288_GRF_SOC_CON15 0x03a4
299 #define RK3288_GRF_SOC_CON16 0x03a8
301 #define RK3288_SGRF_SOC_CON0 0x0000
302 #define RK3288_SGRF_SOC_CON1 0x0004
303 #define RK3288_SGRF_SOC_CON2 0x0008
304 #define RK3288_SGRF_SOC_CON3 0x000c
305 #define RK3288_SGRF_SOC_CON4 0x0010
306 #define RK3288_SGRF_SOC_CON5 0x0014
308 #define RK3288_SGRF_BUSDMAC_CON0 0x0020
309 #define RK3288_SGRF_BUSDMAC_CON1 0x0024
311 #define RK3288_SGRF_CPU_CON0 0x0040
312 #define RK3288_SGRF_CPU_CON1 0x0044
313 #define RK3288_SGRF_CPU_CON2 0x0048
315 #define RK3288_SGRF_SOC_CON6 0x0050
316 #define RK3288_SGRF_SOC_CON7 0x0054
317 #define RK3288_SGRF_SOC_CON8 0x0058
318 #define RK3288_SGRF_SOC_CON9 0x005c
319 #define RK3288_SGRF_SOC_CON10 0x0060
320 #define RK3288_SGRF_SOC_CON11 0x0064
321 #define RK3288_SGRF_SOC_CON12 0x0068
322 #define RK3288_SGRF_SOC_CON13 0x006c
323 #define RK3288_SGRF_SOC_CON14 0x0070
324 #define RK3288_SGRF_SOC_CON15 0x0074
325 #define RK3288_SGRF_SOC_CON16 0x0078
326 #define RK3288_SGRF_SOC_CON17 0x007c
327 #define RK3288_SGRF_SOC_CON18 0x0080
328 #define RK3288_SGRF_SOC_CON19 0x0084
329 #define RK3288_SGRF_SOC_CON20 0x0088
330 #define RK3288_SGRF_SOC_CON21 0x008c
332 #define RK3288_SGRF_SOC_STATUS0 0x0100
333 #define RK3288_SGRF_SOC_STATUS1 0x0104
335 #define RK3288_SGRF_FAST_BOOT_ADDR 0x0120