e5d355b7e06c5801c3b7401f26689f0dd35862a0
[firefly-linux-kernel-4.4.55.git] / include / linux / rockchip / cru.h
1 #ifndef __MACH_ROCKCHIP_CRU_H
2 #define __MACH_ROCKCHIP_CRU_H
3
4 #include <dt-bindings/clock/rockchip,rk3188.h>
5 #include <linux/rockchip/iomap.h>
6
7
8 /*******************CRU BITS*******************************/
9
10 #define CRU_W_MSK(bits_shift, msk)      ((msk) << ((bits_shift) + 16))
11
12 #define CRU_SET_BITS(val, bits_shift, msk)      (((val)&(msk)) << (bits_shift))
13
14 #define CRU_W_MSK_SETBITS(val, bits_shift,msk) \
15         (CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk))
16
17 /*******************RK3188********************************/
18 /*******************CRU OFFSET*********************/
19 #define RK3188_CRU_MODE_CON             0x40
20 #define RK3188_CRU_CLKSEL_CON           0x44
21 #define RK3188_CRU_CLKGATE_CON          0xd0
22 #define RK3188_CRU_GLB_SRST_FST         0x100
23 #define RK3188_CRU_GLB_SRST_SND         0x104
24 #define RK3188_CRU_SOFTRST_CON          0x110
25
26 #define RK3188_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
27
28 #define RK3188_CRU_CLKSELS_CON_CNT      (35)
29 #define RK3188_CRU_CLKSELS_CON(i)       (RK3188_CRU_CLKSEL_CON + ((i) * 4))
30
31 #define RK3188_CRU_CLKGATES_CON_CNT     (10)
32 #define RK3188_CRU_CLKGATES_CON(i)      (RK3188_CRU_CLKGATE_CON + ((i) * 4))
33
34 #define RK3188_CRU_SOFTRSTS_CON_CNT     (9)
35 #define RK3188_CRU_SOFTRSTS_CON(i)      (RK3188_CRU_SOFTRST_CON + ((i) * 4))
36
37 #define RK3188_CRU_MISC_CON             (0x134)
38 #define RK3188_CRU_GLB_CNT_TH           (0x140)
39
40 /******************PLL MODE BITS*******************/
41 #define RK3188_PLL_MODE_MSK(id)         (0x3 << ((id) * 4))
42 #define RK3188_PLL_MODE_SLOW(id)        ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
43 #define RK3188_PLL_MODE_NORM(id)        ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
44 #define RK3188_PLL_MODE_DEEP(id)        ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
45
46 /******************CRU GATINGS**********************************/
47 #define RK3188_CRU_GATEID_CONS(ID) (RK3188_CRU_CLKGATE_CON+(ID/16)*4)
48
49 /*************************RK3288********************************/
50
51 /*******************CRU OFFSET*********************/
52 #define RK3288_CRU_MODE_CON             0x50
53 #define RK3288_CRU_CLKSEL_CON           0x60
54 #define RK3288_CRU_CLKGATE_CON          0x160
55
56 #define RK3288_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
57 #define RK3288_CRU_CLKSELS_CON(i)       (RK3288_CRU_CLKSEL_CON + ((i) * 4))
58 #define RK3288_CRU_CLKGATES_CON(i)      (RK3288_CRU_CLKGATE_CON + ((i) * 4))
59
60 /******************PLL MODE BITS*******************/
61 // apll dpll,cpll,gpll,npll 0~4
62 #define RK3288_PLLS_MODE_OFFSET(id) ((id)<=3 ? (id*4) : 14)
63 #define RK3288_PLL_MODE_MSK(id)         (0x3 << RK3288_PLLS_MODE_OFFSET(id))
64 #define RK3288_PLL_MODE_SLOW(id)        ((0x0<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
65 #define RK3288_PLL_MODE_NORM(id)        ((0x1<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
66 #define RK3288_PLL_MODE_DEEP(id)        ((0x2<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
67
68 /*******************CRU GATING*********************/
69 #define RK3288_CRU_CLKGATES_CON_CNT (19)
70 #define RK3288_CRU_CONS_GATEID(i)       (16 * (i))
71 #define RK3288_CRU_GATEID_CONS(ID)      (RK3288_CRU_CLKGATE_CON+(ID/16)*4)
72
73 enum rk3288_cru_clk_gate {
74         /* SCU CLK GATE 0 CON */
75         //gate0
76         RK3288_CLKGATE_UART0_SRC    =   (RK3288_CRU_CONS_GATEID(1)+8),   
77         
78         RK3288_CLKGATE_UART4_SRC    =   (RK3288_CRU_CONS_GATEID(2)+12),   
79         
80         RK3288_CLKGATE_PCLK_UART0= (RK3288_CRU_CONS_GATEID(6)+8),   
81         RK3288_CLKGATE_PCLK_UART1,
82         RK3288_CLKGATE6_DUMP1,
83         RK3288_CLKGATE_PCLK_UART3,
84         RK3288_CLKGATE_PCLK_I2C2,
85         RK3288_CLKGATE_PCLK_I2C3,
86         RK3288_CLKGATE_PCLK_I2C4,
87
88         RK3288_CLKGATE_PCLK_I2C0    =   (RK3288_CRU_CONS_GATEID(10)+2), 
89         RK3288_CLKGATE_PCLK_I2C1,
90         
91         RK3288_CLKGATE_PCLK_UART2    =   (RK3288_CRU_CONS_GATEID(11)+9), 
92
93     
94         RK3288_CLKGATE_PCLK_GPIO1   =   (RK3288_CRU_CONS_GATEID(14)+1),
95         
96         RK3288_CLKGATE_PCLK_GPIO0   =   (RK3288_CRU_CONS_GATEID(17)+4),
97         //gate6
98 };
99
100 #define RK3288_CRU_GLB_SRST_FST_VALUE   0x1b0
101 #define RK3288_CRU_GLB_SRST_SND_VALUE   0x1b4
102 #define RK3288_CRU_SOFTRST_CON          0x1b8
103 #define RK3288_CRU_MISC_CON             0x1e8
104 #define RK3288_CRU_GLB_CNT_TH           0x1ec
105 #define RK3288_CRU_GLB_RST_CON          0x1f0
106 #define RK3288_CRU_GLB_RST_ST           0x1f8
107 #define RK3288_CRU_SDMMC_CON0           0x200
108 #define RK3288_CRU_SDMMC_CON1           0x204
109 #define RK3288_CRU_SDIO0_CON0           0x208
110 #define RK3288_CRU_SDIO0_CON1           0x20c
111 #define RK3288_CRU_SDIO1_CON0           0x210
112 #define RK3288_CRU_SDIO1_CON1           0x214
113 #define RK3288_CRU_EMMC_CON0            0x218
114 #define RK3288_CRU_EMMC_CON1            0x21c
115
116 #define RK3288_CRU_SOFTRSTS_CON_CNT     (12)
117 #define RK3288_CRU_SOFTRSTS_CON(i)      (RK3288_CRU_SOFTRST_CON + ((i) * 4))
118
119 enum rk3288_cru_soft_reset {
120         RK3288_SOFT_RST_CORE0,
121         RK3288_SOFT_RST_CORE1,
122         RK3288_SOFT_RST_CORE2,
123         RK3288_SOFT_RST_CORE3,
124         RK3288_SOFT_RST_CORE0_PO,
125         RK3288_SOFT_RST_CORE1_PO,
126         RK3288_SOFT_RST_CORE2_PO,
127         RK3288_SOFT_RST_CORE3_PO,
128         RK3288_SOFT_RST_PD_CORE_STR_SYS_A,
129         RK3288_SOFT_RST_PD_BUS_STR_SYS_A,
130         RK3288_SOFT_RST_L2C,
131         RK3288_SOFT_RST_TOPDBG,
132         RK3288_SOFT_RST_CORE0_DBG,
133         RK3288_SOFT_RST_CORE1_DBG,
134         RK3288_SOFT_RST_CORE2_DBG,
135         RK3288_SOFT_RST_CORE3_DBG,
136
137         RK3288_SOFT_RST_PD_BUS_AHB_ARBITOR,
138         RK3288_SOFT_RST_EFUSE_256BIT_P,
139         RK3288_SOFT_RST_DMA1,
140         RK3288_SOFT_RST_INTMEM,
141         RK3288_SOFT_RST_ROM,
142         RK3288_SOFT_RST_SPDIF_8CH,
143         RK3288_SOFT_RST_TIMER_P,
144         RK3288_SOFT_RST_I2S,
145         RK3288_SOFT_RST_SPDIF,
146         RK3288_SOFT_RST_TIMER0,
147         RK3288_SOFT_RST_TIMER1,
148         RK3288_SOFT_RST_TIMER2,
149         RK3288_SOFT_RST_TIMER3,
150         RK3288_SOFT_RST_TIMER4,
151         RK3288_SOFT_RST_TIMER5,
152         RK3288_SOFT_RST_EFUSE_P,
153
154         RK3288_SOFT_RST_GPIO0,
155         RK3288_SOFT_RST_GPIO1,
156         RK3288_SOFT_RST_GPIO2,
157         RK3288_SOFT_RST_GPIO3,
158         RK3288_SOFT_RST_GPIO4,
159         RK3288_SOFT_RST_GPIO5,
160         RK3288_SOFT_RST_GPIO6,
161         RK3288_SOFT_RST_GPIO7,
162         RK3288_SOFT_RST_GPIO8,
163         RK3288_SOFT_RST_2RES9,
164         RK3288_SOFT_RST_I2C0,
165         RK3288_SOFT_RST_I2C1,
166         RK3288_SOFT_RST_I2C2,
167         RK3288_SOFT_RST_I2C3,
168         RK3288_SOFT_RST_I2C4,
169         RK3288_SOFT_RST_I2C5,
170
171         RK3288_SOFT_RST_DW_PWM,
172         RK3288_SOFT_RST_MMC_PERI,
173         RK3288_SOFT_RST_PERIPH_MMU,
174         RK3288_SOFT_RST_DAP,
175         RK3288_SOFT_RST_DAP_SYS,
176         RK3288_SOFT_RST_TPIU_AT,
177         RK3288_SOFT_RST_PMU_P,
178         RK3288_SOFT_RST_GRF,
179         RK3288_SOFT_RST_PMU,
180         RK3288_SOFT_RST_PERIPHSYS_A,
181         RK3288_SOFT_RST_PERIPHSYS_H,
182         RK3288_SOFT_RST_PERIPHSYS_P,
183         RK3288_SOFT_RST_PERIPH_NIU,
184         RK3288_SOFT_RST_PD_PERI_AHB_ARBITOR,
185         RK3288_SOFT_RST_EMEM_PERI,
186         RK3288_SOFT_RST_USB_PERI,
187
188         RK3288_SOFT_RST_DMA2,
189         RK3288_SOFT_RST_4RES1,
190         RK3288_SOFT_RST_MAC,
191         RK3288_SOFT_RST_GPS,
192         RK3288_SOFT_RST_4RES4,
193         RK3288_SOFT_RST_RK_PWM,
194         RK3288_SOFT_RST_4RES6,
195         RK3288_SOFT_RST_CCP,
196         RK3288_SOFT_RST_USB_HOST0,
197         RK3288_SOFT_RST_HSIC,
198         RK3288_SOFT_RST_HSIC_AUX,
199         RK3288_SOFT_RST_HSICPHY,
200         RK3288_SOFT_RST_HSADC,
201         RK3288_SOFT_RST_NANDC0,
202         RK3288_SOFT_RST_NANDC1,
203         RK3288_SOFT_RST_4RES15,
204
205         RK3288_SOFT_RST_TZPC,
206         RK3288_SOFT_RST_5RES1,
207         RK3288_SOFT_RST_5RES2,
208         RK3288_SOFT_RST_SPI0,
209         RK3288_SOFT_RST_SPI1,
210         RK3288_SOFT_RST_SPI2,
211         RK3288_SOFT_RST_5RES6,
212         RK3288_SOFT_RST_SARADC,
213         RK3288_SOFT_RST_PD_ALIVE_NIU_P,
214         RK3288_SOFT_RST_PD_PMU_INTMEM_P,
215         RK3288_SOFT_RST_PD_PMU_NIU_P,
216         RK3288_SOFT_RST_SECURITY_GRF_P,
217         RK3288_SOFT_RST_5RES12,
218         RK3288_SOFT_RST_5RES13,
219         RK3288_SOFT_RST_5RES14,
220         RK3288_SOFT_RST_5RES15,
221
222         RK3288_SOFT_RST_VIO_ARBI_H,
223         RK3288_SOFT_RST_RGA_NIU_A,
224         RK3288_SOFT_RST_VIO0_NIU_A,
225         RK3288_SOFT_RST_VIO_NIU_H,
226         RK3288_SOFT_RST_LCDC0_A,
227         RK3288_SOFT_RST_LCDC0_H,
228         RK3288_SOFT_RST_LCDC0_D,
229         RK3288_SOFT_RST_VIO1_NIU_A,
230         RK3288_SOFT_RST_VIP,
231         RK3288_SOFT_RST_RGA_CORE,
232         RK3288_SOFT_RST_IEP_A,
233         RK3288_SOFT_RST_IEP_H,
234         RK3288_SOFT_RST_RGA_A,
235         RK3288_SOFT_RST_RGA_H,
236         RK3288_SOFT_RST_ISP,
237         RK3288_SOFT_RST_EDP,
238
239         RK3288_SOFT_RST_VCODEC_A,
240         RK3288_SOFT_RST_VCODEC_H,
241         RK3288_SOFT_RST_VIO_H2P_H,
242         RK3288_SOFT_RST_MIPIDSI0_P,
243         RK3288_SOFT_RST_MIPIDSI1_P,
244         RK3288_SOFT_RST_MIPICSI_P,
245         RK3288_SOFT_RST_LVDS_PHY_P,
246         RK3288_SOFT_RST_LVDS_CON,
247         RK3288_SOFT_RST_GPU,
248         RK3288_SOFT_RST_HDMI,
249         RK3288_SOFT_RST_7RES10,
250         RK3288_SOFT_RST_7RES11,
251         RK3288_SOFT_RST_CORE_PVTM,
252         RK3288_SOFT_RST_GPU_PVTM,
253         RK3288_SOFT_RST_7RES14,
254         RK3288_SOFT_RST_7RES15,
255
256         RK3288_SOFT_RST_MMC0,
257         RK3288_SOFT_RST_SDIO0,
258         RK3288_SOFT_RST_SDIO1,
259         RK3288_SOFT_RST_EMMC,
260         RK3288_SOFT_RST_USBOTG_H,
261         RK3288_SOFT_RST_USBOTGPHY,
262         RK3288_SOFT_RST_USBOTGC,
263         RK3288_SOFT_RST_USBHOST0_H,
264         RK3288_SOFT_RST_USBHOST0PHY,
265         RK3288_SOFT_RST_USBHOST0C,
266         RK3288_SOFT_RST_USBHOST1_H,
267         RK3288_SOFT_RST_USBHOST1PHY,
268         RK3288_SOFT_RST_USBHOST1C,
269         RK3288_SOFT_RST_USB_ADP,
270         RK3288_SOFT_RST_ACC_EFUSE,
271         RK3288_SOFT_RST_8RES15,
272
273         RK3288_SOFT_RST_CORESIGHT,
274         RK3288_SOFT_RST_PD_CORE_AHB_NOC,
275         RK3288_SOFT_RST_PD_CORE_APB_NOC,
276         RK3288_SOFT_RST_PD_CORE_MP_AXI,
277         RK3288_SOFT_RST_GIC,
278         RK3288_SOFT_RST_LCDCPWM0,
279         RK3288_SOFT_RST_LCDCPWM1,
280         RK3288_SOFT_RST_VIO0_H2P_BRG,
281         RK3288_SOFT_RST_VIO1_H2P_BRG,
282         RK3288_SOFT_RST_RGA_H2P_BRG,
283         RK3288_SOFT_RST_HEVC,
284         RK3288_SOFT_RST_9RES11,
285         RK3288_SOFT_RST_9RES12,
286         RK3288_SOFT_RST_9RES13,
287         RK3288_SOFT_RST_9RES14,
288         RK3288_SOFT_RST_TSADC_P,
289
290         RK3288_SOFT_RST_DDRPHY0,
291         RK3288_SOFT_RST_DDRPHY0_P,
292         RK3288_SOFT_RST_DDRCTRL0,
293         RK3288_SOFT_RST_DDRCTRL0_P,
294         RK3288_SOFT_RST_DDRPHY0_CTL,
295         RK3288_SOFT_RST_DDRPHY1,
296         RK3288_SOFT_RST_DDRPHY1_P,
297         RK3288_SOFT_RST_DDRCTRL1,
298         RK3288_SOFT_RST_DDRCTRL1_P,
299         RK3288_SOFT_RST_DDRPHY1_CTL,
300         RK3288_SOFT_RST_DDRMSCH0,
301         RK3288_SOFT_RST_DDRMSCH1,
302         RK3288_SOFT_RST_10RES12,
303         RK3288_SOFT_RST_10RES13,
304         RK3288_SOFT_RST_CRYPTO,
305         RK3288_SOFT_RST_C2C_HOST,
306
307         RK3288_SOFT_RST_LCDC1_A,
308         RK3288_SOFT_RST_LCDC1_H,
309         RK3288_SOFT_RST_LCDC1_D,
310         RK3288_SOFT_RST_UART0,
311         RK3288_SOFT_RST_UART1,
312         RK3288_SOFT_RST_UART2,
313         RK3288_SOFT_RST_UART3,
314         RK3288_SOFT_RST_UART4,
315         RK3288_SOFT_RST_11RES8,
316         RK3288_SOFT_RST_11RES9,
317         RK3288_SOFT_RST_SIMC,
318         RK3288_SOFT_RST_PS2C,
319         RK3288_SOFT_RST_TSP,
320         RK3288_SOFT_RST_TSP_CLKIN0,
321         RK3288_SOFT_RST_TSP_CLKIN1,
322         RK3288_SOFT_RST_TSP_27M,
323 };
324
325 static inline void rk3288_cru_set_soft_reset(enum rk3288_cru_soft_reset idx, bool on)
326 {
327         void __iomem *reg = RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(idx >> 4);
328         u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
329         writel_relaxed(val, reg);
330         dsb();
331 }
332
333 #endif