4bd4cfbed11909e8c160c6f683e0a4fafb859517
[firefly-linux-kernel-4.4.55.git] / include / linux / rockchip / cru.h
1 #ifndef __MACH_ROCKCHIP_CRU_H
2 #define __MACH_ROCKCHIP_CRU_H
3
4 #include <dt-bindings/clock/rockchip,rk3188.h>
5 #include <dt-bindings/clock/rockchip,rk3288.h>
6 #include <linux/rockchip/iomap.h>
7
8
9 /*******************CRU BITS*******************************/
10
11 #define CRU_W_MSK(bits_shift, msk)      ((msk) << ((bits_shift) + 16))
12
13 #define CRU_SET_BITS(val, bits_shift, msk)      (((val)&(msk)) << (bits_shift))
14
15 #define CRU_W_MSK_SETBITS(val, bits_shift,msk) \
16         (CRU_W_MSK(bits_shift, msk) | CRU_SET_BITS(val, bits_shift, msk))
17
18 /*******************RK3188********************************/
19 /*******************CRU OFFSET*********************/
20 #define RK3188_CRU_MODE_CON             0x40
21 #define RK3188_CRU_CLKSEL_CON           0x44
22 #define RK3188_CRU_CLKGATE_CON          0xd0
23 #define RK3188_CRU_GLB_SRST_FST         0x100
24 #define RK3188_CRU_GLB_SRST_SND         0x104
25 #define RK3188_CRU_SOFTRST_CON          0x110
26
27 #define RK3188_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
28
29 #define RK3188_CRU_CLKSELS_CON_CNT      (35)
30 #define RK3188_CRU_CLKSELS_CON(i)       (RK3188_CRU_CLKSEL_CON + ((i) * 4))
31
32 #define RK3188_CRU_CLKGATES_CON_CNT     (10)
33 #define RK3188_CRU_CLKGATES_CON(i)      (RK3188_CRU_CLKGATE_CON + ((i) * 4))
34
35 #define RK3188_CRU_SOFTRSTS_CON_CNT     (9)
36 #define RK3188_CRU_SOFTRSTS_CON(i)      (RK3188_CRU_SOFTRST_CON + ((i) * 4))
37
38 #define RK3188_CRU_MISC_CON             (0x134)
39 #define RK3188_CRU_GLB_CNT_TH           (0x140)
40
41 /******************PLL MODE BITS*******************/
42 #define RK3188_PLL_MODE_MSK(id)         (0x3 << ((id) * 4))
43 #define RK3188_PLL_MODE_SLOW(id)        ((0x0<<((id)*4))|(0x3<<(16+(id)*4)))
44 #define RK3188_PLL_MODE_NORM(id)        ((0x1<<((id)*4))|(0x3<<(16+(id)*4)))
45 #define RK3188_PLL_MODE_DEEP(id)        ((0x2<<((id)*4))|(0x3<<(16+(id)*4)))
46
47 /******************CRU GATINGS**********************************/
48 #define RK3188_CRU_GATEID_CONS(ID) (RK3188_CRU_CLKGATE_CON+(ID/16)*4)
49
50 /*************************RK3288********************************/
51
52 /*******************CRU OFFSET*********************/
53 #define RK3288_CRU_MODE_CON             0x50
54 #define RK3288_CRU_CLKSEL_CON           0x60
55 #define RK3288_CRU_CLKGATE_CON          0x160
56
57 #define RK3288_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
58 #define RK3288_CRU_CLKSELS_CON(i)       (RK3288_CRU_CLKSEL_CON + ((i) * 4))
59 #define RK3288_CRU_CLKGATES_CON(i)      (RK3288_CRU_CLKGATE_CON + ((i) * 4))
60
61 /******************PLL MODE BITS*******************/
62 /*************apll dpll,cpll,gpll,npll 0~4************/
63 #define RK3288_PLLS_MODE_OFFSET(id) ((id)<=3 ? (id*4) : 14)
64 #define RK3288_PLL_MODE_MSK(id)         (0x3 << RK3288_PLLS_MODE_OFFSET(id))
65 #define RK3288_PLL_MODE_SLOW(id)        ((0x0<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
66 #define RK3288_PLL_MODE_NORM(id)        ((0x1<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
67 #define RK3288_PLL_MODE_DEEP(id)        ((0x2<<RK3288_PLLS_MODE_OFFSET(id))|(0x3<<(16+RK3288_PLLS_MODE_OFFSET(id))))
68
69 /*******************CRU GATING*********************/
70 #define RK3288_CRU_CLKGATES_CON_CNT (19)
71 #define RK3288_CRU_CONS_GATEID(i)       (16 * (i))
72 #define RK3288_CRU_GATEID_CONS(ID)      (RK3288_CRU_CLKGATE_CON+(ID/16)*4)
73
74 enum rk3288_cru_clk_gate {
75         /* SCU CLK GATE 0 CON */
76         RK3288_CLKGATE_UART0_SRC    =   (RK3288_CRU_CONS_GATEID(1)+8),   
77         
78         RK3288_CLKGATE_UART4_SRC    =   (RK3288_CRU_CONS_GATEID(2)+12),   
79         
80         RK3288_CLKGATE_PCLK_UART0= (RK3288_CRU_CONS_GATEID(6)+8),   
81         RK3288_CLKGATE_PCLK_UART1,
82         RK3288_CLKGATE6_DUMP1,
83         RK3288_CLKGATE_PCLK_UART3,
84         RK3288_CLKGATE_PCLK_I2C2,
85         RK3288_CLKGATE_PCLK_I2C3,
86         RK3288_CLKGATE_PCLK_I2C4,
87
88         RK3288_CLKGATE_PCLK_I2C0    =   (RK3288_CRU_CONS_GATEID(10)+2), 
89         RK3288_CLKGATE_PCLK_I2C1,
90         
91         RK3288_CLKGATE_PCLK_UART2    =   (RK3288_CRU_CONS_GATEID(11)+9), 
92
93     
94         RK3288_CLKGATE_PCLK_GPIO1   =   (RK3288_CRU_CONS_GATEID(14)+1),
95         
96         RK3288_CLKGATE_PCLK_GPIO0   =   (RK3288_CRU_CONS_GATEID(17)+4),
97         //gate6
98 };
99
100 #define RK3288_CRU_GLB_SRST_FST_VALUE   0x1b0
101 #define RK3288_CRU_GLB_SRST_SND_VALUE   0x1b4
102 #define RK3288_CRU_SOFTRST_CON          0x1b8
103 #define RK3288_CRU_MISC_CON             0x1e8
104 #define RK3288_CRU_GLB_CNT_TH           0x1ec
105 #define RK3288_CRU_GLB_RST_CON          0x1f0
106 #define RK3288_CRU_GLB_RST_ST           0x1f8
107 #define RK3288_CRU_SDMMC_CON0           0x200
108 #define RK3288_CRU_SDMMC_CON1           0x204
109 #define RK3288_CRU_SDIO0_CON0           0x208
110 #define RK3288_CRU_SDIO0_CON1           0x20c
111 #define RK3288_CRU_SDIO1_CON0           0x210
112 #define RK3288_CRU_SDIO1_CON1           0x214
113 #define RK3288_CRU_EMMC_CON0            0x218
114 #define RK3288_CRU_EMMC_CON1            0x21c
115
116 #define RK3288_CRU_SOFTRSTS_CON_CNT     (12)
117 #define RK3288_CRU_SOFTRSTS_CON(i)      (RK3288_CRU_SOFTRST_CON + ((i) * 4))
118
119 static inline void rk3288_cru_set_soft_reset(u32 idx, bool on)
120 {
121         void __iomem *reg = RK_CRU_VIRT + RK3288_CRU_SOFTRSTS_CON(idx >> 4);
122         u32 val = on ? 0x10001U << (idx & 0xf) : 0x10000U << (idx & 0xf);
123         writel_relaxed(val, reg);
124         dsb(sy);
125 }
126
127 #define RK3036_CRU_MODE_CON 0x0040
128
129 /******************PLL MODE BITS*******************/
130 /****************apll dpll,gpll 0~2******************/
131 #define RK3036_PLLS_MODE_OFFSET(id) ((id) < 2 ? (id*4) : 12)
132
133 #define RK3036_PLL_MODE_SLOW(id)        ((0x0 << RK3036_PLLS_MODE_OFFSET(id)) \
134         | (((id) < 2 ? 0x1 : 0x3) << (16 + RK3036_PLLS_MODE_OFFSET(id))))
135
136 #define RK3036_PLL_MODE_MSK(id) (0x1 << RK3036_PLLS_MODE_OFFSET(id))
137
138 #define RK3036_APLL_MODE_SLOW   ((0x0<<0x00)|(0x1<<(16+0x00)))
139 #define RK3036_DPLL_MODE_SLOW   ((0x0<<0x04)|(0x1<<(16+0x04)))
140 #define RK3036_GPLL_MODE_SLOW   ((0x0<<0x12)|(0x3<<(16+0x12)))
141
142 #define RK3036_APLL_MODE_NORM   ((0x1<<0x00)|(0x1<<(16+0x00)))
143 #define RK3036_DPLL_MODE_NORM   ((0x1<<0x04)|(0x1<<(16+0x04)))
144 #define RK3036_GPLL_MODE_NORM   ((0x1<<0x12)|(0x3<<(16+0x12)))
145
146 #define RK3036_GPLL_MODE_DEEP   ((0x10<<0x12)|(0x3<<(16+0x12)))
147
148 #define RK3036_PLL_CONS(id, i)  (((id) < 2 ? id : (id + 1)) * 0x10 + ((i) * 4))
149
150 #define RK3036_CRU_GLB_SRST_FST_VALUE 0x00100
151 #define RK3036_CRU_GLB_SRST_SND_VALUE 0x00104
152 #define RK3036_CRU_SOFTRST0_CON 0x00110
153 #define RK3036_CRU_SOFTRST1_CON 0x00114
154 #define RK3036_CRU_SOFTRST2_CON 0x00118
155 #define RK3036_CRU_SOFTRST3_CON 0x0011c
156 #define RK3036_CRU_SOFTRST4_CON 0x00120
157 #define RK3036_CRU_SOFTRST5_CON 0x00124
158 #define RK3036_CRU_SOFTRST6_CON 0x00128
159 #define RK3036_CRU_SOFTRST7_CON 0x0012c
160 #define RK3036_CRU_SOFTRST8_CON 0x00130
161 #define RK3036_CRU_MISC_CON 0x00134
162 #define RK3036_CRU_GLB_CNT_TH 0x00140
163 #define RK3036_CRU_SDMMC_CON0 0x00144
164 #define RK3036_CRU_SDMMC_CON1 0x00148
165 #define RK3036_CRU_SDIO_CON0 0x0014c
166 #define RK3036_CRU_SDIO_CON1 0x00150
167 #define RK3036_CRU_EMMC_CON0 0x00154
168 #define RK3036_CRU_EMMC_CON1 0x00158
169 #define RK3036_CRU_RST_ST 0x00160
170 #define RK3036_CRU_PLL_MASK_CON 0x001f0
171
172 #define RK3036_CRU_CLKSEL_CON           0x44
173 #define RK3036_CRU_CLKGATE_CON          0xd0
174
175 #define RK3036_CRU_CLKSELS_CON_CNT      (35)
176 #define RK3036_CRU_CLKSELS_CON(i)       (RK3036_CRU_CLKSEL_CON + ((i) * 4))
177
178 #define RK3036_CRU_CLKGATES_CON_CNT     (11)
179 #define RK3036_CRU_CLKGATES_CON(i)      (RK3036_CRU_CLKGATE_CON + ((i) * 4))
180
181 #define RK3036_CRU_SOFTRSTS_CON_CNT     (9)
182 #define RK3036_CRU_SOFTRSTS_CON(i)      (RK3036_CRU_SOFTRST_CON + ((i) * 4))
183
184 /*******************CRU GATING*********************/
185 #define RK3036_CRU_UART_GATE                0xd4
186 #define RK3036_CLKGATE_UART0_SRC        8
187 #define RK3036_CLKGATE_UART0_PCLK      9
188
189 #define RK312X_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
190
191 #define RK312X_CRU_GLB_SRST_FST_VALUE 0x00100
192 #define RK312X_CRU_GLB_SRST_SND_VALUE 0x00104
193 #define RK312X_CRU_MISC_CON 0x00134
194 #define RK312X_CRU_GLB_CNT_TH 0x00140
195 #define RK312X_CRU_GLB_RST_ST 0x00150
196 #define RK312X_CRU_SDMMC_CON0   0x01c0
197 #define RK312X_CRU_SDMMC_CON1   0x01c4
198 #define RK312X_CRU_SDIO_CON0    0x01c8
199 #define RK312X_CRU_SDIO_CON1    0x01cc
200 #define RK312X_CRU_EMMC_CON0    0x01d8
201 #define RK312X_CRU_EMMC_CON1    0x01dc
202 #define RK312X_CRU_PLL_PRG_EN   0x01f0
203 #define RK312X_CRU_MODE_CON             0x40
204 #define RK312X_CRU_RST_ST 0x00160
205 #define RK312X_CRU_PLL_MASK_CON 0x001f0
206
207 #define RK312X_CRU_CLKSEL_CON           0x44
208 #define RK312X_CRU_CLKGATE_CON          0xd0
209
210 #define RK312X_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
211
212 /******************PLL MODE BITS*******************/
213 #define RK312X_PLLS_MODE_OFFSET(id) ((id) <= 3 ? (id * 4) : 14)
214 #define RK312X_PLL_MODE_MSK(id)         (0x1 << RK312X_PLLS_MODE_OFFSET(id))
215 #define RK312X_PLL_MODE_SLOW(id)        ((0x0 << RK312X_PLLS_MODE_OFFSET(id))\
216 | (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
217 #define RK312X_PLL_MODE_NORM(id)        ((0x1 << RK312X_PLLS_MODE_OFFSET(id))\
218 | (0x1 << (16 + RK312X_PLLS_MODE_OFFSET(id))))
219
220
221 #define RK312X_CRU_SOFTRST_CON          0x110
222
223 #define RK312X_CRU_CLKSELS_CON_CNT      (35)
224 #define RK312X_CRU_CLKSELS_CON(i)       (RK3036_CRU_CLKSEL_CON + ((i) * 4))
225
226 #define RK312X_CRU_CLKGATES_CON_CNT     (11)
227 #define RK312X_CRU_CLKGATES_CON(i)      (RK3036_CRU_CLKGATE_CON + ((i) * 4))
228
229 #define RK312X_CRU_SOFTRSTS_CON_CNT     (9)
230 #define RK312X_CRU_SOFTRSTS_CON(i)      (RK312X_CRU_SOFTRST_CON + ((i) * 4))
231
232 /*******************CRU GATING*********************/
233 #define RK312X_CRU_CONS_GATEID(i)       (16 * (i))
234 #define RK312X_CRU_GATEID_CONS(ID)      (RK312X_CRU_CLKGATE_CON\
235         + ((ID) / 16) * 4)
236
237 enum rk312x_cru_clk_gate {
238         /* SCU CLK GATE 0 CON */
239         RK312X_CLKGATE_UART0_SRC = (RK312X_CRU_CONS_GATEID(1) + 8),
240         RK312X_CLKGATE_PCLK_UART0 = (RK312X_CRU_CONS_GATEID(8) + 0),
241         RK312X_CLKGATE_PCLK_UART1,
242         RK312X_CLKGATE_PCLK_UART2,
243 };
244
245 /*************************RK3368********************************/
246
247 /*******************CRU OFFSET*********************/
248 #define RK3368_CRU_CLKSEL_CON           0x100
249 #define RK3368_CRU_CLKGATE_CON          0x200
250
251 #define RK3368_PLL_CONS(id, i)          ((id) * 0x10 + ((i) * 4))
252 #define RK3368_CRU_CLKSELS_CON(i)       (RK3368_CRU_CLKSEL_CON + ((i) * 4))
253 #define RK3368_CRU_CLKGATES_CON(i)      (RK3368_CRU_CLKGATE_CON + ((i) * 4))
254
255 #define RK3368_CRU_SOFTRSTS_CON_CNT     (15)
256 #define RK3368_CRU_SOFTRST_CON          0x300
257 #define RK3368_CRU_SOFTRSTS_CON(i)      (RK3368_CRU_SOFTRST_CON + ((i) * 4))
258
259 #endif