1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include<linux/completion.h>
21 #include<linux/spinlock.h>
22 #include<asm/atomic.h>
23 #include<mach/board.h>
24 #include<linux/rk_screen.h>
26 #define RK30_MAX_LCDC_SUPPORT 4
27 #define RK30_MAX_LAYER_SUPPORT 4
28 #define RK_MAX_FB_SUPPORT 8
32 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
33 #define FB0_IOCTL_SET_PANEL 0x6002
39 #define FB0_IOCTL_SET_BUF 0x6017
40 #define FB0_IOCTL_COPY_CURBUF 0x6018
41 #define FB0_IOCTL_CLOSE_BUF 0x6019
44 #define FBIOGET_PANEL_SIZE 0x5001
45 #define FBIOSET_YUV_ADDR 0x5002
46 //#define FB1_TOCTL_SET_MCU_DIR 0x5003
47 #define FBIOSET_ROTATE 0x5003
48 #define FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
49 #define FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
50 #define FBIOSET_OVERLAY_STATE 0x5018
51 #define FBIOSET_ENABLE 0x5019
52 #define FBIOGET_ENABLE 0x5020
54 /********************************************************************
55 ** display output interface supported by rockchip lcdc *
56 ********************************************************************/
58 #define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
59 #define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
64 #define OUT_S888DUMY 12
65 #define OUT_P16BPP4 24
66 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
67 #define OUT_D888_P565 0x22
70 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
74 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
75 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
76 HAL_PIXEL_FORMAT_RGB_888 = 3,
77 HAL_PIXEL_FORMAT_RGB_565 = 4,
78 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
79 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
80 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
82 /* 0x8 - 0xFF range unavailable */
87 * This range is reserved for pixel formats that are specific to the HAL
88 * implementation. Implementations can use any value in this range to
89 * communicate video pixel formats between their HAL modules. These formats
90 * must not have an alpha channel. Additionally, an EGLimage created from a
91 * gralloc buffer of one of these formats must be supported for use with the
92 * GL_OES_EGL_image_external OpenGL ES extension.
98 * This format is exposed outside of the HAL to software decoders and
99 * applications. EGLImageKHR must support it in conjunction with the
100 * OES_EGL_image_external extension.
102 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
103 * by (W/2) x (H/2) Cr and Cb planes.
105 * This format assumes
108 * - a horizontal stride multiple of 16 pixels
109 * - a vertical stride equal to the height
111 * y_size = stride * height
112 * c_size = ALIGN(stride/2, 16) * height/2
113 * size = y_size + c_size * 2
115 * cb_offset = y_size + c_size
118 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
122 /* Legacy formats (deprecated), used by ImageFormat.java */
123 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
124 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
125 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
126 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
127 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
128 HAL_PIXEL_FORMAT_YCrCb_444 = 0x22, //yuv444
134 //display data format
144 enum fb_win_map_order{
145 FB_DEFAULT_ORDER = 0,
146 FB0_WIN2_FB1_WIN1_FB2_WIN0 = 12,
147 FB0_WIN1_FB1_WIN2_FB2_WIN0 = 21,
148 FB0_WIN2_FB1_WIN0_FB2_WIN1 = 102,
149 FB0_WIN0_FB1_WIN2_FB2_WIN1 = 120,
150 FB0_WIN0_FB1_WIN1_FB2_WIN2 = 210,
151 FB0_WIN1_FB1_WIN0_FB2_WIN2 = 201,
155 struct fb_bitfield red;
156 struct fb_bitfield green;
157 struct fb_bitfield blue;
158 struct fb_bitfield transp;
161 typedef enum _TRSP_MODE
175 bool state; //on or off
177 u32 y_offset; //yuv/rgb offset -->LCDC_WINx_YRGB_MSTx
178 u32 c_offset; //cb cr offset--->LCDC_WINx_CBR_MSTx
179 u32 xpos; //start point in panel --->LCDC_WINx_DSP_ST
181 u16 xsize; // display window width/height -->LCDC_WINx_DSP_INFO
183 u16 xact; //origin display window size -->LCDC_WINx_ACT_INFO
185 u16 xvir; //virtual width/height -->LCDC_WINx_VIR
187 unsigned long smem_start;
188 unsigned long cbr_start; // Cbr memory start address
189 enum data_format format;
195 struct rk_lcdc_device_driver{
200 struct layer_par *layer_par[RK_MAX_FB_SUPPORT];
201 struct layer_par *def_layer_par;
203 int num_buf; //the num_of buffer
204 int fb_index_base; //the first fb index of the lcdc device
205 rk_screen *screen0; //some platform have only one lcdc,but extend
206 rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
207 rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
214 struct mutex fb_win_id_mutex;
216 struct completion frame_done; //sync for pan_display,whe we set a new frame address to lcdc register,we must make sure the frame begain to display
217 spinlock_t cpl_lock; //lock for completion frame done
220 struct rk29fb_info *screen_ctr_info;
221 int (*open)(struct rk_lcdc_device_driver *dev_drv,int layer_id,bool open);
222 int (*init_lcdc)(struct rk_lcdc_device_driver *dev_drv);
223 int (*ioctl)(struct rk_lcdc_device_driver *dev_drv, unsigned int cmd,unsigned long arg,int layer_id);
224 int (*suspend)(struct rk_lcdc_device_driver *dev_drv);
225 int (*resume)(struct rk_lcdc_device_driver *dev_drv);
226 int (*blank)(struct rk_lcdc_device_driver *dev_drv,int layer_id,int blank_mode);
227 int (*set_par)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
228 int (*pan_display)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
229 ssize_t (*get_disp_info)(struct rk_lcdc_device_driver *dev_drv,char *buf,int layer_id);
230 int (*load_screen)(struct rk_lcdc_device_driver *dev_drv, bool initscreen);
231 int (*get_layer_state)(struct rk_lcdc_device_driver *dev_drv,int layer_id);
232 int (*ovl_mgr)(struct rk_lcdc_device_driver *dev_drv,int swap,bool set); //overlay manager
233 int (*fps_mgr)(struct rk_lcdc_device_driver *dev_drv,int fps,bool set);
234 int (*fb_get_layer)(struct rk_lcdc_device_driver *dev_drv,const char *id); //find layer for fb
235 int (*fb_layer_remap)(struct rk_lcdc_device_driver *dev_drv,enum fb_win_map_order order);
236 int (*set_dsp_lut)(struct rk_lcdc_device_driver *dev_drv,int *lut);
237 int (*read_dsp_lut)(struct rk_lcdc_device_driver *dev_drv,int *lut);
238 int (*lcdc_hdmi_process)(struct rk_lcdc_device_driver *dev_drv,int mode); //some lcdc need to some process in hdmi mode
239 int (*lcdc_rst)(struct rk_lcdc_device_driver *dev_drv);
244 struct rk29fb_info * mach_info; //lcd io control info
245 struct fb_info *fb[RK_MAX_FB_SUPPORT];
248 struct rk_lcdc_device_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
251 int video_mode; //when play video set it to 1
252 struct workqueue_struct *workqueue;
253 struct delayed_work delay_work;
255 extern int rk_fb_register(struct rk_lcdc_device_driver *dev_drv,
256 struct rk_lcdc_device_driver *def_drv,int id);
257 extern int rk_fb_unregister(struct rk_lcdc_device_driver *dev_drv);
258 extern int get_fb_layer_id(struct fb_fix_screeninfo *fix);
259 extern struct rk_lcdc_device_driver * rk_get_lcdc_drv(char *name);
260 extern int rk_fb_switch_screen(rk_screen *screen ,int enable ,int lcdc_id);
261 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y,u8 lcdc_id);
262 extern int rkfb_create_sysfs(struct fb_info *fbi);
263 static int inline rk_fb_calc_fps(rk_screen *screen,u32 pixclock)
266 unsigned long long hz;
269 printk(KERN_ERR "%s:null screen!\n",__func__);
272 x = screen->x_res + screen->left_margin + screen->right_margin + screen->hsync_len;
273 y = screen->y_res + screen->upper_margin + screen->lower_margin + screen->vsync_len;
275 hz = 1000000000000ULL; /* 1e12 picoseconds per second */
278 do_div(hz, x * y); /* divide by x * y with rounding */
281 do_div(hz,pixclock); /* divide by pixclock with rounding */