1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/rkfb/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
33 #define RK30_MAX_LCDC_SUPPORT 4
34 #define RK30_MAX_LAYER_SUPPORT 4
35 #define RK_MAX_FB_SUPPORT 4
36 #define RK_WIN_MAX_AREA 4
37 #define RK_MAX_BUF_NUM 10
39 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
40 #define FB0_IOCTL_SET_PANEL 0x6002
46 #define FB0_IOCTL_SET_BUF 0x6017
47 #define FB0_IOCTL_COPY_CURBUF 0x6018
48 #define FB0_IOCTL_CLOSE_BUF 0x6019
51 #define RK_FBIOGET_PANEL_SIZE 0x5001
52 #define RK_FBIOSET_YUV_ADDR 0x5002
53 #define RK_FBIOGET_SCREEN_STATE 0X4620
54 #define RK_FBIOGET_16OR32 0X4621
55 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
56 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
58 #define RK_FBIOGET_DMABUF_FD 0x5003
59 #define RK_FBIOSET_DMABUF_FD 0x5004
60 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
61 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
62 #define RK_FBIOSET_OVERLAY_STATE 0x5018
63 #define RK_FBIOGET_OVERLAY_STATE 0X4619
64 #define RK_FBIOSET_ENABLE 0x5019
65 #define RK_FBIOGET_ENABLE 0x5020
66 #define RK_FBIOSET_CONFIG_DONE 0x4628
67 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
68 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
69 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
70 #define RK_FBIOGET_DSP_ADDR 0x4630
71 #define RK_FBIOGET_LIST_STAT 0X4631
75 #define RK_LF_STATUS_FC 0xef
76 #define RK_LF_STATUS_FR 0xee
77 #define RK_LF_STATUS_NC 0xfe
78 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
80 #if defined(CONFIG_ION_ROCKCHIP)
81 extern struct ion_client *rockchip_ion_client_create(const char * name);
84 extern int rk_fb_poll_prmry_screen_vblank(void);
85 extern int rk_fb_get_prmry_screen_ft(void);
86 extern bool rk_fb_poll_wait_frame_complete(void);
88 /********************************************************************
89 ** display output interface supported by rockchip lcdc *
90 ********************************************************************/
92 #define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
93 #define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
98 #define OUT_S888DUMY 12
99 #define OUT_RGB_AAA 15
100 #define OUT_P16BPP4 24
101 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
102 #define OUT_D888_P565 0x22
105 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
109 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
110 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
111 HAL_PIXEL_FORMAT_RGB_888 = 3,
112 HAL_PIXEL_FORMAT_RGB_565 = 4,
113 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
114 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
115 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
117 /* 0x8 - 0xFF range unavailable */
122 * This range is reserved for pixel formats that are specific to the HAL
123 * implementation. Implementations can use any value in this range to
124 * communicate video pixel formats between their HAL modules. These formats
125 * must not have an alpha channel. Additionally, an EGLimage created from a
126 * gralloc buffer of one of these formats must be supported for use with the
127 * GL_OES_EGL_image_external OpenGL ES extension.
131 * Android YUV format:
133 * This format is exposed outside of the HAL to software decoders and
134 * applications. EGLImageKHR must support it in conjunction with the
135 * OES_EGL_image_external extension.
137 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
138 * by (W/2) x (H/2) Cr and Cb planes.
140 * This format assumes
143 * - a horizontal stride multiple of 16 pixels
144 * - a vertical stride equal to the height
146 * y_size = stride * height
147 * c_size = ALIGN(stride/2, 16) * height/2
148 * size = y_size + c_size * 2
150 * cb_offset = y_size + c_size
153 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
155 /* Legacy formats (deprecated), used by ImageFormat.java */
156 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
157 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
158 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
159 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
160 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
161 HAL_PIXEL_FORMAT_YCrCb_444 = 0x22, //yuv444
162 HAL_PIXEL_FORMAT_H265 = 0x23, //yuv444
166 //display data format
179 enum fb_win_map_order {
180 FB_DEFAULT_ORDER = 0,
181 FB0_WIN2_FB1_WIN1_FB2_WIN0 = 12,
182 FB0_WIN1_FB1_WIN2_FB2_WIN0 = 21,
183 FB0_WIN2_FB1_WIN0_FB2_WIN1 = 102,
184 FB0_WIN0_FB1_WIN2_FB2_WIN1 = 120,
185 FB0_WIN0_FB1_WIN1_FB2_WIN2 = 210,
186 FB0_WIN1_FB1_WIN0_FB2_WIN2 = 201,
187 FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3 = 3210,
199 struct fb_bitfield red;
200 struct fb_bitfield green;
201 struct fb_bitfield blue;
202 struct fb_bitfield transp;
206 wait_queue_head_t wait;
211 struct mutex irq_lock;
212 struct task_struct *thread;
215 struct color_key_cfg {
216 u32 win0_color_key_cfg;
217 u32 win1_color_key_cfg;
218 u32 win2_color_key_cfg;
232 struct rk_disp_pwr_ctr_list {
233 struct list_head list;
234 struct pwr_ctr pwr_ctr;
237 typedef enum _TRSP_MODE {
247 struct rk_lcdc_post_cfg{
256 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
257 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
258 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
260 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
262 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
264 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
266 unsigned long smem_start;
267 unsigned long cbr_start; /*Cbr memory start address*/
268 #if defined(CONFIG_ION_ROCKCHIP)
269 struct ion_handle *ion_hdl;
285 bool state; /*on or off*/
287 enum data_format format;
288 u8 z_order; /*win sel layer*/
303 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
304 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
305 u8 yrgb_hsd_mode;//h scale down mode
306 u8 yrgb_vsu_mode;//v scale up mode
307 u8 yrgb_vsd_mode;//v scale down mode
323 struct rk_lcdc_area area[RK_WIN_MAX_AREA];
324 struct rk_lcdc_post_cfg post_cfg;
327 struct rk_lcdc_driver;
329 struct rk_fb_trsm_ops {
331 int (*disable)(void);
334 struct rk_lcdc_drv_ops {
335 int (*open) (struct rk_lcdc_driver * dev_drv, int layer_id, bool open);
336 int (*init_lcdc) (struct rk_lcdc_driver * dev_drv);
337 int (*ioctl) (struct rk_lcdc_driver * dev_drv, unsigned int cmd,
338 unsigned long arg, int layer_id);
339 int (*suspend) (struct rk_lcdc_driver * dev_drv);
340 int (*resume) (struct rk_lcdc_driver * dev_drv);
341 int (*blank) (struct rk_lcdc_driver * dev_drv, int layer_id,
343 int (*set_par) (struct rk_lcdc_driver * dev_drv, int layer_id);
344 int (*pan_display) (struct rk_lcdc_driver * dev_drv, int layer_id);
345 int (*lcdc_reg_update) (struct rk_lcdc_driver * dev_drv);
346 ssize_t(*get_disp_info) (struct rk_lcdc_driver * dev_drv, char *buf,
348 int (*load_screen) (struct rk_lcdc_driver * dev_drv, bool initscreen);
349 int (*get_win_state) (struct rk_lcdc_driver * dev_drv, int layer_id);
350 int (*ovl_mgr) (struct rk_lcdc_driver * dev_drv, int swap, bool set); //overlay manager
351 int (*fps_mgr) (struct rk_lcdc_driver * dev_drv, int fps, bool set);
352 int (*fb_get_win_id) (struct rk_lcdc_driver * dev_drv, const char *id); //find layer for fb
353 int (*fb_win_remap) (struct rk_lcdc_driver * dev_drv,
354 enum fb_win_map_order order);
355 int (*set_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
356 int (*read_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
357 int (*lcdc_hdmi_process) (struct rk_lcdc_driver * dev_drv, int mode); //some lcdc need to some process in hdmi mode
358 int (*poll_vblank) (struct rk_lcdc_driver * dev_drv);
359 int (*lcdc_rst) (struct rk_lcdc_driver * dev_drv);
360 int (*dpi_open) (struct rk_lcdc_driver * dev_drv, bool open);
361 int (*dpi_win_sel) (struct rk_lcdc_driver * dev_drv, int layer_id);
362 int (*dpi_status) (struct rk_lcdc_driver * dev_drv);
363 int (*get_dsp_addr)(struct rk_lcdc_driver * dev_drv,unsigned int *dsp_addr);
364 int (*set_dsp_cabc) (struct rk_lcdc_driver * dev_drv, int mode);
365 int (*set_dsp_hue) (struct rk_lcdc_driver *dev_drv,int hue);
366 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,int bri,int con,int sat);
367 int (*dump_reg) (struct rk_lcdc_driver * dev_drv);
370 struct rk_fb_area_par {
372 unsigned long phy_addr;
376 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
378 u32 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
380 u32 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
382 u32 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
387 struct rk_fb_win_par {
388 u8 data_format; /*layer data fmt*/
390 u8 z_order; /*win sel layer*/
391 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
396 struct rk_fb_win_cfg_data {
398 u16 rel_fence_fd[RK_MAX_BUF_NUM];
399 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
400 struct rk_lcdc_post_cfg post_cfg;
405 struct rk_fb_reg_area_data {
406 struct sync_fence *acq_fence;
407 u8 index_buf; /*judge if the buffer is index*/
408 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
409 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
412 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
414 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
416 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
418 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
420 unsigned long smem_start;
421 unsigned long cbr_start; /*Cbr memory start address*/
425 struct rk_fb_reg_win_data {
426 u8 data_format; /*layer data fmt*/
428 u8 z_order; /*win sel layer*/
429 u32 area_num; /*maybe two region have the same dma buff,*/
430 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
436 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
439 struct rk_fb_reg_data {
440 struct list_head list;
444 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
445 struct rk_lcdc_post_cfg post_cfg;
446 //struct sync_fence *acq_fence[RK_MAX_BUF_NUM];
447 //int fence_wait_begin;
450 struct rk_lcdc_driver {
456 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
458 int num_buf; //the num_of buffer
460 int fb_index_base; //the first fb index of the lcdc device
461 struct rk_screen *screen0; //some platform have only one lcdc,but extend
462 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
463 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
470 struct mutex fb_win_id_mutex;
472 struct completion frame_done; //sync for pan_display,whe we set a new frame address to lcdc register,we must make sure the frame begain to display
473 spinlock_t cpl_lock; //lock for completion frame done
475 struct rk_fb_vsync vsync_info;
476 int wait_fs; //wait for new frame start in kernel
477 struct sw_sync_timeline *timeline;
480 struct list_head update_regs_list;
481 struct mutex update_regs_list_lock;
482 struct kthread_worker update_regs_worker;
483 struct task_struct *update_regs_thread;
484 struct kthread_work update_regs_work;
486 struct mutex output_lock;
487 struct rk29fb_info *screen_ctr_info;
488 struct list_head pwrlist_head;
489 struct rk_lcdc_drv_ops *ops;
490 struct rk_fb_trsm_ops *trsm_ops;
494 /*disp_mode: dual display mode
495 * NO_DUAL,no dual display,
496 ONE_DUAL,use one lcdc + rk61x for dual display
497 DUAL,use 2 lcdcs for dual display
498 num_fb: the total number of fb
499 num_lcdc: the total number of lcdc
504 struct rk29fb_info *mach_info;
505 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
508 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
511 #if defined(CONFIG_ION_ROCKCHIP)
512 struct ion_client * ion_client;
518 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
519 extern struct rk_fb_trsm_ops * rk_fb_trsm_ops_get(int type);
520 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
521 struct rk_lcdc_win *win, int id);
522 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
523 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
524 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
525 extern u32 rk_fb_get_prmry_screen_pixclock(void);
526 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
527 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
528 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
529 extern bool is_prmry_rk_lcdc_registered(void);
530 extern int rk_fb_prase_timing_dt(struct device_node *np,
531 struct rk_screen *screen);
533 static int inline support_uboot_display(void)
538 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
540 extern int rk_fb_dpi_open(bool open);
541 extern int rk_fb_dpi_layer_sel(int layer_id);
542 extern int rk_fb_dpi_status(void);
544 extern int rk_fb_switch_screen(struct rk_screen * screen, int enable, int lcdc_id);
545 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
546 extern int rkfb_create_sysfs(struct fb_info *fbi);
547 extern char *get_format_string(enum data_format, char *fmt);
548 extern int support_uboot_display(void);
549 extern int rk_fb_calc_fps(struct rk_screen * screen, u32 pixclock);