1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/rkfb/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
33 #define RK30_MAX_LCDC_SUPPORT 2
34 #define RK30_MAX_LAYER_SUPPORT 5
35 #define RK_MAX_FB_SUPPORT 5
36 #define RK_WIN_MAX_AREA 4
37 #define RK_MAX_BUF_NUM 11
39 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
40 #define FB0_IOCTL_SET_PANEL 0x6002
46 #define FB0_IOCTL_SET_BUF 0x6017
47 #define FB0_IOCTL_COPY_CURBUF 0x6018
48 #define FB0_IOCTL_CLOSE_BUF 0x6019
51 #define RK_FBIOGET_PANEL_SIZE 0x5001
52 #define RK_FBIOSET_YUV_ADDR 0x5002
53 #define RK_FBIOGET_SCREEN_STATE 0X4620
54 #define RK_FBIOGET_16OR32 0X4621
55 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
56 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
57 #define RK_FBIOSET_HWC_ADDR 0x4624
59 #define RK_FBIOGET_DMABUF_FD 0x5003
60 #define RK_FBIOSET_DMABUF_FD 0x5004
61 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
62 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
63 #define RK_FBIOSET_OVERLAY_STA 0x5018
64 #define RK_FBIOGET_OVERLAY_STA 0X4619
65 #define RK_FBIOSET_ENABLE 0x5019
66 #define RK_FBIOGET_ENABLE 0x5020
67 #define RK_FBIOSET_CONFIG_DONE 0x4628
68 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
69 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
70 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
71 #define RK_FBIOGET_DSP_ADDR 0x4630
72 #define RK_FBIOGET_LIST_STA 0X4631
73 #define RK_FBIOGET_IOMMU_STA 0x4632
74 #define RK_FBIOSET_CLEAR_FB 0x4633
78 #define RK_LF_STATUS_FC 0xef
79 #define RK_LF_STATUS_FR 0xee
80 #define RK_LF_STATUS_NC 0xfe
81 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
84 /* x y mirror or rotate mode */
86 #define X_MIRROR 1 /* up-down flip*/
87 #define Y_MIRROR 2 /* left-right flip */
88 #define X_Y_MIRROR 3 /* the same as rotate 180 degrees */
89 #define ROTATE_90 4 /* clockwise rotate 90 degrees */
90 #define ROTATE_180 8 /* rotate 180 degrees
91 * It is recommended to use X_Y_MIRROR
92 * rather than ROTATE_180
94 #define ROTATE_270 12 /* clockwise rotate 270 degrees */
98 * pixel align value for gpu,align as 64 bytes in an odd number of times
100 #define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
101 #define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
102 #define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
103 #define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
104 #define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
107 //#define USE_ION_MMU 1
108 #if defined(CONFIG_ION_ROCKCHIP)
109 extern struct ion_client *rockchip_ion_client_create(const char *name);
112 extern int rk_fb_poll_prmry_screen_vblank(void);
113 extern u32 rk_fb_get_prmry_screen_ft(void);
114 extern u32 rk_fb_get_prmry_screen_vbt(void);
115 extern u64 rk_fb_get_prmry_screen_framedone_t(void);
116 extern int rk_fb_set_prmry_screen_status(int status);
117 extern bool rk_fb_poll_wait_frame_complete(void);
119 /********************************************************************
120 ** display output interface supported by rockchip lcdc *
121 ********************************************************************/
123 #define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
124 #define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
127 #define OUT_CCIR656 6
129 #define OUT_S888DUMY 12
130 #define OUT_YUV_420 14
131 #define OUT_RGB_AAA 15
132 #define OUT_P16BPP4 24
133 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
134 #define OUT_D888_P565 0x22
137 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
141 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
142 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
143 HAL_PIXEL_FORMAT_RGB_888 = 3,
144 HAL_PIXEL_FORMAT_RGB_565 = 4,
145 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
146 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
147 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
149 /* 0x8 - 0xFF range unavailable */
154 * This range is reserved for pixel formats that are specific to the HAL
155 * implementation. Implementations can use any value in this range to
156 * communicate video pixel formats between their HAL modules. These formats
157 * must not have an alpha channel. Additionally, an EGLimage created from a
158 * gralloc buffer of one of these formats must be supported for use with the
159 * GL_OES_EGL_image_external OpenGL ES extension.
163 * Android YUV format:
165 * This format is exposed outside of the HAL to software decoders and
166 * applications. EGLImageKHR must support it in conjunction with the
167 * OES_EGL_image_external extension.
169 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
170 * by (W/2) x (H/2) Cr and Cb planes.
172 * This format assumes
175 * - a horizontal stride multiple of 16 pixels
176 * - a vertical stride equal to the height
178 * y_size = stride * height
179 * c_size = ALIGN(stride/2, 16) * height/2
180 * size = y_size + c_size * 2
182 * cb_offset = y_size + c_size
185 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
187 /* Legacy formats (deprecated), used by ImageFormat.java */
188 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
189 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
190 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
191 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
192 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
194 HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
195 HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
196 HAL_PIXEL_FORMAT_YCrCb_420_SP_10 = 0x24, //YUV444_1obit
198 HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
203 //display data format
238 SCREEN_PREPARE_DDR_CHANGE = 0x0,
239 SCREEN_UNPREPARE_DDR_CHANGE,
243 struct fb_bitfield red;
244 struct fb_bitfield green;
245 struct fb_bitfield blue;
246 struct fb_bitfield transp;
249 struct rk_fb_frame_time {
250 u64 last_framedone_t;
256 wait_queue_head_t wait;
261 struct mutex irq_lock;
262 struct task_struct *thread;
265 struct color_key_cfg {
266 u32 win0_color_key_cfg;
267 u32 win1_color_key_cfg;
268 u32 win2_color_key_cfg;
277 const char *rgl_name;
282 struct rk_disp_pwr_ctr_list {
283 struct list_head list;
284 struct pwr_ctr pwr_ctr;
287 typedef enum _TRSP_MODE {
297 struct rk_lcdc_post_cfg {
304 struct rk_lcdc_bcsh {
313 struct rk_lcdc_win_area {
315 enum data_format format;
318 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
319 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
320 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
322 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
324 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
326 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
328 u16 xoff; /*mem offset*/
330 unsigned long smem_start;
331 unsigned long cbr_start; /*Cbr memory start address*/
332 #if defined(CONFIG_ION_ROCKCHIP)
333 struct ion_handle *ion_hdl;
335 struct dma_buf *dma_buf;
347 u8 fbdc_dsp_width_ratio;
349 u16 fbdc_mb_vir_width;
350 u16 fbdc_mb_vir_height;
356 u16 fbdc_cmp_index_init;
363 bool state; /*on or off*/
364 bool last_state; /*on or off*/
366 int z_order; /*win sel layer*/
379 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
380 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
381 u8 yrgb_hsd_mode;//h scale down mode
382 u8 yrgb_vsu_mode;//v scale up mode
383 u8 yrgb_vsd_mode;//v scale down mode
401 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
402 struct rk_lcdc_post_cfg post_cfg;
405 struct rk_lcdc_driver;
407 struct rk_fb_trsm_ops {
409 int (*disable)(void);
410 int (*dsp_pwr_on) (void);
411 int (*dsp_pwr_off) (void);
414 struct rk_lcdc_drv_ops {
415 int (*open) (struct rk_lcdc_driver *dev_drv, int layer_id, bool open);
416 int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
417 int (*init_lcdc) (struct rk_lcdc_driver *dev_drv);
418 int (*ioctl) (struct rk_lcdc_driver *dev_drv, unsigned int cmd,
419 unsigned long arg, int layer_id);
420 int (*suspend) (struct rk_lcdc_driver *dev_drv);
421 int (*resume) (struct rk_lcdc_driver *dev_drv);
422 int (*blank) (struct rk_lcdc_driver *dev_drv, int layer_id,
424 int (*set_par) (struct rk_lcdc_driver *dev_drv, int layer_id);
425 int (*pan_display) (struct rk_lcdc_driver *dev_drv, int layer_id);
426 int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
427 int (*lcdc_reg_update) (struct rk_lcdc_driver *dev_drv);
428 ssize_t(*get_disp_info) (struct rk_lcdc_driver *dev_drv, char *buf,
430 int (*load_screen) (struct rk_lcdc_driver *dev_drv, bool initscreen);
431 int (*get_win_state) (struct rk_lcdc_driver *dev_drv, int layer_id);
432 int (*ovl_mgr) (struct rk_lcdc_driver *dev_drv, int swap, bool set); /*overlay manager*/
433 int (*fps_mgr) (struct rk_lcdc_driver *dev_drv, int fps, bool set);
434 int (*fb_get_win_id) (struct rk_lcdc_driver *dev_drv, const char *id); /*find layer for fb*/
435 int (*fb_win_remap) (struct rk_lcdc_driver *dev_drv,
436 u16 fb_win_map_order);
437 int (*set_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
438 int (*set_hwc_lut) (struct rk_lcdc_driver *dev_drv, int *hwc_lut, int mode);
439 int (*read_dsp_lut) (struct rk_lcdc_driver *dev_drv, int *lut);
440 int (*lcdc_hdmi_process) (struct rk_lcdc_driver *dev_drv, int mode); /*some lcdc need to some process in hdmi mode*/
441 int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
442 int (*poll_vblank) (struct rk_lcdc_driver *dev_drv);
443 int (*lcdc_rst) (struct rk_lcdc_driver *dev_drv);
444 int (*dpi_open) (struct rk_lcdc_driver *dev_drv, bool open);
445 int (*dpi_win_sel) (struct rk_lcdc_driver *dev_drv, int layer_id);
446 int (*dpi_status) (struct rk_lcdc_driver *dev_drv);
447 int (*get_dsp_addr)(struct rk_lcdc_driver *dev_drv,unsigned int *dsp_addr);
448 int (*set_dsp_cabc) (struct rk_lcdc_driver *dev_drv, int mode);
449 int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
450 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
451 int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
452 int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
453 int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
454 int (*set_screen_scaler) (struct rk_lcdc_driver *dev_drv, struct rk_screen *screen, bool enable);
455 int (*dump_reg) (struct rk_lcdc_driver *dev_drv);
456 int (*mmu_en) (struct rk_lcdc_driver *dev_drv);
457 int (*cfg_done) (struct rk_lcdc_driver *dev_drv);
458 int (*set_overscan) (struct rk_lcdc_driver *dev_drv,
459 struct overscan *overscan);
460 int (*dsp_black) (struct rk_lcdc_driver *dev_drv, int enable);
463 struct rk_fb_area_par {
464 u8 data_format; /*layer data fmt*/
466 unsigned long phy_addr;
470 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
472 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
474 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
476 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
486 struct rk_fb_win_par {
488 u8 z_order; /*win sel layer*/
492 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
496 struct rk_fb_win_cfg_data {
499 short rel_fence_fd[RK_MAX_BUF_NUM];
500 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
501 struct rk_lcdc_post_cfg post_cfg;
504 struct rk_fb_reg_area_data {
505 struct sync_fence *acq_fence;
506 u8 data_format; /*layer data fmt*/
507 u8 index_buf; /*judge if the buffer is index*/
508 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
509 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
512 u16 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
514 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
516 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
518 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
520 u16 xoff; /*mem offset*/
522 unsigned long smem_start;
523 unsigned long cbr_start; /*Cbr memory start address*/
525 struct ion_handle *ion_handle;
527 struct dma_buf *dma_buf;
528 struct dma_buf_attachment *attachment;
529 struct sg_table *sg_table;
537 struct rk_fb_reg_win_data {
539 u8 z_order; /*win sel layer*/
540 u32 area_num; /*maybe two region have the same dma buff,*/
541 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
547 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
550 struct rk_fb_reg_data {
551 struct list_head list;
555 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
556 struct rk_lcdc_post_cfg post_cfg;
559 struct rk_lcdc_driver {
565 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
567 int num_buf; //the num_of buffer
569 int fb_index_base; //the first fb index of the lcdc device
570 struct rk_screen *screen0; //some platform have only one lcdc,but extend
571 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
572 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
586 char mmu_dts_name[40];
587 struct device *mmu_dev;
590 struct rk_fb_reg_area_data reg_area_data;
592 * front_regs means this config is scaning on the devices.
594 struct rk_fb_reg_data *front_regs;
595 struct mutex front_lock;
597 struct mutex fb_win_id_mutex;
598 struct mutex win_config;
600 struct completion frame_done; /*sync for pan_display,whe we set a new
601 frame address to lcdc register,we must
602 make sure the frame begain to display*/
603 spinlock_t cpl_lock; /*lock for completion frame done */
605 struct rk_fb_vsync vsync_info;
606 struct rk_fb_frame_time frame_time;
607 int wait_fs; /*wait for new frame start in kernel */
608 struct sw_sync_timeline *timeline;
611 struct list_head update_regs_list;
612 struct mutex update_regs_list_lock;
613 struct kthread_worker update_regs_worker;
614 struct task_struct *update_regs_thread;
615 struct kthread_work update_regs_work;
616 wait_queue_head_t update_regs_wait;
618 struct mutex output_lock;
619 struct rk29fb_info *screen_ctr_info;
620 struct list_head pwrlist_head;
621 struct rk_lcdc_drv_ops *ops;
622 struct rk_fb_trsm_ops *trsm_ops;
623 #ifdef CONFIG_DRM_ROCKCHIP
624 void (*irq_call_back)(struct rk_lcdc_driver *driver);
626 struct overscan overscan;
627 struct rk_lcdc_bcsh bcsh;
630 int bcsh_init_status;
637 unsigned long fb_phy_base; /* Start of fb address (physical address) */
638 char __iomem *fb_virt_base; /* Start of fb address (virt address) */
640 struct rk_lcdc_driver *lcdc_drv;
642 #if defined(CONFIG_ION_ROCKCHIP)
643 struct ion_handle *ion_hdl;
648 /*disp_mode: dual display mode
649 * NO_DUAL,no dual display,
650 ONE_DUAL,use one lcdc + rk61x for dual display
651 DUAL,use 2 lcdcs for dual display
652 num_fb: the total number of fb
653 num_lcdc: the total number of lcdc
659 struct rk29fb_info *mach_info;
660 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
662 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
665 #if defined(CONFIG_ION_ROCKCHIP)
666 struct ion_client *ion_client;
672 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
673 extern struct rk_fb_trsm_ops *rk_fb_trsm_ops_get(int type);
674 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
675 struct rk_lcdc_win *win, int id);
676 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
677 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
678 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
679 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
680 extern u32 rk_fb_get_prmry_screen_pixclock(void);
681 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
682 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
683 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
684 extern bool is_prmry_rk_lcdc_registered(void);
685 extern int rk_fb_prase_timing_dt(struct device_node *np,
686 struct rk_screen *screen);
687 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
689 extern int rk_fb_dpi_open(bool open);
690 extern int rk_fb_dpi_layer_sel(int layer_id);
691 extern int rk_fb_dpi_status(void);
693 extern int rk_fb_switch_screen(struct rk_screen *screen, int enable, int lcdc_id);
694 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
695 extern int rkfb_create_sysfs(struct fb_info *fbi);
696 extern char *get_format_string(enum data_format, char *fmt);
697 extern int support_uboot_display(void);
698 extern int rk_fb_calc_fps(struct rk_screen *screen, u32 pixclock);
699 extern int rk_get_real_fps(int time);
700 extern struct device *rk_fb_get_sysmmu_device_by_compatible(const char *compt);
701 extern void rk_fb_platform_set_sysmmu(struct device *sysmmu,
703 int rk_fb_get_display_policy(void);