1 /* drivers/video/rk_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK30_FB_H
17 #define __ARCH_ARM_MACH_RK30_FB_H
20 #include <linux/platform_device.h>
21 #include <linux/completion.h>
22 #include <linux/spinlock.h>
23 #include <asm/atomic.h>
24 #include <linux/rk_screen.h>
25 #if defined(CONFIG_OF)
26 #include <dt-bindings/rkfb/rk_fb.h>
28 #include "../../drivers/staging/android/sw_sync.h"
29 #include <linux/file.h>
30 #include <linux/kthread.h>
33 #define RK30_MAX_LCDC_SUPPORT 4
34 #define RK30_MAX_LAYER_SUPPORT 4
35 #define RK_MAX_FB_SUPPORT 4
36 #define RK_WIN_MAX_AREA 4
37 #define RK_MAX_BUF_NUM 10
39 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
40 #define FB0_IOCTL_SET_PANEL 0x6002
46 #define FB0_IOCTL_SET_BUF 0x6017
47 #define FB0_IOCTL_COPY_CURBUF 0x6018
48 #define FB0_IOCTL_CLOSE_BUF 0x6019
51 #define RK_FBIOGET_PANEL_SIZE 0x5001
52 #define RK_FBIOSET_YUV_ADDR 0x5002
53 #define RK_FBIOGET_SCREEN_STATE 0X4620
54 #define RK_FBIOGET_16OR32 0X4621
55 #define RK_FBIOGET_IDLEFBUff_16OR32 0X4622
56 #define RK_FBIOSET_COMPOSE_LAYER_COUNTS 0X4623
58 #define RK_FBIOGET_DMABUF_FD 0x5003
59 #define RK_FBIOSET_DMABUF_FD 0x5004
60 #define RK_FB_IOCTL_SET_I2P_ODD_ADDR 0x5005
61 #define RK_FB_IOCTL_SET_I2P_EVEN_ADDR 0x5006
62 #define RK_FBIOSET_OVERLAY_STA 0x5018
63 #define RK_FBIOGET_OVERLAY_STA 0X4619
64 #define RK_FBIOSET_ENABLE 0x5019
65 #define RK_FBIOGET_ENABLE 0x5020
66 #define RK_FBIOSET_CONFIG_DONE 0x4628
67 #define RK_FBIOSET_VSYNC_ENABLE 0x4629
68 #define RK_FBIOPUT_NUM_BUFFERS 0x4625
69 #define RK_FBIOPUT_COLOR_KEY_CFG 0x4626
70 #define RK_FBIOGET_DSP_ADDR 0x4630
71 #define RK_FBIOGET_LIST_STA 0X4631
72 #define RK_FBIOGET_IOMMU_STA 0x4632
73 #define RK_FBIOSET_CLEAR_FB 0x4633
77 #define RK_LF_STATUS_FC 0xef
78 #define RK_LF_STATUS_FR 0xee
79 #define RK_LF_STATUS_NC 0xfe
80 #define RK_LF_MAX_TIMEOUT (1600000UL << 6) //>0.64s
91 * pixel align value for gpu,align as 64 bytes in an odd number of times
93 #define ALIGN_PIXEL_64BYTE_RGB565 32 /* 64/2*/
94 #define ALIGN_PIXEL_64BYTE_RGB8888 16 /* 64/4*/
95 #define ALIGN_N_TIMES(x, align) (((x) % (align) == 0) ? (x) : (((x) + ((align) - 1)) & (~((align) - 1))))
96 #define ALIGN_ODD_TIMES(x, align) (((x) % ((align) * 2) == 0) ? ((x) + (align)) : (x))
97 #define ALIGN_64BYTE_ODD_TIMES(x, align) ALIGN_ODD_TIMES(ALIGN_N_TIMES(x, align), align)
100 //#define USE_ION_MMU 1
101 #if defined(CONFIG_ION_ROCKCHIP)
102 extern struct ion_client *rockchip_ion_client_create(const char * name);
105 extern int rk_fb_poll_prmry_screen_vblank(void);
106 extern u32 rk_fb_get_prmry_screen_ft(void);
107 extern u32 rk_fb_get_prmry_screen_vbt(void);
108 extern u64 rk_fb_get_prmry_screen_framedone_t(void);
109 extern bool rk_fb_poll_wait_frame_complete(void);
111 /********************************************************************
112 ** display output interface supported by rockchip lcdc *
113 ********************************************************************/
115 #define OUT_P888 0 //24bit screen,connect to lcdc D0~D23
116 #define OUT_P666 1 //18bit screen,connect to lcdc D0~D17
119 #define OUT_CCIR656 6
121 #define OUT_S888DUMY 12
122 #define OUT_RGB_AAA 15
123 #define OUT_P16BPP4 24
124 #define OUT_D888_P666 0x21 //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
125 #define OUT_D888_P565 0x22
128 * pixel format definitions,this is copy from android/system/core/include/system/graphics.h
132 HAL_PIXEL_FORMAT_RGBA_8888 = 1,
133 HAL_PIXEL_FORMAT_RGBX_8888 = 2,
134 HAL_PIXEL_FORMAT_RGB_888 = 3,
135 HAL_PIXEL_FORMAT_RGB_565 = 4,
136 HAL_PIXEL_FORMAT_BGRA_8888 = 5,
137 HAL_PIXEL_FORMAT_RGBA_5551 = 6,
138 HAL_PIXEL_FORMAT_RGBA_4444 = 7,
140 /* 0x8 - 0xFF range unavailable */
145 * This range is reserved for pixel formats that are specific to the HAL
146 * implementation. Implementations can use any value in this range to
147 * communicate video pixel formats between their HAL modules. These formats
148 * must not have an alpha channel. Additionally, an EGLimage created from a
149 * gralloc buffer of one of these formats must be supported for use with the
150 * GL_OES_EGL_image_external OpenGL ES extension.
154 * Android YUV format:
156 * This format is exposed outside of the HAL to software decoders and
157 * applications. EGLImageKHR must support it in conjunction with the
158 * OES_EGL_image_external extension.
160 * YV12 is a 4:2:0 YCrCb planar format comprised of a WxH Y plane followed
161 * by (W/2) x (H/2) Cr and Cb planes.
163 * This format assumes
166 * - a horizontal stride multiple of 16 pixels
167 * - a vertical stride equal to the height
169 * y_size = stride * height
170 * c_size = ALIGN(stride/2, 16) * height/2
171 * size = y_size + c_size * 2
173 * cb_offset = y_size + c_size
176 HAL_PIXEL_FORMAT_YV12 = 0x32315659, // YCrCb 4:2:0 Planar
178 /* Legacy formats (deprecated), used by ImageFormat.java */
179 HAL_PIXEL_FORMAT_YCbCr_422_SP = 0x10, // NV16
180 HAL_PIXEL_FORMAT_YCrCb_420_SP = 0x11, // NV21
181 HAL_PIXEL_FORMAT_YCbCr_422_I = 0x14, // YUY2
182 HAL_PIXEL_FORMAT_YCrCb_NV12 = 0x20, // YUY2
183 HAL_PIXEL_FORMAT_YCrCb_NV12_VIDEO = 0x21, // YUY2
185 HAL_PIXEL_FORMAT_YCrCb_NV12_10 = 0x22, // YUV420_1obit
186 HAL_PIXEL_FORMAT_YCbCr_422_SP_10 = 0x23, // YUV422_1obit
187 HAL_PIXEL_FORMAT_YCrCb_420_SP_10 = 0x24, //YUV444_1obit
189 HAL_PIXEL_FORMAT_YCrCb_444 = 0x25, //yuv444
194 //display data format
210 enum fb_win_map_order {
211 FB_DEFAULT_ORDER = 0,
212 FB0_WIN2_FB1_WIN1_FB2_WIN0 = 12,
213 FB0_WIN1_FB1_WIN2_FB2_WIN0 = 21,
214 FB0_WIN2_FB1_WIN0_FB2_WIN1 = 102,
215 FB0_WIN0_FB1_WIN2_FB2_WIN1 = 120,
216 FB0_WIN0_FB1_WIN1_FB2_WIN2 = 210,
217 FB0_WIN1_FB1_WIN0_FB2_WIN2 = 201,
218 FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3 = 3210,
241 struct fb_bitfield red;
242 struct fb_bitfield green;
243 struct fb_bitfield blue;
244 struct fb_bitfield transp;
247 struct rk_fb_frame_time {
248 u64 last_framedone_t;
254 wait_queue_head_t wait;
259 struct mutex irq_lock;
260 struct task_struct *thread;
263 struct color_key_cfg {
264 u32 win0_color_key_cfg;
265 u32 win1_color_key_cfg;
266 u32 win2_color_key_cfg;
280 struct rk_disp_pwr_ctr_list {
281 struct list_head list;
282 struct pwr_ctr pwr_ctr;
285 typedef enum _TRSP_MODE {
295 struct rk_lcdc_post_cfg{
302 struct rk_lcdc_win_area{
304 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
305 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
306 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
308 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
310 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
312 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
314 unsigned long smem_start;
315 unsigned long cbr_start; /*Cbr memory start address*/
316 #if defined(CONFIG_ION_ROCKCHIP)
317 struct ion_handle *ion_hdl;
319 struct dma_buf *dma_buf;
334 bool state; /*on or off*/
335 bool last_state; /*on or off*/
337 enum data_format format;
338 int z_order; /*win sel layer*/
353 u8 yrgb_hor_scl_mode;//h 01:scale up ;10:down
354 u8 yrgb_ver_scl_mode;//v 01:scale up ;10:down
355 u8 yrgb_hsd_mode;//h scale down mode
356 u8 yrgb_vsu_mode;//v scale up mode
357 u8 yrgb_vsd_mode;//v scale down mode
373 struct rk_lcdc_win_area area[RK_WIN_MAX_AREA];
374 struct rk_lcdc_post_cfg post_cfg;
377 struct rk_lcdc_driver;
379 struct rk_fb_trsm_ops {
381 int (*disable)(void);
384 struct rk_lcdc_drv_ops {
385 int (*open) (struct rk_lcdc_driver * dev_drv, int layer_id, bool open);
386 int (*win_direct_en)(struct rk_lcdc_driver *dev_drv, int win_id, int en);
387 int (*init_lcdc) (struct rk_lcdc_driver * dev_drv);
388 int (*ioctl) (struct rk_lcdc_driver * dev_drv, unsigned int cmd,
389 unsigned long arg, int layer_id);
390 int (*suspend) (struct rk_lcdc_driver * dev_drv);
391 int (*resume) (struct rk_lcdc_driver * dev_drv);
392 int (*blank) (struct rk_lcdc_driver * dev_drv, int layer_id,
394 int (*set_par) (struct rk_lcdc_driver * dev_drv, int layer_id);
395 int (*pan_display) (struct rk_lcdc_driver * dev_drv, int layer_id);
396 int (*direct_set_addr)(struct rk_lcdc_driver *drv, int win_id, u32 addr);
397 int (*lcdc_reg_update) (struct rk_lcdc_driver * dev_drv);
398 ssize_t(*get_disp_info) (struct rk_lcdc_driver * dev_drv, char *buf,
400 int (*load_screen) (struct rk_lcdc_driver * dev_drv, bool initscreen);
401 int (*get_win_state) (struct rk_lcdc_driver * dev_drv, int layer_id);
402 int (*ovl_mgr) (struct rk_lcdc_driver * dev_drv, int swap, bool set); //overlay manager
403 int (*fps_mgr) (struct rk_lcdc_driver * dev_drv, int fps, bool set);
404 int (*fb_get_win_id) (struct rk_lcdc_driver * dev_drv, const char *id); //find layer for fb
405 int (*fb_win_remap) (struct rk_lcdc_driver * dev_drv,
406 enum fb_win_map_order order);
407 int (*set_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
408 int (*read_dsp_lut) (struct rk_lcdc_driver * dev_drv, int *lut);
409 int (*lcdc_hdmi_process) (struct rk_lcdc_driver * dev_drv, int mode); //some lcdc need to some process in hdmi mode
410 int (*set_irq_to_cpu)(struct rk_lcdc_driver *dev_drv,int enable);
411 int (*poll_vblank) (struct rk_lcdc_driver * dev_drv);
412 int (*lcdc_rst) (struct rk_lcdc_driver * dev_drv);
413 int (*dpi_open) (struct rk_lcdc_driver * dev_drv, bool open);
414 int (*dpi_win_sel) (struct rk_lcdc_driver * dev_drv, int layer_id);
415 int (*dpi_status) (struct rk_lcdc_driver * dev_drv);
416 int (*get_dsp_addr)(struct rk_lcdc_driver * dev_drv,unsigned int *dsp_addr);
417 int (*set_dsp_cabc) (struct rk_lcdc_driver * dev_drv, int mode);
418 int (*set_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,int sin_hue, int cos_hue);
419 int (*set_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode,int value);
420 int (*get_dsp_bcsh_hue) (struct rk_lcdc_driver *dev_drv,bcsh_hue_mode mode);
421 int (*get_dsp_bcsh_bcs)(struct rk_lcdc_driver *dev_drv,bcsh_bcs_mode mode);
422 int (*open_bcsh)(struct rk_lcdc_driver *dev_drv, bool open);
423 int (*dump_reg) (struct rk_lcdc_driver * dev_drv);
424 int (*mmu_en) (struct rk_lcdc_driver * dev_drv);
425 int (*cfg_done) (struct rk_lcdc_driver * dev_drv);
428 struct rk_fb_area_par {
430 unsigned long phy_addr;
434 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
436 u32 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
438 u32 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
440 u32 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
445 struct rk_fb_win_par {
446 u8 data_format; /*layer data fmt*/
448 u8 z_order; /*win sel layer*/
449 struct rk_fb_area_par area_par[RK_WIN_MAX_AREA];
454 struct rk_fb_win_cfg_data {
456 int rel_fence_fd[RK_MAX_BUF_NUM];
457 struct rk_fb_win_par win_par[RK30_MAX_LAYER_SUPPORT];
458 struct rk_lcdc_post_cfg post_cfg;
463 struct rk_fb_reg_area_data {
464 struct sync_fence *acq_fence;
465 u8 index_buf; /*judge if the buffer is index*/
466 u32 y_offset; /*yuv/rgb offset -->LCDC_WINx_YRGB_MSTx*/
467 u32 c_offset; /*cb cr offset--->LCDC_WINx_CBR_MSTx*/
470 u32 xpos; /*start point in panel --->LCDC_WINx_DSP_ST*/
472 u16 xsize; /* display window width/height -->LCDC_WINx_DSP_INFO*/
474 u16 xact; /*origin display window size -->LCDC_WINx_ACT_INFO*/
476 u16 xvir; /*virtual width/height -->LCDC_WINx_VIR*/
478 unsigned long smem_start;
479 unsigned long cbr_start; /*Cbr memory start address*/
481 struct ion_handle *ion_handle;
483 struct dma_buf *dma_buf;
484 struct dma_buf_attachment *attachment;
485 struct sg_table *sg_table;
490 struct rk_fb_reg_win_data {
491 u8 data_format; /*layer data fmt*/
493 u8 z_order; /*win sel layer*/
494 u32 area_num; /*maybe two region have the same dma buff,*/
495 u32 area_buf_num; /*so area_num maybe not equal to area_buf_num*/
501 struct rk_fb_reg_area_data reg_area_data[RK_WIN_MAX_AREA];
504 struct rk_fb_reg_data {
505 struct list_head list;
509 struct rk_fb_reg_win_data reg_win_data[RK30_MAX_LAYER_SUPPORT];
510 struct rk_lcdc_post_cfg post_cfg;
511 //struct sync_fence *acq_fence[RK_MAX_BUF_NUM];
512 //int fence_wait_begin;
515 struct rk_lcdc_driver {
521 struct rk_lcdc_win *win[RK_MAX_FB_SUPPORT];
523 int num_buf; //the num_of buffer
525 int fb_index_base; //the first fb index of the lcdc device
526 struct rk_screen *screen0; //some platform have only one lcdc,but extend
527 struct rk_screen *screen1; //two display devices for dual display,such as rk2918,rk2928
528 struct rk_screen *cur_screen; //screen0 is primary screen ,like lcd panel,screen1 is extend screen,like hdmi
535 char mmu_dts_name[40];
537 struct rk_fb_reg_area_data reg_area_data;
538 struct mutex fb_win_id_mutex;
540 struct completion frame_done; //sync for pan_display,whe we set a new frame address to lcdc register,we must make sure the frame begain to display
541 spinlock_t cpl_lock; //lock for completion frame done
543 struct rk_fb_vsync vsync_info;
544 struct rk_fb_frame_time frame_time;
545 int wait_fs; //wait for new frame start in kernel
546 struct sw_sync_timeline *timeline;
550 struct list_head update_regs_list;
551 struct mutex update_regs_list_lock;
552 struct kthread_worker update_regs_worker;
553 struct task_struct *update_regs_thread;
554 struct kthread_work update_regs_work;
555 wait_queue_head_t update_regs_wait;
557 struct mutex output_lock;
558 struct rk29fb_info *screen_ctr_info;
559 struct list_head pwrlist_head;
560 struct rk_lcdc_drv_ops *ops;
561 struct rk_fb_trsm_ops *trsm_ops;
562 #ifdef CONFIG_DRM_ROCKCHIP
563 void (*irq_call_back)(struct rk_lcdc_driver *driver);
568 /*disp_mode: dual display mode
569 * NO_DUAL,no dual display,
570 ONE_DUAL,use one lcdc + rk61x for dual display
571 DUAL,use 2 lcdcs for dual display
572 num_fb: the total number of fb
573 num_lcdc: the total number of lcdc
578 struct rk29fb_info *mach_info;
579 struct fb_info *fb[RK_MAX_FB_SUPPORT*2];
582 struct rk_lcdc_driver *lcdc_dev_drv[RK30_MAX_LCDC_SUPPORT];
585 #if defined(CONFIG_ION_ROCKCHIP)
586 struct ion_client * ion_client;
592 extern int rk_fb_trsm_ops_register(struct rk_fb_trsm_ops *ops, int type);
593 extern struct rk_fb_trsm_ops * rk_fb_trsm_ops_get(int type);
594 extern int rk_fb_register(struct rk_lcdc_driver *dev_drv,
595 struct rk_lcdc_win *win, int id);
596 extern int rk_fb_unregister(struct rk_lcdc_driver *dev_drv);
597 extern struct rk_lcdc_driver *rk_get_lcdc_drv(char *name);
598 extern int rk_fb_get_prmry_screen( struct rk_screen *screen);
599 extern int rk_fb_set_prmry_screen(struct rk_screen *screen);
600 extern u32 rk_fb_get_prmry_screen_pixclock(void);
601 extern int rk_disp_pwr_ctr_parse_dt(struct rk_lcdc_driver *dev_drv);
602 extern int rk_disp_pwr_enable(struct rk_lcdc_driver *dev_drv);
603 extern int rk_disp_pwr_disable(struct rk_lcdc_driver *dev_drv);
604 extern bool is_prmry_rk_lcdc_registered(void);
605 extern int rk_fb_prase_timing_dt(struct device_node *np,
606 struct rk_screen *screen);
607 extern int rk_disp_prase_timing_dt(struct rk_lcdc_driver *dev_drv);
609 extern int rk_fb_dpi_open(bool open);
610 extern int rk_fb_dpi_layer_sel(int layer_id);
611 extern int rk_fb_dpi_status(void);
613 extern int rk_fb_switch_screen(struct rk_screen * screen, int enable, int lcdc_id);
614 extern int rk_fb_disp_scale(u8 scale_x, u8 scale_y, u8 lcdc_id);
615 extern int rkfb_create_sysfs(struct fb_info *fbi);
616 extern char *get_format_string(enum data_format, char *fmt);
617 extern int support_uboot_display(void);
618 extern int rk_fb_calc_fps(struct rk_screen * screen, u32 pixclock);
619 extern int rk_get_real_fps(int time);