2 * linux/include/linux/mtd/nand.h
4 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
5 * Steven J. Hill <sjhill@realitydiluted.com>
6 * Thomas Gleixner <tglx@linutronix.de>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 * Contains standard defines and IDs for NAND flash devices
18 #ifndef __LINUX_MTD_NAND_H
19 #define __LINUX_MTD_NAND_H
21 #include <linux/wait.h>
22 #include <linux/spinlock.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/flashchip.h>
25 #include <linux/mtd/bbm.h>
28 struct nand_flash_dev;
31 /* Scan and identify a NAND device */
32 extern int nand_scan(struct mtd_info *mtd, int max_chips);
34 * Separate phases of nand_scan(), allowing board driver to intervene
35 * and override command or ECC setup according to flash type.
37 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
38 struct nand_flash_dev *table);
39 extern int nand_scan_tail(struct mtd_info *mtd);
41 /* Free resources held by the NAND device */
42 extern void nand_release(struct mtd_info *mtd);
44 /* Internal helper for board drivers which need to override command function */
45 extern void nand_wait_ready(struct mtd_info *mtd);
47 /* locks all blocks present in the device */
48 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
50 /* unlocks specified locked blocks */
51 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
53 /* The maximum number of NAND chips in an array */
54 #define NAND_MAX_CHIPS 8
57 * Constants for hardware specific CLE/ALE/NCE function
59 * These are bits which can be or'ed to set/clear multiple
62 /* Select the chip by setting nCE to low */
64 /* Select the command latch by setting CLE to high */
66 /* Select the address latch by setting ALE to high */
69 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
70 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
71 #define NAND_CTRL_CHANGE 0x80
74 * Standard NAND flash commands
76 #define NAND_CMD_READ0 0
77 #define NAND_CMD_READ1 1
78 #define NAND_CMD_RNDOUT 5
79 #define NAND_CMD_PAGEPROG 0x10
80 #define NAND_CMD_READOOB 0x50
81 #define NAND_CMD_ERASE1 0x60
82 #define NAND_CMD_STATUS 0x70
83 #define NAND_CMD_SEQIN 0x80
84 #define NAND_CMD_RNDIN 0x85
85 #define NAND_CMD_READID 0x90
86 #define NAND_CMD_ERASE2 0xd0
87 #define NAND_CMD_PARAM 0xec
88 #define NAND_CMD_GET_FEATURES 0xee
89 #define NAND_CMD_SET_FEATURES 0xef
90 #define NAND_CMD_RESET 0xff
92 #define NAND_CMD_LOCK 0x2a
93 #define NAND_CMD_UNLOCK1 0x23
94 #define NAND_CMD_UNLOCK2 0x24
96 /* Extended commands for large page devices */
97 #define NAND_CMD_READSTART 0x30
98 #define NAND_CMD_RNDOUTSTART 0xE0
99 #define NAND_CMD_CACHEDPROG 0x15
101 #define NAND_CMD_NONE -1
104 #define NAND_STATUS_FAIL 0x01
105 #define NAND_STATUS_FAIL_N1 0x02
106 #define NAND_STATUS_TRUE_READY 0x20
107 #define NAND_STATUS_READY 0x40
108 #define NAND_STATUS_WP 0x80
111 * Constants for ECC_MODES
117 NAND_ECC_HW_SYNDROME,
118 NAND_ECC_HW_OOB_FIRST,
123 * Constants for Hardware ECC
125 /* Reset Hardware ECC for read */
126 #define NAND_ECC_READ 0
127 /* Reset Hardware ECC for write */
128 #define NAND_ECC_WRITE 1
129 /* Enable Hardware ECC before syndrome is read back from flash */
130 #define NAND_ECC_READSYN 2
132 /* Bit mask for flags passed to do_nand_read_ecc */
133 #define NAND_GET_DEVICE 0x80
137 * Option constants for bizarre disfunctionality and real
140 /* Buswidth is 16 bit */
141 #define NAND_BUSWIDTH_16 0x00000002
142 /* Chip has cache program function */
143 #define NAND_CACHEPRG 0x00000008
145 * Chip requires ready check on read (for auto-incremented sequential read).
146 * True only for small page devices; large page devices do not support
149 #define NAND_NEED_READRDY 0x00000100
151 /* Chip does not allow subpage writes */
152 #define NAND_NO_SUBPAGE_WRITE 0x00000200
154 /* Device is one of 'new' xD cards that expose fake nand command set */
155 #define NAND_BROKEN_XD 0x00000400
157 /* Device behaves just like nand, but is readonly */
158 #define NAND_ROM 0x00000800
160 /* Device supports subpage reads */
161 #define NAND_SUBPAGE_READ 0x00001000
163 /* Options valid for Samsung large page devices */
164 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
166 /* Macros to identify the above */
167 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
168 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
170 /* Non chip related options */
171 /* This option skips the bbt scan during initialization. */
172 #define NAND_SKIP_BBTSCAN 0x00010000
174 * This option is defined if the board driver allocates its own buffers
175 * (e.g. because it needs them DMA-coherent).
177 #define NAND_OWN_BUFFERS 0x00020000
178 /* Chip may not exist, so silence any errors in scan */
179 #define NAND_SCAN_SILENT_NODEV 0x00040000
181 * Autodetect nand buswidth with readid/onfi.
182 * This suppose the driver will configure the hardware in 8 bits mode
183 * when calling nand_scan_ident, and update its configuration
184 * before calling nand_scan_tail.
186 #define NAND_BUSWIDTH_AUTO 0x00080000
188 * This option could be defined by controller drivers to protect against
189 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
191 #define NAND_USE_BOUNCE_BUFFER 0x00100000
193 /* Options set by nand scan */
194 /* Nand scan has allocated controller struct */
195 #define NAND_CONTROLLER_ALLOC 0x80000000
197 /* Cell info constants */
198 #define NAND_CI_CHIPNR_MSK 0x03
199 #define NAND_CI_CELLTYPE_MSK 0x0C
200 #define NAND_CI_CELLTYPE_SHIFT 2
206 #define ONFI_FEATURE_16_BIT_BUS (1 << 0)
207 #define ONFI_FEATURE_EXT_PARAM_PAGE (1 << 7)
209 /* ONFI timing mode, used in both asynchronous and synchronous mode */
210 #define ONFI_TIMING_MODE_0 (1 << 0)
211 #define ONFI_TIMING_MODE_1 (1 << 1)
212 #define ONFI_TIMING_MODE_2 (1 << 2)
213 #define ONFI_TIMING_MODE_3 (1 << 3)
214 #define ONFI_TIMING_MODE_4 (1 << 4)
215 #define ONFI_TIMING_MODE_5 (1 << 5)
216 #define ONFI_TIMING_MODE_UNKNOWN (1 << 6)
218 /* ONFI feature address */
219 #define ONFI_FEATURE_ADDR_TIMING_MODE 0x1
221 /* Vendor-specific feature address (Micron) */
222 #define ONFI_FEATURE_ADDR_READ_RETRY 0x89
224 /* ONFI subfeature parameters length */
225 #define ONFI_SUBFEATURE_PARAM_LEN 4
227 /* ONFI optional commands SET/GET FEATURES supported? */
228 #define ONFI_OPT_CMD_SET_GET_FEATURES (1 << 2)
230 struct nand_onfi_params {
231 /* rev info and features block */
232 /* 'O' 'N' 'F' 'I' */
238 __le16 ext_param_page_length; /* since ONFI 2.1 */
239 u8 num_of_param_pages; /* since ONFI 2.1 */
242 /* manufacturer information block */
243 char manufacturer[12];
249 /* memory organization block */
250 __le32 byte_per_page;
251 __le16 spare_bytes_per_page;
252 __le32 data_bytes_per_ppage;
253 __le16 spare_bytes_per_ppage;
254 __le32 pages_per_block;
255 __le32 blocks_per_lun;
260 __le16 block_endurance;
261 u8 guaranteed_good_blocks;
262 __le16 guaranteed_block_endurance;
263 u8 programs_per_page;
270 /* electrical parameter block */
271 u8 io_pin_capacitance_max;
272 __le16 async_timing_mode;
273 __le16 program_cache_timing_mode;
278 __le16 src_sync_timing_mode;
279 __le16 src_ssync_features;
280 __le16 clk_pin_capacitance_typ;
281 __le16 io_pin_capacitance_typ;
282 __le16 input_pin_capacitance_typ;
283 u8 input_pin_capacitance_max;
284 u8 driver_strength_support;
290 __le16 vendor_revision;
296 #define ONFI_CRC_BASE 0x4F4E
298 /* Extended ECC information Block Definition (since ONFI 2.1) */
299 struct onfi_ext_ecc_info {
303 __le16 block_endurance;
307 #define ONFI_SECTION_TYPE_0 0 /* Unused section. */
308 #define ONFI_SECTION_TYPE_1 1 /* for additional sections. */
309 #define ONFI_SECTION_TYPE_2 2 /* for ECC information. */
310 struct onfi_ext_section {
315 #define ONFI_EXT_SECTION_MAX 8
317 /* Extended Parameter Page Definition (since ONFI 2.1) */
318 struct onfi_ext_param_page {
320 u8 sig[4]; /* 'E' 'P' 'P' 'S' */
322 struct onfi_ext_section sections[ONFI_EXT_SECTION_MAX];
325 * The actual size of the Extended Parameter Page is in
326 * @ext_param_page_length of nand_onfi_params{}.
327 * The following are the variable length sections.
328 * So we do not add any fields below. Please see the ONFI spec.
332 struct nand_onfi_vendor_micron {
337 u8 dq_imped_num_settings;
338 u8 dq_imped_feat_addr;
339 u8 rb_pulldown_strength;
340 u8 rb_pulldown_strength_feat_addr;
341 u8 rb_pulldown_strength_num_settings;
344 u8 otp_data_prot_addr;
347 u8 read_retry_options;
352 struct jedec_ecc_info {
356 __le16 block_endurance;
361 #define JEDEC_FEATURE_16_BIT_BUS (1 << 0)
363 struct nand_jedec_params {
364 /* rev info and features block */
365 /* 'J' 'E' 'S' 'D' */
371 u8 num_of_param_pages;
374 /* manufacturer information block */
375 char manufacturer[12];
380 /* memory organization block */
381 __le32 byte_per_page;
382 __le16 spare_bytes_per_page;
384 __le32 pages_per_block;
385 __le32 blocks_per_lun;
389 u8 programs_per_page;
391 u8 multi_plane_op_attr;
394 /* electrical parameter block */
395 __le16 async_sdr_speed_grade;
396 __le16 toggle_ddr_speed_grade;
397 __le16 sync_ddr_speed_grade;
398 u8 async_sdr_features;
399 u8 toggle_ddr_features;
400 u8 sync_ddr_features;
404 __le16 t_r_multi_plane;
406 __le16 io_pin_capacitance_typ;
407 __le16 input_pin_capacitance_typ;
408 __le16 clk_pin_capacitance_typ;
409 u8 driver_strength_support;
413 /* ECC and endurance block */
414 u8 guaranteed_good_blocks;
415 __le16 guaranteed_block_endurance;
416 struct jedec_ecc_info ecc_info[4];
423 __le16 vendor_rev_num;
426 /* CRC for Parameter Page */
431 * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
432 * @lock: protection lock
433 * @active: the mtd device which holds the controller currently
434 * @wq: wait queue to sleep on if a NAND operation is in
435 * progress used instead of the per chip wait queue
436 * when a hw controller is available.
438 struct nand_hw_control {
440 struct nand_chip *active;
441 wait_queue_head_t wq;
445 * struct nand_ecc_ctrl - Control structure for ECC
447 * @steps: number of ECC steps per page
448 * @size: data bytes per ECC step
449 * @bytes: ECC bytes per step
450 * @strength: max number of correctible bits per ECC step
451 * @total: total number of ECC bytes per page
452 * @prepad: padding information for syndrome based ECC generators
453 * @postpad: padding information for syndrome based ECC generators
454 * @layout: ECC layout control struct pointer
455 * @priv: pointer to private ECC control data
456 * @hwctl: function to control hardware ECC generator. Must only
457 * be provided if an hardware ECC is available
458 * @calculate: function for ECC calculation or readback from ECC hardware
459 * @correct: function for ECC correction, matching to ECC generator (sw/hw)
460 * @read_page_raw: function to read a raw page without ECC. This function
461 * should hide the specific layout used by the ECC
462 * controller and always return contiguous in-band and
463 * out-of-band data even if they're not stored
464 * contiguously on the NAND chip (e.g.
465 * NAND_ECC_HW_SYNDROME interleaves in-band and
467 * @write_page_raw: function to write a raw page without ECC. This function
468 * should hide the specific layout used by the ECC
469 * controller and consider the passed data as contiguous
470 * in-band and out-of-band data. ECC controller is
471 * responsible for doing the appropriate transformations
472 * to adapt to its specific layout (e.g.
473 * NAND_ECC_HW_SYNDROME interleaves in-band and
475 * @read_page: function to read a page according to the ECC generator
476 * requirements; returns maximum number of bitflips corrected in
477 * any single ECC step, 0 if bitflips uncorrectable, -EIO hw error
478 * @read_subpage: function to read parts of the page covered by ECC;
479 * returns same as read_page()
480 * @write_subpage: function to write parts of the page covered by ECC.
481 * @write_page: function to write a page according to the ECC generator
483 * @write_oob_raw: function to write chip OOB data without ECC
484 * @read_oob_raw: function to read chip OOB data without ECC
485 * @read_oob: function to read chip OOB data
486 * @write_oob: function to write chip OOB data
488 struct nand_ecc_ctrl {
489 nand_ecc_modes_t mode;
497 struct nand_ecclayout *layout;
499 void (*hwctl)(struct mtd_info *mtd, int mode);
500 int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
502 int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
504 int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
505 uint8_t *buf, int oob_required, int page);
506 int (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
507 const uint8_t *buf, int oob_required, int page);
508 int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
509 uint8_t *buf, int oob_required, int page);
510 int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
511 uint32_t offs, uint32_t len, uint8_t *buf, int page);
512 int (*write_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
513 uint32_t offset, uint32_t data_len,
514 const uint8_t *data_buf, int oob_required, int page);
515 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
516 const uint8_t *buf, int oob_required, int page);
517 int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
519 int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
521 int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page);
522 int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
527 * struct nand_buffers - buffer structure for read/write
528 * @ecccalc: buffer pointer for calculated ECC, size is oobsize.
529 * @ecccode: buffer pointer for ECC read from flash, size is oobsize.
530 * @databuf: buffer pointer for data, size is (page size + oobsize).
532 * Do not change the order of buffers. databuf and oobrbuf must be in
535 struct nand_buffers {
542 * struct nand_chip - NAND Private Flash Chip Data
543 * @IO_ADDR_R: [BOARDSPECIFIC] address to read the 8 I/O lines of the
545 * @IO_ADDR_W: [BOARDSPECIFIC] address to write the 8 I/O lines of the
547 * @flash_node: [BOARDSPECIFIC] device node describing this instance
548 * @read_byte: [REPLACEABLE] read one byte from the chip
549 * @read_word: [REPLACEABLE] read one word from the chip
550 * @write_byte: [REPLACEABLE] write a single byte to the chip on the
552 * @write_buf: [REPLACEABLE] write data from the buffer to the chip
553 * @read_buf: [REPLACEABLE] read data from the chip into the buffer
554 * @select_chip: [REPLACEABLE] select chip nr
555 * @block_bad: [REPLACEABLE] check if a block is bad, using OOB markers
556 * @block_markbad: [REPLACEABLE] mark a block bad
557 * @cmd_ctrl: [BOARDSPECIFIC] hardwarespecific function for controlling
558 * ALE/CLE/nCE. Also used to write command and address
559 * @dev_ready: [BOARDSPECIFIC] hardwarespecific function for accessing
560 * device ready/busy line. If set to NULL no access to
561 * ready/busy is available and the ready/busy information
562 * is read from the chip status register.
563 * @cmdfunc: [REPLACEABLE] hardwarespecific function for writing
564 * commands to the chip.
565 * @waitfunc: [REPLACEABLE] hardwarespecific function for wait on
567 * @setup_read_retry: [FLASHSPECIFIC] flash (vendor) specific function for
568 * setting the read-retry mode. Mostly needed for MLC NAND.
569 * @ecc: [BOARDSPECIFIC] ECC control structure
570 * @buffers: buffer structure for read/write
571 * @hwcontrol: platform-specific hardware control structure
572 * @erase: [REPLACEABLE] erase function
573 * @scan_bbt: [REPLACEABLE] function to scan bad block table
574 * @chip_delay: [BOARDSPECIFIC] chip dependent delay for transferring
575 * data from array to read regs (tR).
576 * @state: [INTERN] the current state of the NAND device
577 * @oob_poi: "poison value buffer," used for laying out OOB data
579 * @page_shift: [INTERN] number of address bits in a page (column
581 * @phys_erase_shift: [INTERN] number of address bits in a physical eraseblock
582 * @bbt_erase_shift: [INTERN] number of address bits in a bbt entry
583 * @chip_shift: [INTERN] number of address bits in one chip
584 * @options: [BOARDSPECIFIC] various chip options. They can partly
585 * be set to inform nand_scan about special functionality.
586 * See the defines for further explanation.
587 * @bbt_options: [INTERN] bad block specific options. All options used
588 * here must come from bbm.h. By default, these options
589 * will be copied to the appropriate nand_bbt_descr's.
590 * @badblockpos: [INTERN] position of the bad block marker in the oob
592 * @badblockbits: [INTERN] minimum number of set bits in a good block's
593 * bad block marker position; i.e., BBM == 11110111b is
594 * not bad when badblockbits == 7
595 * @bits_per_cell: [INTERN] number of bits per cell. i.e., 1 means SLC.
596 * @ecc_strength_ds: [INTERN] ECC correctability from the datasheet.
597 * Minimum amount of bit errors per @ecc_step_ds guaranteed
598 * to be correctable. If unknown, set to zero.
599 * @ecc_step_ds: [INTERN] ECC step required by the @ecc_strength_ds,
600 * also from the datasheet. It is the recommended ECC step
601 * size, if known; if unknown, set to zero.
602 * @onfi_timing_mode_default: [INTERN] default ONFI timing mode. This field is
603 * either deduced from the datasheet if the NAND
604 * chip is not ONFI compliant or set to 0 if it is
605 * (an ONFI chip is always configured in mode 0
606 * after a NAND reset)
607 * @numchips: [INTERN] number of physical chips
608 * @chipsize: [INTERN] the size of one chip for multichip arrays
609 * @pagemask: [INTERN] page number mask = number of (pages / chip) - 1
610 * @pagebuf: [INTERN] holds the pagenumber which is currently in
612 * @pagebuf_bitflips: [INTERN] holds the bitflip count for the page which is
613 * currently in data_buf.
614 * @subpagesize: [INTERN] holds the subpagesize
615 * @onfi_version: [INTERN] holds the chip ONFI version (BCD encoded),
616 * non 0 if ONFI supported.
617 * @jedec_version: [INTERN] holds the chip JEDEC version (BCD encoded),
618 * non 0 if JEDEC supported.
619 * @onfi_params: [INTERN] holds the ONFI page parameter when ONFI is
620 * supported, 0 otherwise.
621 * @jedec_params: [INTERN] holds the JEDEC parameter page when JEDEC is
622 * supported, 0 otherwise.
623 * @read_retries: [INTERN] the number of read retry modes supported
624 * @onfi_set_features: [REPLACEABLE] set the features for ONFI nand
625 * @onfi_get_features: [REPLACEABLE] get the features for ONFI nand
626 * @bbt: [INTERN] bad block table pointer
627 * @bbt_td: [REPLACEABLE] bad block table descriptor for flash
629 * @bbt_md: [REPLACEABLE] bad block table mirror descriptor
630 * @badblock_pattern: [REPLACEABLE] bad block scan pattern used for initial
632 * @controller: [REPLACEABLE] a pointer to a hardware controller
633 * structure which is shared among multiple independent
635 * @priv: [OPTIONAL] pointer to private chip data
636 * @errstat: [OPTIONAL] hardware specific function to perform
637 * additional error status checks (determine if errors are
639 * @write_page: [REPLACEABLE] High-level page write function
643 void __iomem *IO_ADDR_R;
644 void __iomem *IO_ADDR_W;
646 struct device_node *flash_node;
648 uint8_t (*read_byte)(struct mtd_info *mtd);
649 u16 (*read_word)(struct mtd_info *mtd);
650 void (*write_byte)(struct mtd_info *mtd, uint8_t byte);
651 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
652 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
653 void (*select_chip)(struct mtd_info *mtd, int chip);
654 int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
655 int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
656 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
657 int (*dev_ready)(struct mtd_info *mtd);
658 void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
660 int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
661 int (*erase)(struct mtd_info *mtd, int page);
662 int (*scan_bbt)(struct mtd_info *mtd);
663 int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
664 int status, int page);
665 int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
666 uint32_t offset, int data_len, const uint8_t *buf,
667 int oob_required, int page, int cached, int raw);
668 int (*onfi_set_features)(struct mtd_info *mtd, struct nand_chip *chip,
669 int feature_addr, uint8_t *subfeature_para);
670 int (*onfi_get_features)(struct mtd_info *mtd, struct nand_chip *chip,
671 int feature_addr, uint8_t *subfeature_para);
672 int (*setup_read_retry)(struct mtd_info *mtd, int retry_mode);
675 unsigned int options;
676 unsigned int bbt_options;
679 int phys_erase_shift;
686 unsigned int pagebuf_bitflips;
688 uint8_t bits_per_cell;
689 uint16_t ecc_strength_ds;
690 uint16_t ecc_step_ds;
691 int onfi_timing_mode_default;
698 struct nand_onfi_params onfi_params;
699 struct nand_jedec_params jedec_params;
707 struct nand_hw_control *controller;
709 struct nand_ecc_ctrl ecc;
710 struct nand_buffers *buffers;
711 struct nand_hw_control hwcontrol;
714 struct nand_bbt_descr *bbt_td;
715 struct nand_bbt_descr *bbt_md;
717 struct nand_bbt_descr *badblock_pattern;
723 * NAND Flash Manufacturer ID Codes
725 #define NAND_MFR_TOSHIBA 0x98
726 #define NAND_MFR_SAMSUNG 0xec
727 #define NAND_MFR_FUJITSU 0x04
728 #define NAND_MFR_NATIONAL 0x8f
729 #define NAND_MFR_RENESAS 0x07
730 #define NAND_MFR_STMICRO 0x20
731 #define NAND_MFR_HYNIX 0xad
732 #define NAND_MFR_MICRON 0x2c
733 #define NAND_MFR_AMD 0x01
734 #define NAND_MFR_MACRONIX 0xc2
735 #define NAND_MFR_EON 0x92
736 #define NAND_MFR_SANDISK 0x45
737 #define NAND_MFR_INTEL 0x89
738 #define NAND_MFR_ATO 0x9b
740 /* The maximum expected count of bytes in the NAND ID sequence */
741 #define NAND_MAX_ID_LEN 8
744 * A helper for defining older NAND chips where the second ID byte fully
745 * defined the chip, including the geometry (chip size, eraseblock size, page
746 * size). All these chips have 512 bytes NAND page size.
748 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
749 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
750 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
753 * A helper for defining newer chips which report their page size and
754 * eraseblock size via the extended ID bytes.
756 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
757 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
758 * device ID now only represented a particular total chip size (and voltage,
759 * buswidth), and the page size, eraseblock size, and OOB size could vary while
760 * using the same device ID.
762 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
763 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
766 #define NAND_ECC_INFO(_strength, _step) \
767 { .strength_ds = (_strength), .step_ds = (_step) }
768 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
769 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
772 * struct nand_flash_dev - NAND Flash Device ID Structure
773 * @name: a human-readable name of the NAND chip
774 * @dev_id: the device ID (the second byte of the full chip ID array)
775 * @mfr_id: manufecturer ID part of the full chip ID array (refers the same
776 * memory address as @id[0])
777 * @dev_id: device ID part of the full chip ID array (refers the same memory
779 * @id: full device ID array
780 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
781 * well as the eraseblock size) is determined from the extended NAND
783 * @chipsize: total chip size in MiB
784 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
785 * @options: stores various chip bit options
786 * @id_len: The valid length of the @id.
788 * @ecc: ECC correctability and step information from the datasheet.
789 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
790 * @ecc_strength_ds in nand_chip{}.
791 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
792 * @ecc_step_ds in nand_chip{}, also from the datasheet.
793 * For example, the "4bit ECC for each 512Byte" can be set with
794 * NAND_ECC_INFO(4, 512).
795 * @onfi_timing_mode_default: the default ONFI timing mode entered after a NAND
796 * reset. Should be deduced from timings described
800 struct nand_flash_dev {
807 uint8_t id[NAND_MAX_ID_LEN];
809 unsigned int pagesize;
810 unsigned int chipsize;
811 unsigned int erasesize;
812 unsigned int options;
816 uint16_t strength_ds;
819 int onfi_timing_mode_default;
823 * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
824 * @name: Manufacturer name
825 * @id: manufacturer ID code of device.
827 struct nand_manufacturers {
832 extern struct nand_flash_dev nand_flash_ids[];
833 extern struct nand_manufacturers nand_manuf_ids[];
835 extern int nand_default_bbt(struct mtd_info *mtd);
836 extern int nand_markbad_bbt(struct mtd_info *mtd, loff_t offs);
837 extern int nand_isreserved_bbt(struct mtd_info *mtd, loff_t offs);
838 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
839 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
841 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
842 size_t *retlen, uint8_t *buf);
845 * struct platform_nand_chip - chip level device structure
846 * @nr_chips: max. number of chips to scan for
847 * @chip_offset: chip number offset
848 * @nr_partitions: number of partitions pointed to by partitions (or zero)
849 * @partitions: mtd partition list
850 * @chip_delay: R/B delay value in us
851 * @options: Option flags, e.g. 16bit buswidth
852 * @bbt_options: BBT option flags, e.g. NAND_BBT_USE_FLASH
853 * @ecclayout: ECC layout info structure
854 * @part_probe_types: NULL-terminated array of probe types
856 struct platform_nand_chip {
860 struct mtd_partition *partitions;
861 struct nand_ecclayout *ecclayout;
863 unsigned int options;
864 unsigned int bbt_options;
865 const char **part_probe_types;
869 struct platform_device;
872 * struct platform_nand_ctrl - controller level device structure
873 * @probe: platform specific function to probe/setup hardware
874 * @remove: platform specific function to remove/teardown hardware
875 * @hwcontrol: platform specific hardware control structure
876 * @dev_ready: platform specific function to read ready/busy pin
877 * @select_chip: platform specific chip select function
878 * @cmd_ctrl: platform specific function for controlling
879 * ALE/CLE/nCE. Also used to write command and address
880 * @write_buf: platform specific function for write buffer
881 * @read_buf: platform specific function for read buffer
882 * @read_byte: platform specific function to read one byte from chip
883 * @priv: private data to transport driver specific settings
885 * All fields are optional and depend on the hardware driver requirements
887 struct platform_nand_ctrl {
888 int (*probe)(struct platform_device *pdev);
889 void (*remove)(struct platform_device *pdev);
890 void (*hwcontrol)(struct mtd_info *mtd, int cmd);
891 int (*dev_ready)(struct mtd_info *mtd);
892 void (*select_chip)(struct mtd_info *mtd, int chip);
893 void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
894 void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
895 void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
896 unsigned char (*read_byte)(struct mtd_info *mtd);
901 * struct platform_nand_data - container structure for platform-specific data
902 * @chip: chip level chip structure
903 * @ctrl: controller level device structure
905 struct platform_nand_data {
906 struct platform_nand_chip chip;
907 struct platform_nand_ctrl ctrl;
910 /* Some helpers to access the data structures */
912 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
914 struct nand_chip *chip = mtd->priv;
919 /* return the supported features. */
920 static inline int onfi_feature(struct nand_chip *chip)
922 return chip->onfi_version ? le16_to_cpu(chip->onfi_params.features) : 0;
925 /* return the supported asynchronous timing mode. */
926 static inline int onfi_get_async_timing_mode(struct nand_chip *chip)
928 if (!chip->onfi_version)
929 return ONFI_TIMING_MODE_UNKNOWN;
930 return le16_to_cpu(chip->onfi_params.async_timing_mode);
933 /* return the supported synchronous timing mode. */
934 static inline int onfi_get_sync_timing_mode(struct nand_chip *chip)
936 if (!chip->onfi_version)
937 return ONFI_TIMING_MODE_UNKNOWN;
938 return le16_to_cpu(chip->onfi_params.src_sync_timing_mode);
942 * Check if it is a SLC nand.
943 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
944 * We do not distinguish the MLC and TLC now.
946 static inline bool nand_is_slc(struct nand_chip *chip)
948 return chip->bits_per_cell == 1;
952 * Check if the opcode's address should be sent only on the lower 8 bits
953 * @command: opcode to check
955 static inline int nand_opcode_8bits(unsigned int command)
958 case NAND_CMD_READID:
960 case NAND_CMD_GET_FEATURES:
961 case NAND_CMD_SET_FEATURES:
969 /* return the supported JEDEC features. */
970 static inline int jedec_feature(struct nand_chip *chip)
972 return chip->jedec_version ? le16_to_cpu(chip->jedec_params.features)
977 * struct nand_sdr_timings - SDR NAND chip timings
979 * This struct defines the timing requirements of a SDR NAND chip.
980 * These informations can be found in every NAND datasheets and the timings
981 * meaning are described in the ONFI specifications:
982 * www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf (chapter 4.15 Timing
985 * All these timings are expressed in picoseconds.
988 struct nand_sdr_timings {
1025 /* get timing characteristics from ONFI timing mode. */
1026 const struct nand_sdr_timings *onfi_async_timing_mode_to_sdr_timings(int mode);
1028 int nand_check_erased_ecc_chunk(void *data, int datalen,
1029 void *ecc, int ecclen,
1030 void *extraoob, int extraooblen,
1032 #endif /* __LINUX_MTD_NAND_H */