2 * Synopsys DesignWare Multimedia Card Interface driver
3 * (Based on NXP driver for lpc 31xx)
5 * Copyright (C) 2009 NXP Semiconductors
6 * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #ifndef LINUX_MMC_DW_MMC_H
15 #define LINUX_MMC_DW_MMC_H
17 #include <linux/scatterlist.h>
18 #include <linux/mmc/core.h>
19 #include <linux/dmaengine.h>
20 #include <linux/timer.h>
22 #define MAX_MCI_SLOTS 2
34 EVENT_CMD_COMPLETE = 0,
40 struct dw_mci_dma_slave {
42 enum dma_transfer_direction direction;
49 * struct dw_mci - MMC controller state shared between all slots
50 * @lock: Spinlock protecting the queue and associated data.
51 * @regs: Pointer to MMIO registers.
52 * @sg: Scatterlist entry currently being processed by PIO code, if any.
53 * @sg_miter: PIO mapping scatterlist iterator.
54 * @cur_slot: The slot which is currently using the controller.
55 * @mrq: The request currently being processed on @cur_slot,
56 * or NULL if the controller is idle.
57 * @cmd: The command currently being sent to the card, or NULL.
58 * @data: The data currently being transferred, or NULL if no data
59 * transfer is in progress.
60 * @use_dma: Whether DMA channel is initialized or not.
61 * @using_dma: Whether DMA is in use for the current transfer.
62 * @sg_dma: Bus address of DMA buffer.
63 * @sg_cpu: Virtual address of DMA buffer.
64 * @dma_ops: Pointer to platform-specific DMA callbacks.
65 * @cmd_status: Snapshot of SR taken upon completion of the current
66 * command. Only valid when EVENT_CMD_COMPLETE is pending.
67 * @data_status: Snapshot of SR taken upon completion of the current
68 * data transfer. Only valid when EVENT_DATA_COMPLETE or
69 * EVENT_DATA_ERROR is pending.
70 * @stop_cmdr: Value to be loaded into CMDR when the stop command is
72 * @dir_status: Direction of current transfer.
73 * @tasklet: Tasklet running the request state machine.
74 * @card_tasklet: Tasklet handling card detect.
75 * @pending_events: Bitmask of events flagged by the interrupt handler
76 * to be processed by the tasklet.
77 * @completed_events: Bitmask of events which the state machine has
79 * @state: Tasklet state.
80 * @queue: List of slots waiting for access to the controller.
81 * @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
82 * rate and timeout calculations.
83 * @current_speed: Configured rate of the controller.
84 * @num_slots: Number of slots available.
85 * @verid: Denote Version ID.
86 * @data_offset: Set the offset of DATA register according to VERID.
87 * @dev: Device associated with the MMC controller.
88 * @pdata: Platform data associated with the MMC controller.
89 * @drv_data: Driver specific data for identified variant of the controller
90 * @priv: Implementation defined private data.
91 * @biu_clk: Pointer to bus interface unit clock instance.
92 * @ciu_clk: Pointer to card interface unit clock instance.
93 * @slot: Slots sharing this MMC controller.
94 * @fifo_depth: depth of FIFO.
95 * @data_shift: log2 of FIFO item size.
96 * @part_buf_start: Start index in part_buf.
97 * @part_buf_count: Bytes of partial data in part_buf.
98 * @part_buf: Simple buffer for partial fifo reads/writes.
99 * @push_data: Pointer to FIFO push function.
100 * @pull_data: Pointer to FIFO pull function.
101 * @quirks: Set of quirks that apply to specific versions of the IP.
102 * @irq_flags: The flags to be passed to request_irq.
103 * @irq: The irq value to be passed to request_irq.
108 * @lock is a softirq-safe spinlock protecting @queue as well as
109 * @cur_slot, @mrq and @state. These must always be updated
110 * at the same time while holding @lock.
112 * The @mrq field of struct dw_mci_slot is also protected by @lock,
113 * and must always be written at the same time as the slot is added to
116 * @pending_events and @completed_events are accessed using atomic bit
117 * operations, so they don't need any locking.
119 * None of the fields touched by the interrupt handler need any
120 * locking. However, ordering is important: Before EVENT_DATA_ERROR or
121 * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
122 * interrupts must be disabled and @data_status updated with a
123 * snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
124 * CMDRDY interrupt must be disabled and @cmd_status updated with a
125 * snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
126 * bytes_xfered field of @data must be written. This is ensured by
134 struct scatterlist *sg;
135 struct sg_mapping_iter sg_miter;
137 struct dw_mci_slot *cur_slot;
138 struct mmc_request *mrq;
139 struct mmc_command *cmd;
140 struct mmc_data *data;
141 struct mmc_command stop_abort;
142 unsigned int prev_blksz;
143 unsigned char timing;
144 struct workqueue_struct *card_workqueue;
146 /* DMA interface members*/
152 const struct dw_mci_dma_ops *dma_ops;
153 #ifdef CONFIG_MMC_DW_IDMAC
154 unsigned int ring_size;
155 struct dw_mci_dma_slave *dms;
158 struct dw_mci_dma_data *dma_data;
164 struct tasklet_struct tasklet;
165 struct work_struct card_work;
166 unsigned long pending_events;
167 unsigned long completed_events;
168 enum dw_mci_state state;
169 struct list_head queue;
180 struct dw_mci_board *pdata;
181 const struct dw_mci_drv_data *drv_data;
183 struct clk *hclk_mmc;
185 struct dw_mci_slot *slot[MAX_MCI_SLOTS];
186 struct mmc_host *mmc;
187 struct mmc_command *pre_cmd;
188 /* Fix the hold_reg value */
189 unsigned int hold_reg_flag;
190 /* FIFO push and pull */
200 void (*push_data)(struct dw_mci *host, void *buf, int cnt);
201 void (*pull_data)(struct dw_mci *host, void *buf, int cnt);
203 /* Workaround flags */
206 u32 svi_flags; /* Switch voltage interrupt flags */
207 struct regulator *vmmc; /* Power regulator */
208 unsigned long irq_flags; /* IRQ flags */
210 u32 cmd_rto; /* Cmd response timeout hold times */
211 struct pinctrl *pinctrl;
214 struct pinctrl_state *pins_default; /* Function port */
215 struct pinctrl_state *pins_idle; /* Gpio port */
216 struct pinctrl_state *pins_udbg; /* uart_dbg port */
222 /* DMA ops for Internal/External DMAC interface */
223 struct dw_mci_dma_ops {
225 int (*init)(struct dw_mci *host);
226 void (*start)(struct dw_mci *host, unsigned int sg_len);
227 void (*complete)(void *host);
228 void (*stop)(struct dw_mci *host);
229 void (*cleanup)(struct dw_mci *host);
230 void (*exit)(struct dw_mci *host);
233 /* IP Quirks/flags. */
234 /* DTO fix for command transmission with IDMAC configured */
235 #define DW_MCI_QUIRK_IDMAC_DTO BIT(0)
236 /* delay needed between retries on some 2.11a implementations */
237 #define DW_MCI_QUIRK_RETRY_DELAY BIT(1)
238 /* High Speed Capable - Supports HS cards (up to 50MHz) */
239 #define DW_MCI_QUIRK_HIGHSPEED BIT(2)
240 /* Unreliable card detection */
241 #define DW_MCI_QUIRK_BROKEN_CARD_DETECTION BIT(3)
243 /* Slot level quirks */
244 /* This slot has no write protect */
245 #define DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT BIT(0)
249 struct block_settings {
250 unsigned short max_segs; /* see blk_queue_max_segments */
251 unsigned int max_blk_size; /* maximum size of one mmc block */
252 unsigned int max_blk_count; /* maximum number of blocks in one req*/
253 unsigned int max_req_size; /* maximum number of bytes in one req*/
254 unsigned int max_seg_size; /* see blk_queue_max_segment_size */
257 /* Board platform data */
258 struct dw_mci_board {
261 u32 quirks; /* Workaround / Quirk flags */
262 unsigned int bus_hz; /* Clock speed at the cclk_in pad */
264 u32 caps; /* Capabilities */
265 u32 caps2; /* More capabilities */
266 u32 pm_caps; /* PM capabilities */
267 u32 cardtype_restrict; /*restrict the SDMMC controller to support card type;1--SD card; 2--sdio; 4--eMMC */
269 * Override fifo depth. If 0, autodetect it from the FIFOTH register,
270 * but note that this may not be reliable after a bootloader has used
273 unsigned int fifo_depth;
275 /* delay in mS before detecting cards after interrupt */
278 int (*init)(u32 slot_id, irq_handler_t , void *);
279 int (*get_ro)(u32 slot_id);
280 int (*get_cd)(u32 slot_id);
281 int (*get_ocr)(u32 slot_id);
282 int (*get_bus_wd)(u32 slot_id);
284 * Enable power to selected slot and set voltage to desired level.
285 * Voltage levels are specified using MMC_VDD_xxx defines defined
286 * in linux/mmc/host.h file.
288 void (*setpower)(u32 slot_id, u32 volt);
289 void (*exit)(u32 slot_id);
290 void (*select_slot)(u32 slot_id);
292 struct dw_mci_dma_ops *dma_ops;
293 struct dma_pdata *data;
294 struct block_settings *blk_settings;
296 #define grf_writel(v, offset) do \
297 { writel_relaxed(v, RK_GRF_VIRT + offset); dsb(sy); } \
300 #endif /* LINUX_MMC_DW_MMC_H */