2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/mlx5/device.h>
37 #include <linux/mlx5/driver.h>
39 #define MLX5_INVALID_LKEY 0x100
40 #define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
41 #define MLX5_DIF_SIZE 8
42 #define MLX5_STRIDE_BLOCK_OP 0x400
45 MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
46 MLX5_QP_OPTPAR_RRE = 1 << 1,
47 MLX5_QP_OPTPAR_RAE = 1 << 2,
48 MLX5_QP_OPTPAR_RWE = 1 << 3,
49 MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
50 MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
51 MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
52 MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
53 MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
54 MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
55 MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
56 MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
57 MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
58 MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
59 MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
60 MLX5_QP_OPTPAR_SRQN = 1 << 18,
61 MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
62 MLX5_QP_OPTPAR_DC_HS = 1 << 20,
63 MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
67 MLX5_QP_STATE_RST = 0,
68 MLX5_QP_STATE_INIT = 1,
69 MLX5_QP_STATE_RTR = 2,
70 MLX5_QP_STATE_RTS = 3,
71 MLX5_QP_STATE_SQER = 4,
72 MLX5_QP_STATE_SQD = 5,
73 MLX5_QP_STATE_ERR = 6,
74 MLX5_QP_STATE_SQ_DRAINING = 7,
75 MLX5_QP_STATE_SUSPENDED = 9,
89 MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
90 MLX5_QP_ST_RAW_IPV6 = 0xa,
91 MLX5_QP_ST_SNIFFER = 0xb,
92 MLX5_QP_ST_SYNC_UMR = 0xe,
93 MLX5_QP_ST_PTP_1588 = 0xd,
94 MLX5_QP_ST_REG_UMR = 0xc,
99 MLX5_QP_PM_MIGRATED = 0x3,
100 MLX5_QP_PM_ARMED = 0x0,
101 MLX5_QP_PM_REARM = 0x1
105 MLX5_NON_ZERO_RQ = 0 << 24,
106 MLX5_SRQ_RQ = 1 << 24,
107 MLX5_CRQ_RQ = 2 << 24,
108 MLX5_ZERO_LEN_RQ = 3 << 24
113 MLX5_QP_BIT_SRE = 1 << 15,
114 MLX5_QP_BIT_SWE = 1 << 14,
115 MLX5_QP_BIT_SAE = 1 << 13,
117 MLX5_QP_BIT_RRE = 1 << 15,
118 MLX5_QP_BIT_RWE = 1 << 14,
119 MLX5_QP_BIT_RAE = 1 << 13,
120 MLX5_QP_BIT_RIC = 1 << 4,
124 MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
125 MLX5_WQE_CTRL_SOLICITED = 1 << 1,
129 MLX5_SEND_WQE_BB = 64,
133 MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
134 MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
135 MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
136 MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
137 MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
141 MLX5_FENCE_MODE_NONE = 0 << 5,
142 MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
143 MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
144 MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
148 MLX5_QP_LAT_SENSITIVE = 1 << 28,
149 MLX5_QP_BLOCK_MCAST = 1 << 30,
150 MLX5_QP_ENABLE_SIG = 1 << 31,
159 MLX5_FLAGS_INLINE = 1<<7,
160 MLX5_FLAGS_CHECK_FREE = 1<<5,
163 struct mlx5_wqe_fmr_seg {
174 struct mlx5_wqe_ctrl_seg {
175 __be32 opmod_idx_opcode;
183 struct mlx5_wqe_xrc_seg {
188 struct mlx5_wqe_masked_atomic_seg {
191 __be64 swap_add_mask;
214 struct mlx5_wqe_datagram_seg {
218 struct mlx5_wqe_raddr_seg {
224 struct mlx5_wqe_atomic_seg {
229 struct mlx5_wqe_data_seg {
235 struct mlx5_wqe_umr_ctrl_seg {
238 __be16 klm_octowords;
239 __be16 bsf_octowords;
244 struct mlx5_seg_set_psv {
248 __be32 transient_sig;
252 struct mlx5_seg_get_psv {
260 struct mlx5_seg_check_psv {
262 __be16 err_coalescing_op;
266 __be16 xport_err_mask;
274 struct mlx5_rwqe_sig {
280 struct mlx5_wqe_signature_seg {
286 struct mlx5_wqe_inline_seg {
291 struct mlx5_bsf_basic {
303 __be32 raw_data_size;
307 struct mlx5_bsf_ext {
308 __be32 t_init_gen_pro_size;
309 __be32 rsvd_epi_size;
313 struct mlx5_bsf_inl {
316 __be64 w_block_format;
319 __be64 m_block_format;
329 struct mlx5_stride_block_entry {
336 struct mlx5_stride_block_ctrl_seg {
337 __be32 bcount_per_cycle;
344 struct mlx5_core_qp {
345 void (*event) (struct mlx5_core_qp *, int);
348 struct completion free;
349 struct mlx5_rsc_debug *dbg;
353 struct mlx5_qp_path {
365 __be32 tclass_flowlabel;
373 struct mlx5_qp_context {
379 __be32 qp_counter_set_usr_page;
381 __be32 log_pg_sz_remote_qpn;
382 struct mlx5_qp_path pri_path;
383 struct mlx5_qp_path alt_path;
386 __be32 next_send_psn;
389 __be32 last_acked_psn;
392 __be32 rnr_nextrecvpsn;
399 __be16 hw_sq_wqe_counter;
400 __be16 sw_sq_wqe_counter;
401 __be16 hw_rcyclic_byte_counter;
402 __be16 hw_rq_counter;
403 __be16 sw_rcyclic_byte_counter;
404 __be16 sw_rq_counter;
409 __be64 dc_access_key;
413 struct mlx5_create_qp_mbox_in {
414 struct mlx5_inbox_hdr hdr;
417 __be32 opt_param_mask;
419 struct mlx5_qp_context ctx;
424 struct mlx5_create_qp_mbox_out {
425 struct mlx5_outbox_hdr hdr;
430 struct mlx5_destroy_qp_mbox_in {
431 struct mlx5_inbox_hdr hdr;
436 struct mlx5_destroy_qp_mbox_out {
437 struct mlx5_outbox_hdr hdr;
441 struct mlx5_modify_qp_mbox_in {
442 struct mlx5_inbox_hdr hdr;
447 struct mlx5_qp_context ctx;
450 struct mlx5_modify_qp_mbox_out {
451 struct mlx5_outbox_hdr hdr;
455 struct mlx5_query_qp_mbox_in {
456 struct mlx5_inbox_hdr hdr;
461 struct mlx5_query_qp_mbox_out {
462 struct mlx5_outbox_hdr hdr;
466 struct mlx5_qp_context ctx;
471 struct mlx5_conf_sqp_mbox_in {
472 struct mlx5_inbox_hdr hdr;
478 struct mlx5_conf_sqp_mbox_out {
479 struct mlx5_outbox_hdr hdr;
483 struct mlx5_alloc_xrcd_mbox_in {
484 struct mlx5_inbox_hdr hdr;
488 struct mlx5_alloc_xrcd_mbox_out {
489 struct mlx5_outbox_hdr hdr;
494 struct mlx5_dealloc_xrcd_mbox_in {
495 struct mlx5_inbox_hdr hdr;
500 struct mlx5_dealloc_xrcd_mbox_out {
501 struct mlx5_outbox_hdr hdr;
505 static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
507 return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
510 static inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
512 return radix_tree_lookup(&dev->priv.mr_table.tree, key);
515 int mlx5_core_create_qp(struct mlx5_core_dev *dev,
516 struct mlx5_core_qp *qp,
517 struct mlx5_create_qp_mbox_in *in,
519 int mlx5_core_qp_modify(struct mlx5_core_dev *dev, enum mlx5_qp_state cur_state,
520 enum mlx5_qp_state new_state,
521 struct mlx5_modify_qp_mbox_in *in, int sqd_event,
522 struct mlx5_core_qp *qp);
523 int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
524 struct mlx5_core_qp *qp);
525 int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
526 struct mlx5_query_qp_mbox_out *out, int outlen);
528 int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
529 int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
530 void mlx5_init_qp_table(struct mlx5_core_dev *dev);
531 void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
532 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
533 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
535 static inline const char *mlx5_qp_type_str(int type)
538 case MLX5_QP_ST_RC: return "RC";
539 case MLX5_QP_ST_UC: return "C";
540 case MLX5_QP_ST_UD: return "UD";
541 case MLX5_QP_ST_XRC: return "XRC";
542 case MLX5_QP_ST_MLX: return "MLX";
543 case MLX5_QP_ST_QP0: return "QP0";
544 case MLX5_QP_ST_QP1: return "QP1";
545 case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
546 case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
547 case MLX5_QP_ST_SNIFFER: return "SNIFFER";
548 case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
549 case MLX5_QP_ST_PTP_1588: return "PTP_1588";
550 case MLX5_QP_ST_REG_UMR: return "REG_UMR";
551 default: return "Invalid transport type";
555 static inline const char *mlx5_qp_state_str(int state)
558 case MLX5_QP_STATE_RST:
560 case MLX5_QP_STATE_INIT:
562 case MLX5_QP_STATE_RTR:
564 case MLX5_QP_STATE_RTS:
566 case MLX5_QP_STATE_SQER:
568 case MLX5_QP_STATE_SQD:
570 case MLX5_QP_STATE_ERR:
572 case MLX5_QP_STATE_SQ_DRAINING:
573 return "SQ_DRAINING";
574 case MLX5_QP_STATE_SUSPENDED:
576 default: return "Invalid QP state";
580 #endif /* MLX5_QP_H */