2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
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8 * OpenIB.org BSD license below:
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11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/pci.h>
37 #include <linux/completion.h>
38 #include <linux/radix-tree.h>
40 #include <asm/atomic.h>
43 MLX4_FLAG_MSI_X = 1 << 0,
44 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
52 MLX4_BOARD_ID_LEN = 64
56 MLX4_DEV_CAP_FLAG_RC = 1 << 0,
57 MLX4_DEV_CAP_FLAG_UC = 1 << 1,
58 MLX4_DEV_CAP_FLAG_UD = 1 << 2,
59 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
60 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
61 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
62 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
63 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12,
64 MLX4_DEV_CAP_FLAG_BLH = 1 << 15,
65 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
66 MLX4_DEV_CAP_FLAG_APM = 1 << 17,
67 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
68 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
69 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
70 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
74 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
75 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
76 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
77 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
78 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
82 MLX4_EVENT_TYPE_COMP = 0x00,
83 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
84 MLX4_EVENT_TYPE_COMM_EST = 0x02,
85 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
86 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
87 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
88 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
89 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
90 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
91 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
92 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
93 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
94 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
95 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
96 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
97 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
98 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
99 MLX4_EVENT_TYPE_CMD = 0x0a
103 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
104 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
108 MLX4_PERM_LOCAL_READ = 1 << 10,
109 MLX4_PERM_LOCAL_WRITE = 1 << 11,
110 MLX4_PERM_REMOTE_READ = 1 << 12,
111 MLX4_PERM_REMOTE_WRITE = 1 << 13,
112 MLX4_PERM_ATOMIC = 1 << 14
116 MLX4_OPCODE_NOP = 0x00,
117 MLX4_OPCODE_SEND_INVAL = 0x01,
118 MLX4_OPCODE_RDMA_WRITE = 0x08,
119 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
120 MLX4_OPCODE_SEND = 0x0a,
121 MLX4_OPCODE_SEND_IMM = 0x0b,
122 MLX4_OPCODE_LSO = 0x0e,
123 MLX4_OPCODE_RDMA_READ = 0x10,
124 MLX4_OPCODE_ATOMIC_CS = 0x11,
125 MLX4_OPCODE_ATOMIC_FA = 0x12,
126 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
127 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
128 MLX4_OPCODE_BIND_MW = 0x18,
129 MLX4_OPCODE_FMR = 0x19,
130 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
131 MLX4_OPCODE_CONFIG_CMD = 0x1f,
133 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
134 MLX4_RECV_OPCODE_SEND = 0x01,
135 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
136 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
138 MLX4_CQE_OPCODE_ERROR = 0x1e,
139 MLX4_CQE_OPCODE_RESIZE = 0x16,
143 MLX4_STAT_RATE_OFFSET = 5
147 MLX4_MTT_FLAG_PRESENT = 1
150 enum mlx4_qp_region {
151 MLX4_QP_REGION_FW = 0,
152 MLX4_QP_REGION_ETH_ADDR,
153 MLX4_QP_REGION_FC_ADDR,
154 MLX4_QP_REGION_FC_EXCH,
158 enum mlx4_port_type {
159 MLX4_PORT_TYPE_IB = 1,
160 MLX4_PORT_TYPE_ETH = 2,
161 MLX4_PORT_TYPE_AUTO = 3
164 enum mlx4_special_vlan_idx {
165 MLX4_NO_VLAN_IDX = 0,
171 MLX4_NUM_FEXCH = 64 * 1024,
174 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
176 return (major << 32) | (minor << 16) | subminor;
182 int vl_cap[MLX4_MAX_PORTS + 1];
183 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
184 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
185 u64 def_mac[MLX4_MAX_PORTS + 1];
186 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
187 int gid_table_len[MLX4_MAX_PORTS + 1];
188 int pkey_table_len[MLX4_MAX_PORTS + 1];
189 int trans_type[MLX4_MAX_PORTS + 1];
190 int vendor_oui[MLX4_MAX_PORTS + 1];
191 int wavelength[MLX4_MAX_PORTS + 1];
192 u64 trans_code[MLX4_MAX_PORTS + 1];
193 int local_ca_ack_delay;
196 int bf_regs_per_page;
203 int max_qp_init_rdma;
204 int max_qp_dest_rdma;
215 int num_comp_vectors;
219 int fmr_reserved_mtts;
235 u16 stat_rate_support;
237 int loopback_support;
238 u8 port_width_cap[MLX4_MAX_PORTS + 1];
240 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
242 int reserved_qps_base[MLX4_NUM_QP_REGION];
246 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
247 u8 supported_type[MLX4_MAX_PORTS + 1];
249 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
252 struct mlx4_buf_list {
258 struct mlx4_buf_list direct;
259 struct mlx4_buf_list *page_list;
272 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
275 struct mlx4_db_pgdir {
276 struct list_head list;
277 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
278 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
279 unsigned long *bits[2];
284 struct mlx4_ib_user_db_page;
289 struct mlx4_db_pgdir *pgdir;
290 struct mlx4_ib_user_db_page *user_page;
297 struct mlx4_hwq_resources {
315 struct mlx4_mpt_entry *mpt;
317 dma_addr_t dma_handle;
330 void (*comp) (struct mlx4_cq *);
331 void (*event) (struct mlx4_cq *, enum mlx4_event);
333 struct mlx4_uar *uar;
345 struct completion free;
349 void (*event) (struct mlx4_qp *, enum mlx4_event);
354 struct completion free;
358 void (*event) (struct mlx4_srq *, enum mlx4_event);
366 struct completion free;
378 __be32 sl_tclass_flowlabel;
383 struct pci_dev *pdev;
385 struct mlx4_caps caps;
386 struct radix_tree_root qp_table_tree;
388 char board_id[MLX4_BOARD_ID_LEN];
391 struct mlx4_init_port_param {
405 #define mlx4_foreach_port(port, dev, type) \
406 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
407 if (((type) == MLX4_PORT_TYPE_IB ? (dev)->caps.port_mask : \
408 ~(dev)->caps.port_mask) & 1 << ((port) - 1))
410 int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
411 struct mlx4_buf *buf);
412 void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
413 static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
415 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
416 return buf->direct.buf + offset;
418 return buf->page_list[offset >> PAGE_SHIFT].buf +
419 (offset & (PAGE_SIZE - 1));
422 int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
423 void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
425 int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
426 void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
428 int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
429 struct mlx4_mtt *mtt);
430 void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
431 u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
433 int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
434 int npages, int page_shift, struct mlx4_mr *mr);
435 void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
436 int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
437 int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
438 int start_index, int npages, u64 *page_list);
439 int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
440 struct mlx4_buf *buf);
442 int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
443 void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
445 int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
446 int size, int max_direct);
447 void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
450 int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
451 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
452 unsigned vector, int collapsed);
453 void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
455 int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
456 void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
458 int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
459 void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
461 int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
462 u64 db_rec, struct mlx4_srq *srq);
463 void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
464 int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
465 int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
467 int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
468 int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
470 int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
471 int block_mcast_loopback);
472 int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);
474 int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
475 void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
477 int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
478 void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
480 int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
481 int npages, u64 iova, u32 *lkey, u32 *rkey);
482 int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
483 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
484 int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
485 void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
486 u32 *lkey, u32 *rkey);
487 int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
488 int mlx4_SYNC_TPT(struct mlx4_dev *dev);
489 int mlx4_test_interrupts(struct mlx4_dev *dev);
491 #endif /* MLX4_DEVICE_H */