include/linux/mfd/tps65910.h

   1 /*
   2  * tps65910.h  --  TI TPS6591x
   3  *
   4  * Copyright 2010-2011 Texas Instruments Inc.
   5  *
   6  * Author: Graeme Gregory <gg@slimlogic.co.uk>
   7  * Author: Jorge Eduardo Candelaria <jedu@slimlogic.co.uk>
   8  * Author: Arnaud Deconinck <a-deconinck@ti.com>
   9  *
  10  *  This program is free software; you can redistribute it and/or modify it
  11  *  under  the terms of the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the License, or (at your
  13  *  option) any later version.
  14  *
  15  */
  16
  17 #ifndef __LINUX_MFD_TPS65910_H
  18 #define __LINUX_MFD_TPS65910_H
  19
  20 /*
  21  * List of registers for component TPS65910
  22  *
  23  */
  24
  25 #define TPS65910_SECONDS                                0x0
  26 #define TPS65910_MINUTES                                0x1
  27 #define TPS65910_HOURS                                  0x2
  28 #define TPS65910_DAYS                                   0x3
  29 #define TPS65910_MONTHS                                 0x4
  30 #define TPS65910_YEARS                                  0x5
  31 #define TPS65910_WEEKS                                  0x6
  32 #define TPS65910_ALARM_SECONDS                          0x8
  33 #define TPS65910_ALARM_MINUTES                          0x9
  34 #define TPS65910_ALARM_HOURS                            0xA
  35 #define TPS65910_ALARM_DAYS                             0xB
  36 #define TPS65910_ALARM_MONTHS                           0xC
  37 #define TPS65910_ALARM_YEARS                            0xD
  38 #define TPS65910_RTC_CTRL                               0x10
  39 #define TPS65910_RTC_STATUS                             0x11
  40 #define TPS65910_RTC_INTERRUPTS                         0x12
  41 #define TPS65910_RTC_COMP_LSB                           0x13
  42 #define TPS65910_RTC_COMP_MSB                           0x14
  43 #define TPS65910_RTC_RES_PROG                           0x15
  44 #define TPS65910_RTC_RESET_STATUS                       0x16
  45 #define TPS65910_BCK1                                   0x17
  46 #define TPS65910_BCK2                                   0x18
  47 #define TPS65910_BCK3                                   0x19
  48 #define TPS65910_BCK4                                   0x1A
  49 #define TPS65910_BCK5                                   0x1B
  50 #define TPS65910_PUADEN                                 0x1C
  51 #define TPS65910_REF                                    0x1D
  52 #define TPS65910_VRTC                                   0x1E
  53 #define TPS65910_VIO                                    0x20
  54 #define TPS65910_VDD1                                   0x21
  55 #define TPS65910_VDD1_OP                                0x22
  56 #define TPS65910_VDD1_SR                                0x23
  57 #define TPS65910_VDD2                                   0x24
  58 #define TPS65910_VDD2_OP                                0x25
  59 #define TPS65910_VDD2_SR                                0x26
  60 #define TPS65910_VDD3                                   0x27
  61 #define TPS65910_VDIG1                                  0x30
  62 #define TPS65910_VDIG2                                  0x31
  63 #define TPS65910_VAUX1                                  0x32
  64 #define TPS65910_VAUX2                                  0x33
  65 #define TPS65910_VAUX33                                 0x34
  66 #define TPS65910_VMMC                                   0x35
  67 #define TPS65910_VPLL                                   0x36
  68 #define TPS65910_VDAC                                   0x37
  69 #define TPS65910_THERM                                  0x38
  70 #define TPS65910_BBCH                                   0x39
  71 #define TPS65910_DCDCCTRL                               0x3E
  72 #define TPS65910_DEVCTRL                                0x3F
  73 #define TPS65910_DEVCTRL2                               0x40
  74 #define TPS65910_SLEEP_KEEP_LDO_ON                      0x41
  75 #define TPS65910_SLEEP_KEEP_RES_ON                      0x42
  76 #define TPS65910_SLEEP_SET_LDO_OFF                      0x43
  77 #define TPS65910_SLEEP_SET_RES_OFF                      0x44
  78 #define TPS65910_EN1_LDO_ASS                            0x45
  79 #define TPS65910_EN1_SMPS_ASS                           0x46
  80 #define TPS65910_EN2_LDO_ASS                            0x47
  81 #define TPS65910_EN2_SMPS_ASS                           0x48
  82 #define TPS65910_EN3_LDO_ASS                            0x49
  83 #define TPS65910_SPARE                                  0x4A
  84 #define TPS65910_INT_STS                                0x50
  85 #define TPS65910_INT_MSK                                0x51
  86 #define TPS65910_INT_STS2                               0x52
  87 #define TPS65910_INT_MSK2                               0x53
  88 #define TPS65910_INT_STS3                               0x54
  89 #define TPS65910_INT_MSK3                               0x55
  90 #define TPS65910_GPIO0                                  0x60
  91 #define TPS65910_GPIO1                                  0x61
  92 #define TPS65910_GPIO2                                  0x62
  93 #define TPS65910_GPIO3                                  0x63
  94 #define TPS65910_GPIO4                                  0x64
  95 #define TPS65910_GPIO5                                  0x65
  96 #define TPS65910_JTAGVERNUM                             0x80
  97 #define TPS65910_MAX_REGISTER                           0x80
  98
  99 /*
 100  * List of register bitfields for component TPS65910
 101  *
 102  */
 103
 104
 105 /*Register BCK1  (0x80) register.RegisterDescription */
 106 #define BCK1_BCKUP_MASK                                 0xFF
 107 #define BCK1_BCKUP_SHIFT                                0
 108
 109
 110 /*Register BCK2  (0x80) register.RegisterDescription */
 111 #define BCK2_BCKUP_MASK                                 0xFF
 112 #define BCK2_BCKUP_SHIFT                                0
 113
 114
 115 /*Register BCK3  (0x80) register.RegisterDescription */
 116 #define BCK3_BCKUP_MASK                                 0xFF
 117 #define BCK3_BCKUP_SHIFT                                0
 118
 119
 120 /*Register BCK4  (0x80) register.RegisterDescription */
 121 #define BCK4_BCKUP_MASK                                 0xFF
 122 #define BCK4_BCKUP_SHIFT                                0
 123
 124
 125 /*Register BCK5  (0x80) register.RegisterDescription */
 126 #define BCK5_BCKUP_MASK                                 0xFF
 127 #define BCK5_BCKUP_SHIFT                                0
 128
 129
 130 /*Register PUADEN  (0x80) register.RegisterDescription */
 131 #define PUADEN_EN3P_MASK                                0x80
 132 #define PUADEN_EN3P_SHIFT                               7
 133 #define PUADEN_I2CCTLP_MASK                             0x40
 134 #define PUADEN_I2CCTLP_SHIFT                            6
 135 #define PUADEN_I2CSRP_MASK                              0x20
 136 #define PUADEN_I2CSRP_SHIFT                             5
 137 #define PUADEN_PWRONP_MASK                              0x10
 138 #define PUADEN_PWRONP_SHIFT                             4
 139 #define PUADEN_SLEEPP_MASK                              0x08
 140 #define PUADEN_SLEEPP_SHIFT                             3
 141 #define PUADEN_PWRHOLDP_MASK                            0x04
 142 #define PUADEN_PWRHOLDP_SHIFT                           2
 143 #define PUADEN_BOOT1P_MASK                              0x02
 144 #define PUADEN_BOOT1P_SHIFT                             1
 145 #define PUADEN_BOOT0P_MASK                              0x01
 146 #define PUADEN_BOOT0P_SHIFT                             0
 147
 148
 149 /*Register REF  (0x80) register.RegisterDescription */
 150 #define REF_VMBCH_SEL_MASK                              0x0C
 151 #define REF_VMBCH_SEL_SHIFT                             2
 152 #define REF_ST_MASK                                     0x03
 153 #define REF_ST_SHIFT                                    0
 154
 155
 156 /*Register VRTC  (0x80) register.RegisterDescription */
 157 #define VRTC_VRTC_OFFMASK_MASK                          0x08
 158 #define VRTC_VRTC_OFFMASK_SHIFT                         3
 159 #define VRTC_ST_MASK                                    0x03
 160 #define VRTC_ST_SHIFT                                   0
 161
 162
 163 /*Register VIO  (0x80) register.RegisterDescription */
 164 #define VIO_ILMAX_MASK                                  0xC0
 165 #define VIO_ILMAX_SHIFT                                 6
 166 #define VIO_SEL_MASK                                    0x0C
 167 #define VIO_SEL_SHIFT                                   2
 168 #define VIO_ST_MASK                                     0x03
 169 #define VIO_ST_SHIFT                                    0
 170
 171
 172 /*Register VDD1  (0x80) register.RegisterDescription */
 173 #define VDD1_VGAIN_SEL_MASK                             0xC0
 174 #define VDD1_VGAIN_SEL_SHIFT                            6
 175 #define VDD1_ILMAX_MASK                                 0x20
 176 #define VDD1_ILMAX_SHIFT                                5
 177 #define VDD1_TSTEP_MASK                                 0x1C
 178 #define VDD1_TSTEP_SHIFT                                2
 179 #define VDD1_ST_MASK                                    0x03
 180 #define VDD1_ST_SHIFT                                   0
 181
 182
 183 /*Register VDD1_OP  (0x80) register.RegisterDescription */
 184 #define VDD1_OP_CMD_MASK                                0x80
 185 #define VDD1_OP_CMD_SHIFT                               7
 186 #define VDD1_OP_SEL_MASK                                0x7F
 187 #define VDD1_OP_SEL_SHIFT                               0
 188
 189
 190 /*Register VDD1_SR  (0x80) register.RegisterDescription */
 191 #define VDD1_SR_SEL_MASK                                0x7F
 192 #define VDD1_SR_SEL_SHIFT                               0
 193
 194
 195 /*Register VDD2  (0x80) register.RegisterDescription */
 196 #define VDD2_VGAIN_SEL_MASK                             0xC0
 197 #define VDD2_VGAIN_SEL_SHIFT                            6
 198 #define VDD2_ILMAX_MASK                                 0x20
 199 #define VDD2_ILMAX_SHIFT                                5
 200 #define VDD2_TSTEP_MASK                                 0x1C
 201 #define VDD2_TSTEP_SHIFT                                2
 202 #define VDD2_ST_MASK                                    0x03
 203 #define VDD2_ST_SHIFT                                   0
 204
 205
 206 /*Register VDD2_OP  (0x80) register.RegisterDescription */
 207 #define VDD2_OP_CMD_MASK                                0x80
 208 #define VDD2_OP_CMD_SHIFT                               7
 209 #define VDD2_OP_SEL_MASK                                0x7F
 210 #define VDD2_OP_SEL_SHIFT                               0
 211
 212
 213 /*Register VDD2_SR  (0x80) register.RegisterDescription */
 214 #define VDD2_SR_SEL_MASK                                0x7F
 215 #define VDD2_SR_SEL_SHIFT                               0
 216
 217
 218 /*Register VDD3  (0x80) register.RegisterDescription */
 219 #define VDD3_CKINEN_MASK                                0x04
 220 #define VDD3_CKINEN_SHIFT                               2
 221 #define VDD3_ST_MASK                                    0x03
 222 #define VDD3_ST_SHIFT                                   0
 223
 224
 225 /*Register VDIG1  (0x80) register.RegisterDescription */
 226 #define VDIG1_SEL_MASK                                  0x0C
 227 #define VDIG1_SEL_SHIFT                                 2
 228 #define VDIG1_ST_MASK                                   0x03
 229 #define VDIG1_ST_SHIFT                                  0
 230
 231
 232 /*Register VDIG2  (0x80) register.RegisterDescription */
 233 #define VDIG2_SEL_MASK                                  0x0C
 234 #define VDIG2_SEL_SHIFT                                 2
 235 #define VDIG2_ST_MASK                                   0x03
 236 #define VDIG2_ST_SHIFT                                  0
 237
 238
 239 /*Register VAUX1  (0x80) register.RegisterDescription */
 240 #define VAUX1_SEL_MASK                                  0x0C
 241 #define VAUX1_SEL_SHIFT                                 2
 242 #define VAUX1_ST_MASK                                   0x03
 243 #define VAUX1_ST_SHIFT                                  0
 244
 245
 246 /*Register VAUX2  (0x80) register.RegisterDescription */
 247 #define VAUX2_SEL_MASK                                  0x0C
 248 #define VAUX2_SEL_SHIFT                                 2
 249 #define VAUX2_ST_MASK                                   0x03
 250 #define VAUX2_ST_SHIFT                                  0
 251
 252
 253 /*Register VAUX33  (0x80) register.RegisterDescription */
 254 #define VAUX33_SEL_MASK                                 0x0C
 255 #define VAUX33_SEL_SHIFT                                2
 256 #define VAUX33_ST_MASK                                  0x03
 257 #define VAUX33_ST_SHIFT                                 0
 258
 259
 260 /*Register VMMC  (0x80) register.RegisterDescription */
 261 #define VMMC_SEL_MASK                                   0x0C
 262 #define VMMC_SEL_SHIFT                                  2
 263 #define VMMC_ST_MASK                                    0x03
 264 #define VMMC_ST_SHIFT                                   0
 265
 266
 267 /*Register VPLL  (0x80) register.RegisterDescription */
 268 #define VPLL_SEL_MASK                                   0x0C
 269 #define VPLL_SEL_SHIFT                                  2
 270 #define VPLL_ST_MASK                                    0x03
 271 #define VPLL_ST_SHIFT                                   0
 272
 273
 274 /*Register VDAC  (0x80) register.RegisterDescription */
 275 #define VDAC_SEL_MASK                                   0x0C
 276 #define VDAC_SEL_SHIFT                                  2
 277 #define VDAC_ST_MASK                                    0x03
 278 #define VDAC_ST_SHIFT                                   0
 279
 280
 281 /*Register THERM  (0x80) register.RegisterDescription */
 282 #define THERM_THERM_HD_MASK                             0x20
 283 #define THERM_THERM_HD_SHIFT                            5
 284 #define THERM_THERM_TS_MASK                             0x10
 285 #define THERM_THERM_TS_SHIFT                            4
 286 #define THERM_THERM_HDSEL_MASK                          0x0C
 287 #define THERM_THERM_HDSEL_SHIFT                         2
 288 #define THERM_RSVD1_MASK                                0x02
 289 #define THERM_RSVD1_SHIFT                               1
 290 #define THERM_THERM_STATE_MASK                          0x01
 291 #define THERM_THERM_STATE_SHIFT                         0
 292
 293
 294 /*Register BBCH  (0x80) register.RegisterDescription */
 295 #define BBCH_BBSEL_MASK                                 0x06
 296 #define BBCH_BBSEL_SHIFT                                1
 297 #define BBCH_BBCHEN_MASK                                0x01
 298 #define BBCH_BBCHEN_SHIFT                               0
 299
 300
 301 /*Register DCDCCTRL  (0x80) register.RegisterDescription */
 302 #define DCDCCTRL_VDD2_PSKIP_MASK                        0x20
 303 #define DCDCCTRL_VDD2_PSKIP_SHIFT                       5
 304 #define DCDCCTRL_VDD1_PSKIP_MASK                        0x10
 305 #define DCDCCTRL_VDD1_PSKIP_SHIFT                       4
 306 #define DCDCCTRL_VIO_PSKIP_MASK                         0x08
 307 #define DCDCCTRL_VIO_PSKIP_SHIFT                        3
 308 #define DCDCCTRL_DCDCCKEXT_MASK                         0x04
 309 #define DCDCCTRL_DCDCCKEXT_SHIFT                        2
 310 #define DCDCCTRL_DCDCCKSYNC_MASK                        0x03
 311 #define DCDCCTRL_DCDCCKSYNC_SHIFT                       0
 312
 313
 314 /*Register DEVCTRL  (0x80) register.RegisterDescription */
 315 #define DEVCTRL_RTC_PWDN_MASK                           0x40
 316 #define DEVCTRL_RTC_PWDN_SHIFT                          6
 317 #define DEVCTRL_CK32K_CTRL_MASK                         0x20
 318 #define DEVCTRL_CK32K_CTRL_SHIFT                        5
 319 #define DEVCTRL_SR_CTL_I2C_SEL_MASK                     0x10
 320 #define DEVCTRL_SR_CTL_I2C_SEL_SHIFT                    4
 321 #define DEVCTRL_DEV_OFF_RST_MASK                        0x08
 322 #define DEVCTRL_DEV_OFF_RST_SHIFT                       3
 323 #define DEVCTRL_DEV_ON_MASK                             0x04
 324 #define DEVCTRL_DEV_ON_SHIFT                            2
 325 #define DEVCTRL_DEV_SLP_MASK                            0x02
 326 #define DEVCTRL_DEV_SLP_SHIFT                           1
 327 #define DEVCTRL_DEV_OFF_MASK                            0x01
 328 #define DEVCTRL_DEV_OFF_SHIFT                           0
 329
 330
 331 /*Register DEVCTRL2  (0x80) register.RegisterDescription */
 332 #define DEVCTRL2_TSLOT_LENGTH_MASK                      0x30
 333 #define DEVCTRL2_TSLOT_LENGTH_SHIFT                     4
 334 #define DEVCTRL2_SLEEPSIG_POL_MASK                      0x08
 335 #define DEVCTRL2_SLEEPSIG_POL_SHIFT                     3
 336 #define DEVCTRL2_PWON_LP_OFF_MASK                       0x04
 337 #define DEVCTRL2_PWON_LP_OFF_SHIFT                      2
 338 #define DEVCTRL2_PWON_LP_RST_MASK                       0x02
 339 #define DEVCTRL2_PWON_LP_RST_SHIFT                      1
 340 #define DEVCTRL2_IT_POL_MASK                            0x01
 341 #define DEVCTRL2_IT_POL_SHIFT                           0
 342
 343
 344 /*Register SLEEP_KEEP_LDO_ON  (0x80) register.RegisterDescription */
 345 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_MASK              0x80
 346 #define SLEEP_KEEP_LDO_ON_VDAC_KEEPON_SHIFT             7
 347 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_MASK              0x40
 348 #define SLEEP_KEEP_LDO_ON_VPLL_KEEPON_SHIFT             6
 349 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_MASK            0x20
 350 #define SLEEP_KEEP_LDO_ON_VAUX33_KEEPON_SHIFT           5
 351 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_MASK             0x10
 352 #define SLEEP_KEEP_LDO_ON_VAUX2_KEEPON_SHIFT            4
 353 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_MASK             0x08
 354 #define SLEEP_KEEP_LDO_ON_VAUX1_KEEPON_SHIFT            3
 355 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_MASK             0x04
 356 #define SLEEP_KEEP_LDO_ON_VDIG2_KEEPON_SHIFT            2
 357 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_MASK             0x02
 358 #define SLEEP_KEEP_LDO_ON_VDIG1_KEEPON_SHIFT            1
 359 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_MASK              0x01
 360 #define SLEEP_KEEP_LDO_ON_VMMC_KEEPON_SHIFT             0
 361
 362
 363 /*Register SLEEP_KEEP_RES_ON  (0x80) register.RegisterDescription */
 364 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_MASK             0x80
 365 #define SLEEP_KEEP_RES_ON_THERM_KEEPON_SHIFT            7
 366 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_MASK         0x40
 367 #define SLEEP_KEEP_RES_ON_CLKOUT32K_KEEPON_SHIFT        6
 368 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_MASK              0x20
 369 #define SLEEP_KEEP_RES_ON_VRTC_KEEPON_SHIFT             5
 370 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_MASK             0x10
 371 #define SLEEP_KEEP_RES_ON_I2CHS_KEEPON_SHIFT            4
 372 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_MASK              0x08
 373 #define SLEEP_KEEP_RES_ON_VDD3_KEEPON_SHIFT             3
 374 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_MASK              0x04
 375 #define SLEEP_KEEP_RES_ON_VDD2_KEEPON_SHIFT             2
 376 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_MASK              0x02
 377 #define SLEEP_KEEP_RES_ON_VDD1_KEEPON_SHIFT             1
 378 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_MASK               0x01
 379 #define SLEEP_KEEP_RES_ON_VIO_KEEPON_SHIFT              0
 380
 381
 382 /*Register SLEEP_SET_LDO_OFF  (0x80) register.RegisterDescription */
 383 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_MASK              0x80
 384 #define SLEEP_SET_LDO_OFF_VDAC_SETOFF_SHIFT             7
 385 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_MASK              0x40
 386 #define SLEEP_SET_LDO_OFF_VPLL_SETOFF_SHIFT             6
 387 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_MASK            0x20
 388 #define SLEEP_SET_LDO_OFF_VAUX33_SETOFF_SHIFT           5
 389 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_MASK             0x10
 390 #define SLEEP_SET_LDO_OFF_VAUX2_SETOFF_SHIFT            4
 391 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_MASK             0x08
 392 #define SLEEP_SET_LDO_OFF_VAUX1_SETOFF_SHIFT            3
 393 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_MASK             0x04
 394 #define SLEEP_SET_LDO_OFF_VDIG2_SETOFF_SHIFT            2
 395 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_MASK             0x02
 396 #define SLEEP_SET_LDO_OFF_VDIG1_SETOFF_SHIFT            1
 397 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_MASK              0x01
 398 #define SLEEP_SET_LDO_OFF_VMMC_SETOFF_SHIFT             0
 399
 400
 401 /*Register SLEEP_SET_RES_OFF  (0x80) register.RegisterDescription */
 402 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_MASK             0x80
 403 #define SLEEP_SET_RES_OFF_DEFAULT_VOLT_SHIFT            7
 404 #define SLEEP_SET_RES_OFF_RSVD_MASK                     0x60
 405 #define SLEEP_SET_RES_OFF_RSVD_SHIFT                    5
 406 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_MASK             0x10
 407 #define SLEEP_SET_RES_OFF_SPARE_SETOFF_SHIFT            4
 408 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_MASK              0x08
 409 #define SLEEP_SET_RES_OFF_VDD3_SETOFF_SHIFT             3
 410 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_MASK              0x04
 411 #define SLEEP_SET_RES_OFF_VDD2_SETOFF_SHIFT             2
 412 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_MASK              0x02
 413 #define SLEEP_SET_RES_OFF_VDD1_SETOFF_SHIFT             1
 414 #define SLEEP_SET_RES_OFF_VIO_SETOFF_MASK               0x01
 415 #define SLEEP_SET_RES_OFF_VIO_SETOFF_SHIFT              0
 416
 417
 418 /*Register EN1_LDO_ASS  (0x80) register.RegisterDescription */
 419 #define EN1_LDO_ASS_VDAC_EN1_MASK                       0x80
 420 #define EN1_LDO_ASS_VDAC_EN1_SHIFT                      7
 421 #define EN1_LDO_ASS_VPLL_EN1_MASK                       0x40
 422 #define EN1_LDO_ASS_VPLL_EN1_SHIFT                      6
 423 #define EN1_LDO_ASS_VAUX33_EN1_MASK                     0x20
 424 #define EN1_LDO_ASS_VAUX33_EN1_SHIFT                    5
 425 #define EN1_LDO_ASS_VAUX2_EN1_MASK                      0x10
 426 #define EN1_LDO_ASS_VAUX2_EN1_SHIFT                     4
 427 #define EN1_LDO_ASS_VAUX1_EN1_MASK                      0x08
 428 #define EN1_LDO_ASS_VAUX1_EN1_SHIFT                     3
 429 #define EN1_LDO_ASS_VDIG2_EN1_MASK                      0x04
 430 #define EN1_LDO_ASS_VDIG2_EN1_SHIFT                     2
 431 #define EN1_LDO_ASS_VDIG1_EN1_MASK                      0x02
 432 #define EN1_LDO_ASS_VDIG1_EN1_SHIFT                     1
 433 #define EN1_LDO_ASS_VMMC_EN1_MASK                       0x01
 434 #define EN1_LDO_ASS_VMMC_EN1_SHIFT                      0
 435
 436
 437 /*Register EN1_SMPS_ASS  (0x80) register.RegisterDescription */
 438 #define EN1_SMPS_ASS_RSVD_MASK                          0xE0
 439 #define EN1_SMPS_ASS_RSVD_SHIFT                         5
 440 #define EN1_SMPS_ASS_SPARE_EN1_MASK                     0x10
 441 #define EN1_SMPS_ASS_SPARE_EN1_SHIFT                    4
 442 #define EN1_SMPS_ASS_VDD3_EN1_MASK                      0x08
 443 #define EN1_SMPS_ASS_VDD3_EN1_SHIFT                     3
 444 #define EN1_SMPS_ASS_VDD2_EN1_MASK                      0x04
 445 #define EN1_SMPS_ASS_VDD2_EN1_SHIFT                     2
 446 #define EN1_SMPS_ASS_VDD1_EN1_MASK                      0x02
 447 #define EN1_SMPS_ASS_VDD1_EN1_SHIFT                     1
 448 #define EN1_SMPS_ASS_VIO_EN1_MASK                       0x01
 449 #define EN1_SMPS_ASS_VIO_EN1_SHIFT                      0
 450
 451
 452 /*Register EN2_LDO_ASS  (0x80) register.RegisterDescription */
 453 #define EN2_LDO_ASS_VDAC_EN2_MASK                       0x80
 454 #define EN2_LDO_ASS_VDAC_EN2_SHIFT                      7
 455 #define EN2_LDO_ASS_VPLL_EN2_MASK                       0x40
 456 #define EN2_LDO_ASS_VPLL_EN2_SHIFT                      6
 457 #define EN2_LDO_ASS_VAUX33_EN2_MASK                     0x20
 458 #define EN2_LDO_ASS_VAUX33_EN2_SHIFT                    5
 459 #define EN2_LDO_ASS_VAUX2_EN2_MASK                      0x10
 460 #define EN2_LDO_ASS_VAUX2_EN2_SHIFT                     4
 461 #define EN2_LDO_ASS_VAUX1_EN2_MASK                      0x08
 462 #define EN2_LDO_ASS_VAUX1_EN2_SHIFT                     3
 463 #define EN2_LDO_ASS_VDIG2_EN2_MASK                      0x04
 464 #define EN2_LDO_ASS_VDIG2_EN2_SHIFT                     2
 465 #define EN2_LDO_ASS_VDIG1_EN2_MASK                      0x02
 466 #define EN2_LDO_ASS_VDIG1_EN2_SHIFT                     1
 467 #define EN2_LDO_ASS_VMMC_EN2_MASK                       0x01
 468 #define EN2_LDO_ASS_VMMC_EN2_SHIFT                      0
 469
 470
 471 /*Register EN2_SMPS_ASS  (0x80) register.RegisterDescription */
 472 #define EN2_SMPS_ASS_RSVD_MASK                          0xE0
 473 #define EN2_SMPS_ASS_RSVD_SHIFT                         5
 474 #define EN2_SMPS_ASS_SPARE_EN2_MASK                     0x10
 475 #define EN2_SMPS_ASS_SPARE_EN2_SHIFT                    4
 476 #define EN2_SMPS_ASS_VDD3_EN2_MASK                      0x08
 477 #define EN2_SMPS_ASS_VDD3_EN2_SHIFT                     3
 478 #define EN2_SMPS_ASS_VDD2_EN2_MASK                      0x04
 479 #define EN2_SMPS_ASS_VDD2_EN2_SHIFT                     2
 480 #define EN2_SMPS_ASS_VDD1_EN2_MASK                      0x02
 481 #define EN2_SMPS_ASS_VDD1_EN2_SHIFT                     1
 482 #define EN2_SMPS_ASS_VIO_EN2_MASK                       0x01
 483 #define EN2_SMPS_ASS_VIO_EN2_SHIFT                      0
 484
 485
 486 /*Register EN3_LDO_ASS  (0x80) register.RegisterDescription */
 487 #define EN3_LDO_ASS_VDAC_EN3_MASK                       0x80
 488 #define EN3_LDO_ASS_VDAC_EN3_SHIFT                      7
 489 #define EN3_LDO_ASS_VPLL_EN3_MASK                       0x40
 490 #define EN3_LDO_ASS_VPLL_EN3_SHIFT                      6
 491 #define EN3_LDO_ASS_VAUX33_EN3_MASK                     0x20
 492 #define EN3_LDO_ASS_VAUX33_EN3_SHIFT                    5
 493 #define EN3_LDO_ASS_VAUX2_EN3_MASK                      0x10
 494 #define EN3_LDO_ASS_VAUX2_EN3_SHIFT                     4
 495 #define EN3_LDO_ASS_VAUX1_EN3_MASK                      0x08
 496 #define EN3_LDO_ASS_VAUX1_EN3_SHIFT                     3
 497 #define EN3_LDO_ASS_VDIG2_EN3_MASK                      0x04
 498 #define EN3_LDO_ASS_VDIG2_EN3_SHIFT                     2
 499 #define EN3_LDO_ASS_VDIG1_EN3_MASK                      0x02
 500 #define EN3_LDO_ASS_VDIG1_EN3_SHIFT                     1
 501 #define EN3_LDO_ASS_VMMC_EN3_MASK                       0x01
 502 #define EN3_LDO_ASS_VMMC_EN3_SHIFT                      0
 503
 504
 505 /*Register SPARE  (0x80) register.RegisterDescription */
 506 #define SPARE_SPARE_MASK                                0xFF
 507 #define SPARE_SPARE_SHIFT                               0
 508
 509
 510 /*Register INT_STS  (0x80) register.RegisterDescription */
 511 #define INT_STS_RTC_PERIOD_IT_MASK                      0x80
 512 #define INT_STS_RTC_PERIOD_IT_SHIFT                     7
 513 #define INT_STS_RTC_ALARM_IT_MASK                       0x40
 514 #define INT_STS_RTC_ALARM_IT_SHIFT                      6
 515 #define INT_STS_HOTDIE_IT_MASK                          0x20
 516 #define INT_STS_HOTDIE_IT_SHIFT                         5
 517 #define INT_STS_PWRHOLD_IT_MASK                         0x10
 518 #define INT_STS_PWRHOLD_IT_SHIFT                        4
 519 #define INT_STS_PWRON_LP_IT_MASK                        0x08
 520 #define INT_STS_PWRON_LP_IT_SHIFT                       3
 521 #define INT_STS_PWRON_IT_MASK                           0x04
 522 #define INT_STS_PWRON_IT_SHIFT                          2
 523 #define INT_STS_VMBHI_IT_MASK                           0x02
 524 #define INT_STS_VMBHI_IT_SHIFT                          1
 525 #define INT_STS_VMBDCH_IT_MASK                          0x01
 526 #define INT_STS_VMBDCH_IT_SHIFT                         0
 527
 528
 529 /*Register INT_MSK  (0x80) register.RegisterDescription */
 530 #define INT_MSK_RTC_PERIOD_IT_MSK_MASK                  0x80
 531 #define INT_MSK_RTC_PERIOD_IT_MSK_SHIFT                 7
 532 #define INT_MSK_RTC_ALARM_IT_MSK_MASK                   0x40
 533 #define INT_MSK_RTC_ALARM_IT_MSK_SHIFT                  6
 534 #define INT_MSK_HOTDIE_IT_MSK_MASK                      0x20
 535 #define INT_MSK_HOTDIE_IT_MSK_SHIFT                     5
 536 #define INT_MSK_PWRHOLD_IT_MSK_MASK                     0x10
 537 #define INT_MSK_PWRHOLD_IT_MSK_SHIFT                    4
 538 #define INT_MSK_PWRON_LP_IT_MSK_MASK                    0x08
 539 #define INT_MSK_PWRON_LP_IT_MSK_SHIFT                   3
 540 #define INT_MSK_PWRON_IT_MSK_MASK                       0x04
 541 #define INT_MSK_PWRON_IT_MSK_SHIFT                      2
 542 #define INT_MSK_VMBHI_IT_MSK_MASK                       0x02
 543 #define INT_MSK_VMBHI_IT_MSK_SHIFT                      1
 544 #define INT_MSK_VMBDCH_IT_MSK_MASK                      0x01
 545 #define INT_MSK_VMBDCH_IT_MSK_SHIFT                     0
 546
 547
 548 /*Register INT_STS2  (0x80) register.RegisterDescription */
 549 #define INT_STS2_GPIO3_F_IT_MASK                        0x80
 550 #define INT_STS2_GPIO3_F_IT_SHIFT                       7
 551 #define INT_STS2_GPIO3_R_IT_MASK                        0x40
 552 #define INT_STS2_GPIO3_R_IT_SHIFT                       6
 553 #define INT_STS2_GPIO2_F_IT_MASK                        0x20
 554 #define INT_STS2_GPIO2_F_IT_SHIFT                       5
 555 #define INT_STS2_GPIO2_R_IT_MASK                        0x10
 556 #define INT_STS2_GPIO2_R_IT_SHIFT                       4
 557 #define INT_STS2_GPIO1_F_IT_MASK                        0x08
 558 #define INT_STS2_GPIO1_F_IT_SHIFT                       3
 559 #define INT_STS2_GPIO1_R_IT_MASK                        0x04
 560 #define INT_STS2_GPIO1_R_IT_SHIFT                       2
 561 #define INT_STS2_GPIO0_F_IT_MASK                        0x02
 562 #define INT_STS2_GPIO0_F_IT_SHIFT                       1
 563 #define INT_STS2_GPIO0_R_IT_MASK                        0x01
 564 #define INT_STS2_GPIO0_R_IT_SHIFT                       0
 565
 566
 567 /*Register INT_MSK2  (0x80) register.RegisterDescription */
 568 #define INT_MSK2_GPIO3_F_IT_MSK_MASK                    0x80
 569 #define INT_MSK2_GPIO3_F_IT_MSK_SHIFT                   7
 570 #define INT_MSK2_GPIO3_R_IT_MSK_MASK                    0x40
 571 #define INT_MSK2_GPIO3_R_IT_MSK_SHIFT                   6
 572 #define INT_MSK2_GPIO2_F_IT_MSK_MASK                    0x20
 573 #define INT_MSK2_GPIO2_F_IT_MSK_SHIFT                   5
 574 #define INT_MSK2_GPIO2_R_IT_MSK_MASK                    0x10
 575 #define INT_MSK2_GPIO2_R_IT_MSK_SHIFT                   4
 576 #define INT_MSK2_GPIO1_F_IT_MSK_MASK                    0x08
 577 #define INT_MSK2_GPIO1_F_IT_MSK_SHIFT                   3
 578 #define INT_MSK2_GPIO1_R_IT_MSK_MASK                    0x04
 579 #define INT_MSK2_GPIO1_R_IT_MSK_SHIFT                   2
 580 #define INT_MSK2_GPIO0_F_IT_MSK_MASK                    0x02
 581 #define INT_MSK2_GPIO0_F_IT_MSK_SHIFT                   1
 582 #define INT_MSK2_GPIO0_R_IT_MSK_MASK                    0x01
 583 #define INT_MSK2_GPIO0_R_IT_MSK_SHIFT                   0
 584
 585
 586 /*Register INT_STS3  (0x80) register.RegisterDescription */
 587 #define INT_STS3_GPIO5_F_IT_MASK                        0x08
 588 #define INT_STS3_GPIO5_F_IT_SHIFT                       3
 589 #define INT_STS3_GPIO5_R_IT_MASK                        0x04
 590 #define INT_STS3_GPIO5_R_IT_SHIFT                       2
 591 #define INT_STS3_GPIO4_F_IT_MASK                        0x02
 592 #define INT_STS3_GPIO4_F_IT_SHIFT                       1
 593 #define INT_STS3_GPIO4_R_IT_MASK                        0x01
 594 #define INT_STS3_GPIO4_R_IT_SHIFT                       0
 595
 596
 597 /*Register INT_MSK3  (0x80) register.RegisterDescription */
 598 #define INT_MSK3_GPIO5_F_IT_MSK_MASK                    0x08
 599 #define INT_MSK3_GPIO5_F_IT_MSK_SHIFT                   3
 600 #define INT_MSK3_GPIO5_R_IT_MSK_MASK                    0x04
 601 #define INT_MSK3_GPIO5_R_IT_MSK_SHIFT                   2
 602 #define INT_MSK3_GPIO4_F_IT_MSK_MASK                    0x02
 603 #define INT_MSK3_GPIO4_F_IT_MSK_SHIFT                   1
 604 #define INT_MSK3_GPIO4_R_IT_MSK_MASK                    0x01
 605 #define INT_MSK3_GPIO4_R_IT_MSK_SHIFT                   0
 606
 607
 608 /*Register GPIO0  (0x80) register.RegisterDescription */
 609 #define GPIO0_GPIO_DEB_MASK                             0x10
 610 #define GPIO0_GPIO_DEB_SHIFT                            4
 611 #define GPIO0_GPIO_PUEN_MASK                            0x08
 612 #define GPIO0_GPIO_PUEN_SHIFT                           3
 613 #define GPIO0_GPIO_CFG_MASK                             0x04
 614 #define GPIO0_GPIO_CFG_SHIFT                            2
 615 #define GPIO0_GPIO_STS_MASK                             0x02
 616 #define GPIO0_GPIO_STS_SHIFT                            1
 617 #define GPIO0_GPIO_SET_MASK                             0x01
 618 #define GPIO0_GPIO_SET_SHIFT                            0
 619
 620
 621 /*Register GPIO1  (0x80) register.RegisterDescription */
 622 #define GPIO1_GPIO_DEB_MASK                             0x10
 623 #define GPIO1_GPIO_DEB_SHIFT                            4
 624 #define GPIO1_GPIO_PUEN_MASK                            0x08
 625 #define GPIO1_GPIO_PUEN_SHIFT                           3
 626 #define GPIO1_GPIO_CFG_MASK                             0x04
 627 #define GPIO1_GPIO_CFG_SHIFT                            2
 628 #define GPIO1_GPIO_STS_MASK                             0x02
 629 #define GPIO1_GPIO_STS_SHIFT                            1
 630 #define GPIO1_GPIO_SET_MASK                             0x01
 631 #define GPIO1_GPIO_SET_SHIFT                            0
 632
 633
 634 /*Register GPIO2  (0x80) register.RegisterDescription */
 635 #define GPIO2_GPIO_DEB_MASK                             0x10
 636 #define GPIO2_GPIO_DEB_SHIFT                            4
 637 #define GPIO2_GPIO_PUEN_MASK                            0x08
 638 #define GPIO2_GPIO_PUEN_SHIFT                           3
 639 #define GPIO2_GPIO_CFG_MASK                             0x04
 640 #define GPIO2_GPIO_CFG_SHIFT                            2
 641 #define GPIO2_GPIO_STS_MASK                             0x02
 642 #define GPIO2_GPIO_STS_SHIFT                            1
 643 #define GPIO2_GPIO_SET_MASK                             0x01
 644 #define GPIO2_GPIO_SET_SHIFT                            0
 645
 646
 647 /*Register GPIO3  (0x80) register.RegisterDescription */
 648 #define GPIO3_GPIO_DEB_MASK                             0x10
 649 #define GPIO3_GPIO_DEB_SHIFT                            4
 650 #define GPIO3_GPIO_PUEN_MASK                            0x08
 651 #define GPIO3_GPIO_PUEN_SHIFT                           3
 652 #define GPIO3_GPIO_CFG_MASK                             0x04
 653 #define GPIO3_GPIO_CFG_SHIFT                            2
 654 #define GPIO3_GPIO_STS_MASK                             0x02
 655 #define GPIO3_GPIO_STS_SHIFT                            1
 656 #define GPIO3_GPIO_SET_MASK                             0x01
 657 #define GPIO3_GPIO_SET_SHIFT                            0
 658
 659
 660 /*Register GPIO4  (0x80) register.RegisterDescription */
 661 #define GPIO4_GPIO_DEB_MASK                             0x10
 662 #define GPIO4_GPIO_DEB_SHIFT                            4
 663 #define GPIO4_GPIO_PUEN_MASK                            0x08
 664 #define GPIO4_GPIO_PUEN_SHIFT                           3
 665 #define GPIO4_GPIO_CFG_MASK                             0x04
 666 #define GPIO4_GPIO_CFG_SHIFT                            2
 667 #define GPIO4_GPIO_STS_MASK                             0x02
 668 #define GPIO4_GPIO_STS_SHIFT                            1
 669 #define GPIO4_GPIO_SET_MASK                             0x01
 670 #define GPIO4_GPIO_SET_SHIFT                            0
 671
 672
 673 /*Register GPIO5  (0x80) register.RegisterDescription */
 674 #define GPIO5_GPIO_DEB_MASK                             0x10
 675 #define GPIO5_GPIO_DEB_SHIFT                            4
 676 #define GPIO5_GPIO_PUEN_MASK                            0x08
 677 #define GPIO5_GPIO_PUEN_SHIFT                           3
 678 #define GPIO5_GPIO_CFG_MASK                             0x04
 679 #define GPIO5_GPIO_CFG_SHIFT                            2
 680 #define GPIO5_GPIO_STS_MASK                             0x02
 681 #define GPIO5_GPIO_STS_SHIFT                            1
 682 #define GPIO5_GPIO_SET_MASK                             0x01
 683 #define GPIO5_GPIO_SET_SHIFT                            0
 684
 685
 686 /*Register JTAGVERNUM  (0x80) register.RegisterDescription */
 687 #define JTAGVERNUM_VERNUM_MASK                          0x0F
 688 #define JTAGVERNUM_VERNUM_SHIFT                         0
 689
 690
 691 /* IRQ Definitions */
 692 #define TPS65910_IRQ_VBAT_VMBDCH                        0
 693 #define TPS65910_IRQ_VBAT_VMHI                          1
 694 #define TPS65910_IRQ_PWRON                              2
 695 #define TPS65910_IRQ_PWRON_LP                           3
 696 #define TPS65910_IRQ_PWRHOLD                            4
 697 #define TPS65910_IRQ_HOTDIE                             5
 698 #define TPS65910_IRQ_RTC_ALARM                          6
 699 #define TPS65910_IRQ_RTC_PERIOD                         7
 700 #define TPS65910_IRQ_GPIO_R                             8
 701 #define TPS65910_IRQ_GPIO_F                             9
 702 #define TPS65910_NUM_IRQ                                10
 703
 704 /* GPIO Register Definitions */
 705 #define TPS65910_GPIO_DEB                               BIT(2)
 706 #define TPS65910_GPIO_PUEN                              BIT(3)
 707 #define TPS65910_GPIO_CFG                               BIT(2)
 708 #define TPS65910_GPIO_STS                               BIT(1)
 709 #define TPS65910_GPIO_SET                               BIT(0)
 710
 711 /**
 712  * struct tps65910_board
 713  * Board platform data may be used to initialize regulators.
 714  */
 715
 716 struct tps65910_board {
 717         int gpio_base;
 718         struct regulator_init_data *tps65910_pmic_init_data;
 719 };
 720
 721 /**
 722  * struct tps65910 - tps65910 sub-driver chip access routines
 723  */
 724
 725 struct tps65910 {
 726         struct device *dev;
 727         struct i2c_client *i2c_client;
 728         struct mutex io_mutex;
 729         int (*read)(struct tps65910 *tps65910, u8 reg, int size, void *dest);
 730         int (*write)(struct tps65910 *tps65910, u8 reg, int size, void *src);
 731
 732         /* Client devices */
 733         struct tps65910_pmic *pmic;
 734         struct tps65910_rtc *rtc;
 735         struct tps65910_power *power;
 736
 737         /* GPIO Handling */
 738         struct gpio_chip gpio;
 739
 740         /* IRQ Handling */
 741         struct mutex irq_lock;
 742         int chip_irq;
 743         int irq_base;
 744         u16 irq_mask;
 745 };
 746
 747 struct tps65910_platform_data {
 748         int irq_base;
 749 };
 750
 751 int tps65910_set_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
 752 int tps65910_clear_bits(struct tps65910 *tps65910, u8 reg, u8 mask);
 753 void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base);
 754
 755 #endif /*  __LINUX_MFD_TPS65910_H */