2 * rk808.h for Rockchip RK808
4 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
6 * Author: Chris Zhong <zyw@rock-chips.com>
7 * Author: Zhang Qing <zhangqing@rock-chips.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #ifndef __LINUX_REGULATOR_rk808_H
20 #define __LINUX_REGULATOR_rk808_H
22 #include <linux/regulator/machine.h>
23 #include <linux/regmap.h>
26 * rk808 Global Register Map.
29 #define RK808_DCDC1 0 /* (0+RK808_START) */
30 #define RK808_LDO1 4 /* (4+RK808_START) */
31 #define RK808_NUM_REGULATORS 14
80 #define RK808_SECONDS_REG 0x00
81 #define RK808_MINUTES_REG 0x01
82 #define RK808_HOURS_REG 0x02
83 #define RK808_DAYS_REG 0x03
84 #define RK808_MONTHS_REG 0x04
85 #define RK808_YEARS_REG 0x05
86 #define RK808_WEEKS_REG 0x06
87 #define RK808_ALARM_SECONDS_REG 0x08
88 #define RK808_ALARM_MINUTES_REG 0x09
89 #define RK808_ALARM_HOURS_REG 0x0a
90 #define RK808_ALARM_DAYS_REG 0x0b
91 #define RK808_ALARM_MONTHS_REG 0x0c
92 #define RK808_ALARM_YEARS_REG 0x0d
93 #define RK808_RTC_CTRL_REG 0x10
94 #define RK808_RTC_STATUS_REG 0x11
95 #define RK808_RTC_INT_REG 0x12
96 #define RK808_RTC_COMP_LSB_REG 0x13
97 #define RK808_RTC_COMP_MSB_REG 0x14
98 #define RK808_ID_MSB 0x17
99 #define RK808_ID_LSB 0x18
100 #define RK808_CLK32OUT_REG 0x20
101 #define RK808_VB_MON_REG 0x21
102 #define RK808_THERMAL_REG 0x22
103 #define RK808_DCDC_EN_REG 0x23
104 #define RK808_LDO_EN_REG 0x24
105 #define RK808_SLEEP_SET_OFF_REG1 0x25
106 #define RK808_SLEEP_SET_OFF_REG2 0x26
107 #define RK808_DCDC_UV_STS_REG 0x27
108 #define RK808_DCDC_UV_ACT_REG 0x28
109 #define RK808_LDO_UV_STS_REG 0x29
110 #define RK808_LDO_UV_ACT_REG 0x2a
111 #define RK808_DCDC_PG_REG 0x2b
112 #define RK808_LDO_PG_REG 0x2c
113 #define RK808_VOUT_MON_TDB_REG 0x2d
114 #define RK808_BUCK1_CONFIG_REG 0x2e
115 #define RK808_BUCK1_ON_VSEL_REG 0x2f
116 #define RK808_BUCK1_SLP_VSEL_REG 0x30
117 #define RK808_BUCK1_DVS_VSEL_REG 0x31
118 #define RK808_BUCK2_CONFIG_REG 0x32
119 #define RK808_BUCK2_ON_VSEL_REG 0x33
120 #define RK808_BUCK2_SLP_VSEL_REG 0x34
121 #define RK808_BUCK2_DVS_VSEL_REG 0x35
122 #define RK808_BUCK3_CONFIG_REG 0x36
123 #define RK808_BUCK4_CONFIG_REG 0x37
124 #define RK808_BUCK4_ON_VSEL_REG 0x38
125 #define RK808_BUCK4_SLP_VSEL_REG 0x39
126 #define RK808_BOOST_CONFIG_REG 0x3a
127 #define RK808_LDO1_ON_VSEL_REG 0x3b
128 #define RK808_LDO1_SLP_VSEL_REG 0x3c
129 #define RK808_LDO2_ON_VSEL_REG 0x3d
130 #define RK808_LDO2_SLP_VSEL_REG 0x3e
131 #define RK808_LDO3_ON_VSEL_REG 0x3f
132 #define RK808_LDO3_SLP_VSEL_REG 0x40
133 #define RK808_LDO4_ON_VSEL_REG 0x41
134 #define RK808_LDO4_SLP_VSEL_REG 0x42
135 #define RK808_LDO5_ON_VSEL_REG 0x43
136 #define RK808_LDO5_SLP_VSEL_REG 0x44
137 #define RK808_LDO6_ON_VSEL_REG 0x45
138 #define RK808_LDO6_SLP_VSEL_REG 0x46
139 #define RK808_LDO7_ON_VSEL_REG 0x47
140 #define RK808_LDO7_SLP_VSEL_REG 0x48
141 #define RK808_LDO8_ON_VSEL_REG 0x49
142 #define RK808_LDO8_SLP_VSEL_REG 0x4a
143 #define RK808_DEVCTRL_REG 0x4b
144 #define RK808_INT_STS_REG1 0x4c
145 #define RK808_INT_STS_MSK_REG1 0x4d
146 #define RK808_INT_STS_REG2 0x4e
147 #define RK808_INT_STS_MSK_REG2 0x4f
148 #define RK808_IO_POL_REG 0x50
150 #define RK818_VB_MON_REG 0x21
151 #define RK818_THERMAL_REG 0x22
152 #define RK818_DCDC_EN_REG 0x23
153 #define RK818_LDO_EN_REG 0x24
154 #define RK818_SLEEP_SET_OFF_REG1 0x25
155 #define RK818_SLEEP_SET_OFF_REG2 0x26
156 #define RK818_DCDC_UV_STS_REG 0x27
157 #define RK818_DCDC_UV_ACT_REG 0x28
158 #define RK818_LDO_UV_STS_REG 0x29
159 #define RK818_LDO_UV_ACT_REG 0x2a
160 #define RK818_DCDC_PG_REG 0x2b
161 #define RK818_LDO_PG_REG 0x2c
162 #define RK818_VOUT_MON_TDB_REG 0x2d
163 #define RK818_BUCK1_CONFIG_REG 0x2e
164 #define RK818_BUCK1_ON_VSEL_REG 0x2f
165 #define RK818_BUCK1_SLP_VSEL_REG 0x30
166 #define RK818_BUCK2_CONFIG_REG 0x32
167 #define RK818_BUCK2_ON_VSEL_REG 0x33
168 #define RK818_BUCK2_SLP_VSEL_REG 0x34
169 #define RK818_BUCK3_CONFIG_REG 0x36
170 #define RK818_BUCK4_CONFIG_REG 0x37
171 #define RK818_BUCK4_ON_VSEL_REG 0x38
172 #define RK818_BUCK4_SLP_VSEL_REG 0x39
173 #define RK818_BOOST_CONFIG_REG 0x3a
174 #define RK818_LDO1_ON_VSEL_REG 0x3b
175 #define RK818_LDO1_SLP_VSEL_REG 0x3c
176 #define RK818_LDO2_ON_VSEL_REG 0x3d
177 #define RK818_LDO2_SLP_VSEL_REG 0x3e
178 #define RK818_LDO3_ON_VSEL_REG 0x3f
179 #define RK818_LDO3_SLP_VSEL_REG 0x40
180 #define RK818_LDO4_ON_VSEL_REG 0x41
181 #define RK818_LDO4_SLP_VSEL_REG 0x42
182 #define RK818_LDO5_ON_VSEL_REG 0x43
183 #define RK818_LDO5_SLP_VSEL_REG 0x44
184 #define RK818_LDO6_ON_VSEL_REG 0x45
185 #define RK818_LDO6_SLP_VSEL_REG 0x46
186 #define RK818_LDO7_ON_VSEL_REG 0x47
187 #define RK818_LDO7_SLP_VSEL_REG 0x48
188 #define RK818_LDO8_ON_VSEL_REG 0x49
189 #define RK818_LDO8_SLP_VSEL_REG 0x4a
190 #define RK818_DEVCTRL_REG 0x4b
191 #define RK818_INT_STS_REG1 0X4c
192 #define RK818_INT_STS_MSK_REG1 0X4d
193 #define RK818_INT_STS_REG2 0X4e
194 #define RK818_INT_STS_MSK_REG2 0X4f
195 #define RK818_IO_POL_REG 0X50
196 #define RK818_OTP_VDD_EN_REG 0x51
197 #define RK818_H5V_EN_REG 0x52
198 #define RK818_SLEEP_SET_OFF_REG3 0x53
199 #define RK818_BOOST_LDO9_ON_VSEL_REG 0x54
200 #define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55
201 #define RK818_BOOST_CTRL_REG 0x56
202 #define RK818_DCDC_ILMAX_REG 0x90
203 #define RK818_CHRG_COMP_REG 0x9a
204 #define RK818_SUP_STS_REG 0xa0
205 #define RK818_USB_CTRL_REG 0xa1
206 #define RK818_CHRG_CTRL_REG1 0xa3
207 #define RK818_CHRG_CTRL_REG2 0xa4
208 #define RK818_CHRG_CTRL_REG3 0xa5
209 #define RK818_BAT_CTRL_REG 0xa6
210 #define RK818_BAT_HTS_TS1_REG 0xa8
211 #define RK818_BAT_LTS_TS1_REG 0xa9
212 #define RK818_BAT_HTS_TS2_REG 0xaa
213 #define RK818_BAT_LTS_TS2_REG 0xab
214 #define RK818_TS_CTRL_REG 0xac
215 #define RK818_ADC_CTRL_REG 0xad
216 #define RK818_ON_SOURCE_REG 0xae
217 #define RK818_OFF_SOURCE_REG 0xaf
218 #define RK818_GGCON_REG 0xb0
219 #define RK818_GGSTS_REG 0xb1
220 #define RK818_FRAME_SMP_INTERV_REG 0xb2
221 #define RK818_AUTO_SLP_CUR_THR_REG 0xb3
222 #define RK818_GASCNT_CAL_REG3 0xb4
223 #define RK818_GASCNT_CAL_REG2 0xb5
224 #define RK818_GASCNT_CAL_REG1 0xb6
225 #define RK818_GASCNT_CAL_REG0 0xb7
226 #define RK818_GASCNT3_REG 0xb8
227 #define RK818_GASCNT2_REG 0xb9
228 #define RK818_GASCNT1_REG 0xba
229 #define RK818_GASCNT0_REG 0xbb
230 #define RK818_BAT_CUR_AVG_REGH 0xbc
231 #define RK818_BAT_CUR_AVG_REGL 0xbd
232 #define RK818_TS1_ADC_REGH 0xbe
233 #define RK818_TS1_ADC_REGL 0xbf
234 #define RK818_TS2_ADC_REGH 0xc0
235 #define RK818_TS2_ADC_REGL 0xc1
236 #define RK818_BAT_OCV_REGH 0xc2
237 #define RK818_BAT_OCV_REGL 0xc3
238 #define RK818_BAT_VOL_REGH 0xc4
239 #define RK818_BAT_VOL_REGL 0xc5
240 #define RK818_RELAX_ENTRY_THRES_REGH 0xc6
241 #define RK818_RELAX_ENTRY_THRES_REGL 0xc7
242 #define RK818_RELAX_EXIT_THRES_REGH 0xc8
243 #define RK818_RELAX_EXIT_THRES_REGL 0xc9
244 #define RK818_RELAX_VOL1_REGH 0xca
245 #define RK818_RELAX_VOL1_REGL 0xcb
246 #define RK818_RELAX_VOL2_REGH 0xcc
247 #define RK818_RELAX_VOL2_REGL 0xcd
248 #define RK818_BAT_CUR_R_CALC_REGH 0xce
249 #define RK818_BAT_CUR_R_CALC_REGL 0xcf
250 #define RK818_BAT_VOL_R_CALC_REGH 0xd0
251 #define RK818_BAT_VOL_R_CALC_REGL 0xd1
252 #define RK818_CAL_OFFSET_REGH 0xd2
253 #define RK818_CAL_OFFSET_REGL 0xd3
254 #define RK818_NON_ACT_TIMER_CNT_REG 0xd4
255 #define RK818_VCALIB0_REGH 0xd5
256 #define RK818_VCALIB0_REGL 0xd6
257 #define RK818_VCALIB1_REGH 0xd7
258 #define RK818_VCALIB1_REGL 0xd8
259 #define RK818_IOFFSET_REGH 0xdd
260 #define RK818_IOFFSET_REGL 0xde
261 #define RK818_SOC_REG 0xe0
262 #define RK818_REMAIN_CAP_REG3 0xe1
263 #define RK818_REMAIN_CAP_REG2 0xe2
264 #define RK818_REMAIN_CAP_REG1 0xe3
265 #define RK818_REMAIN_CAP_REG0 0xe4
266 #define RK818_UPDAT_LEVE_REG 0xe5
267 #define RK818_NEW_FCC_REG3 0xe6
268 #define RK818_NEW_FCC_REG2 0xe7
269 #define RK818_NEW_FCC_REG1 0xe8
270 #define RK818_NEW_FCC_REG0 0xe9
271 #define RK818_NON_ACT_TIMER_CNT_SAVE_REG 0xea
272 #define RK818_OCV_VOL_VALID_REG 0xeb
273 #define RK818_REBOOT_CNT_REG 0xec
274 #define RK818_POFFSET_REG 0xed
275 #define RK818_MISC_MARK_REG 0xee
276 #define RK818_HALT_CNT_REG 0xef
277 #define RK818_CALC_REST_REGH 0xf0
278 #define RK818_CALC_REST_REGL 0xf1
279 #define RK818_SAVE_DATA19 0xf2
280 #define RK818_NUM_REGULATORS 17
282 /* IRQ Definitions */
283 #define RK808_IRQ_VOUT_LO 0
284 #define RK808_IRQ_VB_LO 1
285 #define RK808_IRQ_PWRON 2
286 #define RK808_IRQ_PWRON_LP 3
287 #define RK808_IRQ_HOTDIE 4
288 #define RK808_IRQ_RTC_ALARM 5
289 #define RK808_IRQ_RTC_PERIOD 6
290 #define RK808_IRQ_PLUG_IN_INT 7
291 #define RK808_IRQ_PLUG_OUT_INT 8
292 #define RK808_NUM_IRQ 9
294 #define RK808_IRQ_VOUT_LO_MSK BIT(0)
295 #define RK808_IRQ_VB_LO_MSK BIT(1)
296 #define RK808_IRQ_PWRON_MSK BIT(2)
297 #define RK808_IRQ_PWRON_LP_MSK BIT(3)
298 #define RK808_IRQ_HOTDIE_MSK BIT(4)
299 #define RK808_IRQ_RTC_ALARM_MSK BIT(5)
300 #define RK808_IRQ_RTC_PERIOD_MSK BIT(6)
301 #define RK808_IRQ_PLUG_IN_INT_MSK BIT(0)
302 #define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1)
304 #define RK808_VBAT_LOW_2V8 0x00
305 #define RK808_VBAT_LOW_2V9 0x01
306 #define RK808_VBAT_LOW_3V0 0x02
307 #define RK808_VBAT_LOW_3V1 0x03
308 #define RK808_VBAT_LOW_3V2 0x04
309 #define RK808_VBAT_LOW_3V3 0x05
310 #define RK808_VBAT_LOW_3V4 0x06
311 #define RK808_VBAT_LOW_3V5 0x07
312 #define VBAT_LOW_VOL_MASK (0x07 << 0)
313 #define EN_VABT_LOW_SHUT_DOWN (0x00 << 4)
314 #define EN_VBAT_LOW_IRQ (0x1 << 4)
315 #define VBAT_LOW_ACT_MASK (0x1 << 4)
317 #define BUCK_ILMIN_MASK (7 << 0)
318 #define BOOST_ILMIN_MASK (7 << 0)
319 #define BUCK1_RATE_MASK (3 << 3)
320 #define BUCK2_RATE_MASK (3 << 3)
321 #define MASK_ALL 0xff
323 #define BUCK_UV_ACT_MASK 0x0f
324 #define BUCK_UV_ACT_DISABLE 0
326 #define SWITCH2_EN BIT(6)
327 #define SWITCH1_EN BIT(5)
328 #define DEV_OFF_RST BIT(3)
329 #define DEV_OFF BIT(0)
331 #define VB_LO_ACT BIT(4)
332 #define VB_LO_SEL_3500MV (7 << 0)
334 #define VOUT_LO_INT BIT(0)
335 #define CLK32KOUT2_EN BIT(0)
336 #define H5V_EN_MASK BIT(0)
337 #define H5V_EN_ENABLE BIT(0)
338 #define REF_RDY_CTRL_MASK BIT(1)
339 #define REF_RDY_CTRL_ENABLE BIT(1)
341 /*RK818_DCDC_EN_REG*/
342 #define BUCK1_EN_MASK BIT(0)
343 #define BUCK2_EN_MASK BIT(1)
344 #define BUCK3_EN_MASK BIT(2)
345 #define BUCK4_EN_MASK BIT(3)
346 #define BOOST_EN_MASK BIT(4)
347 #define LDO9_EN_MASK BIT(5)
348 #define SWITCH_EN_MASK BIT(6)
349 #define OTG_EN_MASK BIT(7)
351 #define BUCK1_EN_ENABLE BIT(0)
352 #define BUCK2_EN_ENABLE BIT(1)
353 #define BUCK3_EN_ENABLE BIT(2)
354 #define BUCK4_EN_ENABLE BIT(3)
355 #define BOOST_EN_ENABLE BIT(4)
356 #define LDO9_EN_ENABLE BIT(5)
357 #define SWITCH_EN_ENABLE BIT(6)
358 #define OTG_EN_ENABLE BIT(7)
360 /* IRQ Definitions */
361 #define RK818_IRQ_VOUT_LO 0
362 #define RK818_IRQ_VB_LO 1
363 #define RK818_IRQ_PWRON 2
364 #define RK818_IRQ_PWRON_LP 3
365 #define RK818_IRQ_HOTDIE 4
366 #define RK818_IRQ_RTC_ALARM 5
367 #define RK818_IRQ_RTC_PERIOD 6
368 #define RK818_IRQ_USB_OV 7
369 #define RK818_IRQ_PLUG_IN 8
370 #define RK818_IRQ_PLUG_OUT 9
371 #define RK818_IRQ_CHG_OK 10
372 #define RK818_IRQ_CHG_TE 11
373 #define RK818_IRQ_CHG_TS1 12
374 #define RK818_IRQ_TS2 13
375 #define RK818_IRQ_CHG_CVTLIM 14
376 #define RK818_IRQ_DISCHG_ILIM 15
378 #define BUCK1_SLP_SET_MASK BIT(0)
379 #define BUCK2_SLP_SET_MASK BIT(1)
380 #define BUCK3_SLP_SET_MASK BIT(2)
381 #define BUCK4_SLP_SET_MASK BIT(3)
382 #define BOOST_SLP_SET_MASK BIT(4)
383 #define LDO9_SLP_SET_MASK BIT(5)
384 #define SWITCH_SLP_SET_MASK BIT(6)
385 #define OTG_SLP_SET_MASK BIT(7)
387 #define BUCK1_SLP_SET_OFF BIT(0)
388 #define BUCK2_SLP_SET_OFF BIT(1)
389 #define BUCK3_SLP_SET_OFF BIT(2)
390 #define BUCK4_SLP_SET_OFF BIT(3)
391 #define BOOST_SLP_SET_OFF BIT(4)
392 #define LDO9_SLP_SET_OFF BIT(5)
393 #define SWITCH_SLP_SET_OFF BIT(6)
394 #define OTG_SLP_SET_OFF BIT(7)
395 #define OTG_BOOST_SLP_OFF (BOOST_SLP_SET_OFF | OTG_SLP_SET_OFF)
397 #define BUCK1_SLP_SET_ON BIT(0)
398 #define BUCK2_SLP_SET_ON BIT(1)
399 #define BUCK3_SLP_SET_ON BIT(2)
400 #define BUCK4_SLP_SET_ON BIT(3)
401 #define BOOST_SLP_SET_ON BIT(4)
402 #define LDO9_SLP_SET_ON BIT(5)
403 #define SWITCH_SLP_SET_ON BIT(6)
404 #define OTG_SLP_SET_ON BIT(7)
406 #define VOUT_LO_MASK BIT(0)
407 #define VB_LO_MASK BIT(1)
408 #define PWRON_MASK BIT(2)
409 #define PWRON_LP_MASK BIT(3)
410 #define HOTDIE_MASK BIT(4)
411 #define RTC_ALARM_MASK BIT(5)
412 #define RTC_PERIOD_MASK BIT(6)
413 #define USB_OV_MASK BIT(7)
415 #define VOUT_LO_DISABLE BIT(0)
416 #define VB_LO_DISABLE BIT(1)
417 #define PWRON_DISABLE BIT(2)
418 #define PWRON_LP_DISABLE BIT(3)
419 #define HOTDIE_DISABLE BIT(4)
420 #define RTC_ALARM_DISABLE BIT(5)
421 #define RTC_PERIOD_DISABLE BIT(6)
422 #define USB_OV_INT_DISABLE BIT(7)
424 #define VOUT_LO_ENABLE (0 << 0)
425 #define VB_LO_ENABLE (0 << 1)
426 #define PWRON_ENABLE (0 << 2)
427 #define PWRON_LP_ENABLE (0 << 3)
428 #define HOTDIE_ENABLE (0 << 4)
429 #define RTC_ALARM_ENABLE (0 << 5)
430 #define RTC_PERIOD_ENABLE (0 << 6)
431 #define USB_OV_INT_ENABLE (0 << 7)
433 #define PLUG_IN_MASK BIT(0)
434 #define PLUG_OUT_MASK BIT(1)
435 #define CHGOK_MASK BIT(2)
436 #define CHGTE_MASK BIT(3)
437 #define CHGTS1_MASK BIT(4)
438 #define TS2_MASK BIT(5)
439 #define CHG_CVTLIM_MASK BIT(6)
440 #define DISCHG_ILIM_MASK BIT(7)
442 #define PLUG_IN_DISABLE BIT(0)
443 #define PLUG_OUT_DISABLE BIT(1)
444 #define CHGOK_DISABLE BIT(2)
445 #define CHGTE_DISABLE BIT(3)
446 #define CHGTS1_DISABLE BIT(4)
447 #define TS2_DISABLE BIT(5)
448 #define CHG_CVTLIM_DISABLE BIT(6)
449 #define DISCHG_ILIM_DISABLE BIT(7)
451 #define PLUG_IN_ENABLE BIT(0)
452 #define PLUG_OUT_ENABLE BIT(1)
453 #define CHGOK_ENABLE BIT(2)
454 #define CHGTE_ENABLE BIT(3)
455 #define CHGTS1_ENABLE BIT(4)
456 #define TS2_ENABLE BIT(5)
457 #define CHG_CVTLIM_ENABLE BIT(6)
458 #define DISCHG_ILIM_ENABLE BIT(7)
460 /* IRQ Definitions */
461 #define RK805_IRQ_PWRON_RISE 0
462 #define RK805_IRQ_VB_LOW 1
463 #define RK805_IRQ_PWRON 2
464 #define RK805_IRQ_PWRON_LP 3
465 #define RK805_IRQ_HOTDIE 4
466 #define RK805_IRQ_RTC_ALARM 5
467 #define RK805_IRQ_RTC_PERIOD 6
468 #define RK805_IRQ_PWRON_FALL 7
470 #define RK805_IRQ_PWRON_RISE_MSK BIT(0)
471 #define RK805_IRQ_VB_LOW_MSK BIT(1)
472 #define RK805_IRQ_PWRON_MSK BIT(2)
473 #define RK805_IRQ_PWRON_LP_MSK BIT(3)
474 #define RK805_IRQ_HOTDIE_MSK BIT(4)
475 #define RK805_IRQ_RTC_ALARM_MSK BIT(5)
476 #define RK805_IRQ_RTC_PERIOD_MSK BIT(6)
477 #define RK805_IRQ_PWRON_FALL_MSK BIT(7)
479 #define RK805_PWR_RISE_INT_STATUS BIT(0)
480 #define RK805_VB_LOW_INT_STATUS BIT(1)
481 #define RK805_PWRON_INT_STATUS BIT(2)
482 #define RK805_PWRON_LP_INT_STATUS BIT(3)
483 #define RK805_HOTDIE_INT_STATUS BIT(4)
484 #define RK805_ALARM_INT_STATUS BIT(5)
485 #define RK805_PERIOD_INT_STATUS BIT(6)
486 #define RK805_PWR_FALL_INT_STATUS BIT(7)
488 /*INTERRUPT REGISTER*/
489 #define RK805_INT_STS_REG 0x4C
490 #define RK805_INT_STS_MSK_REG 0x4D
491 #define RK805_GPIO_IO_POL_REG 0x50
492 #define RK805_OUT_REG 0x52
493 #define RK805_ON_SOURCE_REG 0xAE
494 #define RK805_OFF_SOURCE_REG 0xAF
496 /*POWER CHANNELS ENABLE REGISTER*/
497 #define RK805_DCDC_EN_REG 0x23
498 #define RK805_SLP_DCDC_EN_REG 0x25
499 #define RK805_SLP_LDO_EN_REG 0x26
500 #define RK805_LDO_EN_REG 0x27
503 #define RK805_THERMAL_REG 0x22
505 /*BUCK AND LDO CONFIG REGISTER*/
506 #define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A
507 #define RK805_BUCK1_CONFIG_REG 0x2E
508 #define RK805_BUCK1_ON_VSEL_REG 0x2F
509 #define RK805_BUCK1_SLP_VSEL_REG 0x30
510 #define RK805_BUCK2_CONFIG_REG 0x32
511 #define RK805_BUCK2_ON_VSEL_REG 0x33
512 #define RK805_BUCK2_SLP_VSEL_REG 0x34
513 #define RK805_BUCK3_CONFIG_REG 0x36
514 #define RK805_BUCK4_CONFIG_REG 0x37
515 #define RK805_BUCK4_ON_VSEL_REG 0x38
516 #define RK805_BUCK4_SLP_VSEL_REG 0x39
517 #define RK805_LDO1_ON_VSEL_REG 0x3B
518 #define RK805_LDO1_SLP_VSEL_REG 0x3C
519 #define RK805_LDO2_ON_VSEL_REG 0x3D
520 #define RK805_LDO2_SLP_VSEL_REG 0x3E
521 #define RK805_LDO3_ON_VSEL_REG 0x3F
522 #define RK805_LDO3_SLP_VSEL_REG 0x40
523 #define RK805_OUT_REG 0x52
524 #define RK805_ON_SOURCE_REG 0xAE
525 #define RK805_OFF_SOURCE_REG 0xAF
527 #define RK805_NUM_REGULATORS 7
529 #define RK805_PWRON_FALL_RISE_INT_EN 0x0
530 #define RK805_PWRON_FALL_RISE_INT_MSK 0x81
532 #define TEMP115C 0x0c
533 #define TEMP_HOTDIE_MSK 0x0c
534 #define SLP_SD_MSK (0x3 << 2)
535 #define SHUTDOWN_FUN (0x2 << 2)
536 #define SLEEP_FUN (0x1 << 2)
537 #define RK8XX_ID_MSK 0xfff0
538 #define FPWM_MODE BIT(7)
563 struct i2c_client *i2c;
564 struct regmap_irq_chip_data *irq_data;
565 struct regmap *regmap;
575 #endif /* __LINUX_REGULATOR_rk808_H */