2 * rk808.h for Rockchip RK808
4 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
6 * Author: Chris Zhong <zyw@rock-chips.com>
7 * Author: Zhang Qing <zhangqing@rock-chips.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 #ifndef __LINUX_REGULATOR_rk808_H
20 #define __LINUX_REGULATOR_rk808_H
22 #include <linux/regulator/machine.h>
23 #include <linux/regmap.h>
26 * rk808 Global Register Map.
29 #define RK808_DCDC1 0 /* (0+RK808_START) */
30 #define RK808_LDO1 4 /* (4+RK808_START) */
31 #define RK808_NUM_REGULATORS 14
77 #define RK808_SECONDS_REG 0x00
78 #define RK808_MINUTES_REG 0x01
79 #define RK808_HOURS_REG 0x02
80 #define RK808_DAYS_REG 0x03
81 #define RK808_MONTHS_REG 0x04
82 #define RK808_YEARS_REG 0x05
83 #define RK808_WEEKS_REG 0x06
84 #define RK808_ALARM_SECONDS_REG 0x08
85 #define RK808_ALARM_MINUTES_REG 0x09
86 #define RK808_ALARM_HOURS_REG 0x0a
87 #define RK808_ALARM_DAYS_REG 0x0b
88 #define RK808_ALARM_MONTHS_REG 0x0c
89 #define RK808_ALARM_YEARS_REG 0x0d
90 #define RK808_RTC_CTRL_REG 0x10
91 #define RK808_RTC_STATUS_REG 0x11
92 #define RK808_RTC_INT_REG 0x12
93 #define RK808_RTC_COMP_LSB_REG 0x13
94 #define RK808_RTC_COMP_MSB_REG 0x14
95 #define RK808_ID_MSB 0x17
96 #define RK808_ID_LSB 0x18
97 #define RK808_CLK32OUT_REG 0x20
98 #define RK808_VB_MON_REG 0x21
99 #define RK808_THERMAL_REG 0x22
100 #define RK808_DCDC_EN_REG 0x23
101 #define RK808_LDO_EN_REG 0x24
102 #define RK808_SLEEP_SET_OFF_REG1 0x25
103 #define RK808_SLEEP_SET_OFF_REG2 0x26
104 #define RK808_DCDC_UV_STS_REG 0x27
105 #define RK808_DCDC_UV_ACT_REG 0x28
106 #define RK808_LDO_UV_STS_REG 0x29
107 #define RK808_LDO_UV_ACT_REG 0x2a
108 #define RK808_DCDC_PG_REG 0x2b
109 #define RK808_LDO_PG_REG 0x2c
110 #define RK808_VOUT_MON_TDB_REG 0x2d
111 #define RK808_BUCK1_CONFIG_REG 0x2e
112 #define RK808_BUCK1_ON_VSEL_REG 0x2f
113 #define RK808_BUCK1_SLP_VSEL_REG 0x30
114 #define RK808_BUCK1_DVS_VSEL_REG 0x31
115 #define RK808_BUCK2_CONFIG_REG 0x32
116 #define RK808_BUCK2_ON_VSEL_REG 0x33
117 #define RK808_BUCK2_SLP_VSEL_REG 0x34
118 #define RK808_BUCK2_DVS_VSEL_REG 0x35
119 #define RK808_BUCK3_CONFIG_REG 0x36
120 #define RK808_BUCK4_CONFIG_REG 0x37
121 #define RK808_BUCK4_ON_VSEL_REG 0x38
122 #define RK808_BUCK4_SLP_VSEL_REG 0x39
123 #define RK808_BOOST_CONFIG_REG 0x3a
124 #define RK808_LDO1_ON_VSEL_REG 0x3b
125 #define RK808_LDO1_SLP_VSEL_REG 0x3c
126 #define RK808_LDO2_ON_VSEL_REG 0x3d
127 #define RK808_LDO2_SLP_VSEL_REG 0x3e
128 #define RK808_LDO3_ON_VSEL_REG 0x3f
129 #define RK808_LDO3_SLP_VSEL_REG 0x40
130 #define RK808_LDO4_ON_VSEL_REG 0x41
131 #define RK808_LDO4_SLP_VSEL_REG 0x42
132 #define RK808_LDO5_ON_VSEL_REG 0x43
133 #define RK808_LDO5_SLP_VSEL_REG 0x44
134 #define RK808_LDO6_ON_VSEL_REG 0x45
135 #define RK808_LDO6_SLP_VSEL_REG 0x46
136 #define RK808_LDO7_ON_VSEL_REG 0x47
137 #define RK808_LDO7_SLP_VSEL_REG 0x48
138 #define RK808_LDO8_ON_VSEL_REG 0x49
139 #define RK808_LDO8_SLP_VSEL_REG 0x4a
140 #define RK808_DEVCTRL_REG 0x4b
141 #define RK808_INT_STS_REG1 0x4c
142 #define RK808_INT_STS_MSK_REG1 0x4d
143 #define RK808_INT_STS_REG2 0x4e
144 #define RK808_INT_STS_MSK_REG2 0x4f
145 #define RK808_IO_POL_REG 0x50
147 #define RK818_VB_MON_REG 0x21
148 #define RK818_THERMAL_REG 0x22
149 #define RK818_DCDC_EN_REG 0x23
150 #define RK818_LDO_EN_REG 0x24
151 #define RK818_SLEEP_SET_OFF_REG1 0x25
152 #define RK818_SLEEP_SET_OFF_REG2 0x26
153 #define RK818_DCDC_UV_STS_REG 0x27
154 #define RK818_DCDC_UV_ACT_REG 0x28
155 #define RK818_LDO_UV_STS_REG 0x29
156 #define RK818_LDO_UV_ACT_REG 0x2a
157 #define RK818_DCDC_PG_REG 0x2b
158 #define RK818_LDO_PG_REG 0x2c
159 #define RK818_VOUT_MON_TDB_REG 0x2d
160 #define RK818_BUCK1_CONFIG_REG 0x2e
161 #define RK818_BUCK1_ON_VSEL_REG 0x2f
162 #define RK818_BUCK1_SLP_VSEL_REG 0x30
163 #define RK818_BUCK2_CONFIG_REG 0x32
164 #define RK818_BUCK2_ON_VSEL_REG 0x33
165 #define RK818_BUCK2_SLP_VSEL_REG 0x34
166 #define RK818_BUCK3_CONFIG_REG 0x36
167 #define RK818_BUCK4_CONFIG_REG 0x37
168 #define RK818_BUCK4_ON_VSEL_REG 0x38
169 #define RK818_BUCK4_SLP_VSEL_REG 0x39
170 #define RK818_BOOST_CONFIG_REG 0x3a
171 #define RK818_LDO1_ON_VSEL_REG 0x3b
172 #define RK818_LDO1_SLP_VSEL_REG 0x3c
173 #define RK818_LDO2_ON_VSEL_REG 0x3d
174 #define RK818_LDO2_SLP_VSEL_REG 0x3e
175 #define RK818_LDO3_ON_VSEL_REG 0x3f
176 #define RK818_LDO3_SLP_VSEL_REG 0x40
177 #define RK818_LDO4_ON_VSEL_REG 0x41
178 #define RK818_LDO4_SLP_VSEL_REG 0x42
179 #define RK818_LDO5_ON_VSEL_REG 0x43
180 #define RK818_LDO5_SLP_VSEL_REG 0x44
181 #define RK818_LDO6_ON_VSEL_REG 0x45
182 #define RK818_LDO6_SLP_VSEL_REG 0x46
183 #define RK818_LDO7_ON_VSEL_REG 0x47
184 #define RK818_LDO7_SLP_VSEL_REG 0x48
185 #define RK818_LDO8_ON_VSEL_REG 0x49
186 #define RK818_LDO8_SLP_VSEL_REG 0x4a
187 #define RK818_DEVCTRL_REG 0x4b
188 #define RK818_INT_STS_REG1 0X4c
189 #define RK818_INT_STS_MSK_REG1 0X4d
190 #define RK818_INT_STS_REG2 0X4e
191 #define RK818_INT_STS_MSK_REG2 0X4f
192 #define RK818_IO_POL_REG 0X50
193 #define RK818_OTP_VDD_EN_REG 0x51
194 #define RK818_H5V_EN_REG 0x52
195 #define RK818_SLEEP_SET_OFF_REG3 0x53
196 #define RK818_BOOST_LDO9_ON_VSEL_REG 0x54
197 #define RK818_BOOST_LDO9_SLP_VSEL_REG 0x55
198 #define RK818_BOOST_CTRL_REG 0x56
199 #define RK818_DCDC_ILMAX_REG 0x90
200 #define RK818_CHRG_COMP_REG 0x9a
201 #define RK818_SUP_STS_REG 0xa0
202 #define RK818_USB_CTRL_REG 0xa1
203 #define RK818_CHRG_CTRL_REG1 0xa3
204 #define RK818_CHRG_CTRL_REG2 0xa4
205 #define RK818_CHRG_CTRL_REG3 0xa5
206 #define RK818_BAT_CTRL_REG 0xa6
207 #define RK818_BAT_HTS_TS1_REG 0xa8
208 #define RK818_BAT_LTS_TS1_REG 0xa9
209 #define RK818_BAT_HTS_TS2_REG 0xaa
210 #define RK818_BAT_LTS_TS2_REG 0xab
211 #define RK818_TS_CTRL_REG 0xac
212 #define RK818_ADC_CTRL_REG 0xad
213 #define RK818_ON_SOURCE_REG 0xae
214 #define RK818_OFF_SOURCE_REG 0xaf
215 #define RK818_GGCON_REG 0xb0
216 #define RK818_GGSTS_REG 0xb1
217 #define RK818_FRAME_SMP_INTERV_REG 0xb2
218 #define RK818_AUTO_SLP_CUR_THR_REG 0xb3
219 #define RK818_GASCNT_CAL_REG3 0xb4
220 #define RK818_GASCNT_CAL_REG2 0xb5
221 #define RK818_GASCNT_CAL_REG1 0xb6
222 #define RK818_GASCNT_CAL_REG0 0xb7
223 #define RK818_GASCNT3_REG 0xb8
224 #define RK818_GASCNT2_REG 0xb9
225 #define RK818_GASCNT1_REG 0xba
226 #define RK818_GASCNT0_REG 0xbb
227 #define RK818_BAT_CUR_AVG_REGH 0xbc
228 #define RK818_BAT_CUR_AVG_REGL 0xbd
229 #define RK818_TS1_ADC_REGH 0xbe
230 #define RK818_TS1_ADC_REGL 0xbf
231 #define RK818_TS2_ADC_REGH 0xc0
232 #define RK818_TS2_ADC_REGL 0xc1
233 #define RK818_BAT_OCV_REGH 0xc2
234 #define RK818_BAT_OCV_REGL 0xc3
235 #define RK818_BAT_VOL_REGH 0xc4
236 #define RK818_BAT_VOL_REGL 0xc5
237 #define RK818_RELAX_ENTRY_THRES_REGH 0xc6
238 #define RK818_RELAX_ENTRY_THRES_REGL 0xc7
239 #define RK818_RELAX_EXIT_THRES_REGH 0xc8
240 #define RK818_RELAX_EXIT_THRES_REGL 0xc9
241 #define RK818_RELAX_VOL1_REGH 0xca
242 #define RK818_RELAX_VOL1_REGL 0xcb
243 #define RK818_RELAX_VOL2_REGH 0xcc
244 #define RK818_RELAX_VOL2_REGL 0xcd
245 #define RK818_BAT_CUR_R_CALC_REGH 0xce
246 #define RK818_BAT_CUR_R_CALC_REGL 0xcf
247 #define RK818_BAT_VOL_R_CALC_REGH 0xd0
248 #define RK818_BAT_VOL_R_CALC_REGL 0xd1
249 #define RK818_CAL_OFFSET_REGH 0xd2
250 #define RK818_CAL_OFFSET_REGL 0xd3
251 #define RK818_NON_ACT_TIMER_CNT_REG 0xd4
252 #define RK818_VCALIB0_REGH 0xd5
253 #define RK818_VCALIB0_REGL 0xd6
254 #define RK818_VCALIB1_REGH 0xd7
255 #define RK818_VCALIB1_REGL 0xd8
256 #define RK818_IOFFSET_REGH 0xdd
257 #define RK818_IOFFSET_REGL 0xde
258 #define RK818_SOC_REG 0xe0
259 #define RK818_REMAIN_CAP_REG3 0xe1
260 #define RK818_REMAIN_CAP_REG2 0xe2
261 #define RK818_REMAIN_CAP_REG1 0xe3
262 #define RK818_REMAIN_CAP_REG0 0xe4
263 #define RK818_UPDAT_LEVE_REG 0xe5
264 #define RK818_NEW_FCC_REG3 0xe6
265 #define RK818_NEW_FCC_REG2 0xe7
266 #define RK818_NEW_FCC_REG1 0xe8
267 #define RK818_NEW_FCC_REG0 0xe9
268 #define RK818_NON_ACT_TIMER_CNT_SAVE_REG 0xea
269 #define RK818_OCV_VOL_VALID_REG 0xeb
270 #define RK818_REBOOT_CNT_REG 0xec
271 #define RK818_POFFSET_REG 0xed
272 #define RK818_MISC_MARK_REG 0xee
273 #define RK818_HALT_CNT_REG 0xef
274 #define RK818_CALC_REST_REGH 0xf0
275 #define RK818_CALC_REST_REGL 0xf1
276 #define RK818_SAVE_DATA19 0xf2
277 #define RK818_NUM_REGULATORS 14
279 /* IRQ Definitions */
280 #define RK808_IRQ_VOUT_LO 0
281 #define RK808_IRQ_VB_LO 1
282 #define RK808_IRQ_PWRON 2
283 #define RK808_IRQ_PWRON_LP 3
284 #define RK808_IRQ_HOTDIE 4
285 #define RK808_IRQ_RTC_ALARM 5
286 #define RK808_IRQ_RTC_PERIOD 6
287 #define RK808_IRQ_PLUG_IN_INT 7
288 #define RK808_IRQ_PLUG_OUT_INT 8
289 #define RK808_NUM_IRQ 9
291 #define RK808_IRQ_VOUT_LO_MSK BIT(0)
292 #define RK808_IRQ_VB_LO_MSK BIT(1)
293 #define RK808_IRQ_PWRON_MSK BIT(2)
294 #define RK808_IRQ_PWRON_LP_MSK BIT(3)
295 #define RK808_IRQ_HOTDIE_MSK BIT(4)
296 #define RK808_IRQ_RTC_ALARM_MSK BIT(5)
297 #define RK808_IRQ_RTC_PERIOD_MSK BIT(6)
298 #define RK808_IRQ_PLUG_IN_INT_MSK BIT(0)
299 #define RK808_IRQ_PLUG_OUT_INT_MSK BIT(1)
301 #define RK808_VBAT_LOW_2V8 0x00
302 #define RK808_VBAT_LOW_2V9 0x01
303 #define RK808_VBAT_LOW_3V0 0x02
304 #define RK808_VBAT_LOW_3V1 0x03
305 #define RK808_VBAT_LOW_3V2 0x04
306 #define RK808_VBAT_LOW_3V3 0x05
307 #define RK808_VBAT_LOW_3V4 0x06
308 #define RK808_VBAT_LOW_3V5 0x07
309 #define VBAT_LOW_VOL_MASK (0x07 << 0)
310 #define EN_VABT_LOW_SHUT_DOWN (0x00 << 4)
311 #define EN_VBAT_LOW_IRQ (0x1 << 4)
312 #define VBAT_LOW_ACT_MASK (0x1 << 4)
314 #define BUCK_ILMIN_MASK (7 << 0)
315 #define BOOST_ILMIN_MASK (7 << 0)
316 #define BUCK1_RATE_MASK (3 << 3)
317 #define BUCK2_RATE_MASK (3 << 3)
318 #define MASK_ALL 0xff
320 #define BUCK_UV_ACT_MASK 0x0f
321 #define BUCK_UV_ACT_DISABLE 0
323 #define SWITCH2_EN BIT(6)
324 #define SWITCH1_EN BIT(5)
325 #define DEV_OFF_RST BIT(3)
326 #define DEV_OFF BIT(0)
328 #define VB_LO_ACT BIT(4)
329 #define VB_LO_SEL_3500MV (7 << 0)
331 #define VOUT_LO_INT BIT(0)
332 #define CLK32KOUT2_EN BIT(0)
333 #define H5V_EN_MASK BIT(0)
334 #define H5V_EN_ENABLE BIT(0)
335 #define REF_RDY_CTRL_MASK BIT(1)
336 #define REF_RDY_CTRL_ENABLE BIT(1)
338 /*RK818_DCDC_EN_REG*/
339 #define BUCK1_EN_MASK BIT(0)
340 #define BUCK2_EN_MASK BIT(1)
341 #define BUCK3_EN_MASK BIT(2)
342 #define BUCK4_EN_MASK BIT(3)
343 #define BOOST_EN_MASK BIT(4)
344 #define LDO9_EN_MASK BIT(5)
345 #define SWITCH_EN_MASK BIT(6)
346 #define OTG_EN_MASK BIT(7)
348 #define BUCK1_EN_ENABLE BIT(0)
349 #define BUCK2_EN_ENABLE BIT(1)
350 #define BUCK3_EN_ENABLE BIT(2)
351 #define BUCK4_EN_ENABLE BIT(3)
352 #define BOOST_EN_ENABLE BIT(4)
353 #define LDO9_EN_ENABLE BIT(5)
354 #define SWITCH_EN_ENABLE BIT(6)
355 #define OTG_EN_ENABLE BIT(7)
357 /* IRQ Definitions */
358 #define RK818_IRQ_VOUT_LO 0
359 #define RK818_IRQ_VB_LO 1
360 #define RK818_IRQ_PWRON 2
361 #define RK818_IRQ_PWRON_LP 3
362 #define RK818_IRQ_HOTDIE 4
363 #define RK818_IRQ_RTC_ALARM 5
364 #define RK818_IRQ_RTC_PERIOD 6
365 #define RK818_IRQ_USB_OV 7
366 #define RK818_IRQ_PLUG_IN 8
367 #define RK818_IRQ_PLUG_OUT 9
368 #define RK818_IRQ_CHG_OK 10
369 #define RK818_IRQ_CHG_TE 11
370 #define RK818_IRQ_CHG_TS1 12
371 #define RK818_IRQ_TS2 13
372 #define RK818_IRQ_CHG_CVTLIM 14
373 #define RK818_IRQ_DISCHG_ILIM 15
375 #define BUCK1_SLP_SET_MASK BIT(0)
376 #define BUCK2_SLP_SET_MASK BIT(1)
377 #define BUCK3_SLP_SET_MASK BIT(2)
378 #define BUCK4_SLP_SET_MASK BIT(3)
379 #define BOOST_SLP_SET_MASK BIT(4)
380 #define LDO9_SLP_SET_MASK BIT(5)
381 #define SWITCH_SLP_SET_MASK BIT(6)
382 #define OTG_SLP_SET_MASK BIT(7)
384 #define BUCK1_SLP_SET_OFF BIT(0)
385 #define BUCK2_SLP_SET_OFF BIT(1)
386 #define BUCK3_SLP_SET_OFF BIT(2)
387 #define BUCK4_SLP_SET_OFF BIT(3)
388 #define BOOST_SLP_SET_OFF BIT(4)
389 #define LDO9_SLP_SET_OFF BIT(5)
390 #define SWITCH_SLP_SET_OFF BIT(6)
391 #define OTG_SLP_SET_OFF BIT(7)
392 #define OTG_BOOST_SLP_OFF (BOOST_SLP_SET_OFF | OTG_SLP_SET_OFF)
394 #define BUCK1_SLP_SET_ON BIT(0)
395 #define BUCK2_SLP_SET_ON BIT(1)
396 #define BUCK3_SLP_SET_ON BIT(2)
397 #define BUCK4_SLP_SET_ON BIT(3)
398 #define BOOST_SLP_SET_ON BIT(4)
399 #define LDO9_SLP_SET_ON BIT(5)
400 #define SWITCH_SLP_SET_ON BIT(6)
401 #define OTG_SLP_SET_ON BIT(7)
403 #define VOUT_LO_MASK BIT(0)
404 #define VB_LO_MASK BIT(1)
405 #define PWRON_MASK BIT(2)
406 #define PWRON_LP_MASK BIT(3)
407 #define HOTDIE_MASK BIT(4)
408 #define RTC_ALARM_MASK BIT(5)
409 #define RTC_PERIOD_MASK BIT(6)
410 #define USB_OV_MASK BIT(7)
412 #define VOUT_LO_DISABLE BIT(0)
413 #define VB_LO_DISABLE BIT(1)
414 #define PWRON_DISABLE BIT(2)
415 #define PWRON_LP_DISABLE BIT(3)
416 #define HOTDIE_DISABLE BIT(4)
417 #define RTC_ALARM_DISABLE BIT(5)
418 #define RTC_PERIOD_DISABLE BIT(6)
419 #define USB_OV_INT_DISABLE BIT(7)
421 #define VOUT_LO_ENABLE (0 << 0)
422 #define VB_LO_ENABLE (0 << 1)
423 #define PWRON_ENABLE (0 << 2)
424 #define PWRON_LP_ENABLE (0 << 3)
425 #define HOTDIE_ENABLE (0 << 4)
426 #define RTC_ALARM_ENABLE (0 << 5)
427 #define RTC_PERIOD_ENABLE (0 << 6)
428 #define USB_OV_INT_ENABLE (0 << 7)
430 #define PLUG_IN_MASK BIT(0)
431 #define PLUG_OUT_MASK BIT(1)
432 #define CHGOK_MASK BIT(2)
433 #define CHGTE_MASK BIT(3)
434 #define CHGTS1_MASK BIT(4)
435 #define TS2_MASK BIT(5)
436 #define CHG_CVTLIM_MASK BIT(6)
437 #define DISCHG_ILIM_MASK BIT(7)
439 #define PLUG_IN_DISABLE BIT(0)
440 #define PLUG_OUT_DISABLE BIT(1)
441 #define CHGOK_DISABLE BIT(2)
442 #define CHGTE_DISABLE BIT(3)
443 #define CHGTS1_DISABLE BIT(4)
444 #define TS2_DISABLE BIT(5)
445 #define CHG_CVTLIM_DISABLE BIT(6)
446 #define DISCHG_ILIM_DISABLE BIT(7)
448 #define PLUG_IN_ENABLE BIT(0)
449 #define PLUG_OUT_ENABLE BIT(1)
450 #define CHGOK_ENABLE BIT(2)
451 #define CHGTE_ENABLE BIT(3)
452 #define CHGTS1_ENABLE BIT(4)
453 #define TS2_ENABLE BIT(5)
454 #define CHG_CVTLIM_ENABLE BIT(6)
455 #define DISCHG_ILIM_ENABLE BIT(7)
457 /* IRQ Definitions */
458 #define RK805_IRQ_PWRON_RISE 0
459 #define RK805_IRQ_VB_LOW 1
460 #define RK805_IRQ_PWRON 2
461 #define RK805_IRQ_PWRON_LP 3
462 #define RK805_IRQ_HOTDIE 4
463 #define RK805_IRQ_RTC_ALARM 5
464 #define RK805_IRQ_RTC_PERIOD 6
465 #define RK805_IRQ_PWRON_FALL 7
467 #define RK805_IRQ_PWRON_RISE_MSK BIT(0)
468 #define RK805_IRQ_VB_LOW_MSK BIT(1)
469 #define RK805_IRQ_PWRON_MSK BIT(2)
470 #define RK805_IRQ_PWRON_LP_MSK BIT(3)
471 #define RK805_IRQ_HOTDIE_MSK BIT(4)
472 #define RK805_IRQ_RTC_ALARM_MSK BIT(5)
473 #define RK805_IRQ_RTC_PERIOD_MSK BIT(6)
474 #define RK805_IRQ_PWRON_FALL_MSK BIT(7)
476 #define RK805_PWR_RISE_INT_STATUS BIT(0)
477 #define RK805_VB_LOW_INT_STATUS BIT(1)
478 #define RK805_PWRON_INT_STATUS BIT(2)
479 #define RK805_PWRON_LP_INT_STATUS BIT(3)
480 #define RK805_HOTDIE_INT_STATUS BIT(4)
481 #define RK805_ALARM_INT_STATUS BIT(5)
482 #define RK805_PERIOD_INT_STATUS BIT(6)
483 #define RK805_PWR_FALL_INT_STATUS BIT(7)
485 /*INTERRUPT REGISTER*/
486 #define RK805_INT_STS_REG 0x4C
487 #define RK805_INT_STS_MSK_REG 0x4D
488 #define RK805_GPIO_IO_POL_REG 0x50
489 #define RK805_OUT_REG 0x52
490 #define RK805_ON_SOURCE_REG 0xAE
491 #define RK805_OFF_SOURCE_REG 0xAF
493 /*POWER CHANNELS ENABLE REGISTER*/
494 #define RK805_DCDC_EN_REG 0x23
495 #define RK805_SLP_DCDC_EN_REG 0x25
496 #define RK805_SLP_LDO_EN_REG 0x26
497 #define RK805_LDO_EN_REG 0x27
500 #define RK805_THERMAL_REG 0x22
502 /*BUCK AND LDO CONFIG REGISTER*/
503 #define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A
504 #define RK805_BUCK1_CONFIG_REG 0x2E
505 #define RK805_BUCK1_ON_VSEL_REG 0x2F
506 #define RK805_BUCK1_SLP_VSEL_REG 0x30
507 #define RK805_BUCK2_CONFIG_REG 0x32
508 #define RK805_BUCK2_ON_VSEL_REG 0x33
509 #define RK805_BUCK2_SLP_VSEL_REG 0x34
510 #define RK805_BUCK3_CONFIG_REG 0x36
511 #define RK805_BUCK4_CONFIG_REG 0x37
512 #define RK805_BUCK4_ON_VSEL_REG 0x38
513 #define RK805_BUCK4_SLP_VSEL_REG 0x39
514 #define RK805_LDO1_ON_VSEL_REG 0x3B
515 #define RK805_LDO1_SLP_VSEL_REG 0x3C
516 #define RK805_LDO2_ON_VSEL_REG 0x3D
517 #define RK805_LDO2_SLP_VSEL_REG 0x3E
518 #define RK805_LDO3_ON_VSEL_REG 0x3F
519 #define RK805_LDO3_SLP_VSEL_REG 0x40
520 #define RK805_OUT_REG 0x52
521 #define RK805_ON_SOURCE_REG 0xAE
522 #define RK805_OFF_SOURCE_REG 0xAF
524 #define RK805_NUM_REGULATORS 7
526 #define RK805_PWRON_FALL_RISE_INT_EN 0x0
527 #define RK805_PWRON_FALL_RISE_INT_MSK 0x81
529 #define TEMP115C 0x0c
530 #define TEMP_HOTDIE_MSK 0x0c
531 #define SLP_SD_MSK (0x3 << 2)
532 #define SHUTDOWN_FUN (0x2 << 2)
533 #define SLEEP_FUN (0x1 << 2)
534 #define RK8XX_ID_MSK 0xfff0
535 #define FPWM_MODE BIT(7)
560 struct i2c_client *i2c;
561 struct regmap_irq_chip_data *irq_data;
562 struct regmap *regmap;
572 #endif /* __LINUX_REGULATOR_rk808_H */