2 * max77693-private.h - Voltage regulator driver for the Maxim 77693
4 * Copyright (C) 2012 Samsung Electrnoics
5 * SangYoung Son <hello.son@samsung.com>
7 * This program is not provided / owned by Maxim Integrated Products.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #ifndef __LINUX_MFD_MAX77693_PRIV_H
25 #define __LINUX_MFD_MAX77693_PRIV_H
27 #include <linux/i2c.h>
29 #define MAX77693_REG_INVALID (0xff)
31 /* Slave addr = 0xCC: PMIC, Charger, Flash LED */
32 enum max77693_pmic_reg {
33 MAX77693_LED_REG_IFLASH1 = 0x00,
34 MAX77693_LED_REG_IFLASH2 = 0x01,
35 MAX77693_LED_REG_ITORCH = 0x02,
36 MAX77693_LED_REG_ITORCHTIMER = 0x03,
37 MAX77693_LED_REG_FLASH_TIMER = 0x04,
38 MAX77693_LED_REG_FLASH_EN = 0x05,
39 MAX77693_LED_REG_MAX_FLASH1 = 0x06,
40 MAX77693_LED_REG_MAX_FLASH2 = 0x07,
41 MAX77693_LED_REG_MAX_FLASH3 = 0x08,
42 MAX77693_LED_REG_MAX_FLASH4 = 0x09,
43 MAX77693_LED_REG_VOUT_CNTL = 0x0A,
44 MAX77693_LED_REG_VOUT_FLASH1 = 0x0B,
45 MAX77693_LED_REG_VOUT_FLASH2 = 0x0C,
46 MAX77693_LED_REG_FLASH_INT = 0x0E,
47 MAX77693_LED_REG_FLASH_INT_MASK = 0x0F,
48 MAX77693_LED_REG_FLASH_STATUS = 0x10,
50 MAX77693_PMIC_REG_PMIC_ID1 = 0x20,
51 MAX77693_PMIC_REG_PMIC_ID2 = 0x21,
52 MAX77693_PMIC_REG_INTSRC = 0x22,
53 MAX77693_PMIC_REG_INTSRC_MASK = 0x23,
54 MAX77693_PMIC_REG_TOPSYS_INT = 0x24,
55 MAX77693_PMIC_REG_TOPSYS_INT_MASK = 0x26,
56 MAX77693_PMIC_REG_TOPSYS_STAT = 0x28,
57 MAX77693_PMIC_REG_MAINCTRL1 = 0x2A,
58 MAX77693_PMIC_REG_LSCNFG = 0x2B,
60 MAX77693_CHG_REG_CHG_INT = 0xB0,
61 MAX77693_CHG_REG_CHG_INT_MASK = 0xB1,
62 MAX77693_CHG_REG_CHG_INT_OK = 0xB2,
63 MAX77693_CHG_REG_CHG_DETAILS_00 = 0xB3,
64 MAX77693_CHG_REG_CHG_DETAILS_01 = 0xB4,
65 MAX77693_CHG_REG_CHG_DETAILS_02 = 0xB5,
66 MAX77693_CHG_REG_CHG_DETAILS_03 = 0xB6,
67 MAX77693_CHG_REG_CHG_CNFG_00 = 0xB7,
68 MAX77693_CHG_REG_CHG_CNFG_01 = 0xB8,
69 MAX77693_CHG_REG_CHG_CNFG_02 = 0xB9,
70 MAX77693_CHG_REG_CHG_CNFG_03 = 0xBA,
71 MAX77693_CHG_REG_CHG_CNFG_04 = 0xBB,
72 MAX77693_CHG_REG_CHG_CNFG_05 = 0xBC,
73 MAX77693_CHG_REG_CHG_CNFG_06 = 0xBD,
74 MAX77693_CHG_REG_CHG_CNFG_07 = 0xBE,
75 MAX77693_CHG_REG_CHG_CNFG_08 = 0xBF,
76 MAX77693_CHG_REG_CHG_CNFG_09 = 0xC0,
77 MAX77693_CHG_REG_CHG_CNFG_10 = 0xC1,
78 MAX77693_CHG_REG_CHG_CNFG_11 = 0xC2,
79 MAX77693_CHG_REG_CHG_CNFG_12 = 0xC3,
80 MAX77693_CHG_REG_CHG_CNFG_13 = 0xC4,
81 MAX77693_CHG_REG_CHG_CNFG_14 = 0xC5,
82 MAX77693_CHG_REG_SAFEOUT_CTRL = 0xC6,
84 MAX77693_PMIC_REG_END,
87 /* MAX77693 ITORCH register */
88 #define TORCH_IOUT1_SHIFT 0
89 #define TORCH_IOUT2_SHIFT 4
90 #define TORCH_IOUT_MIN 15625
91 #define TORCH_IOUT_MAX 250000
92 #define TORCH_IOUT_STEP 15625
94 /* MAX77693 IFLASH1 and IFLASH2 registers */
95 #define FLASH_IOUT_MIN 15625
96 #define FLASH_IOUT_MAX_1LED 1000000
97 #define FLASH_IOUT_MAX_2LEDS 625000
98 #define FLASH_IOUT_STEP 15625
100 /* MAX77693 TORCH_TIMER register */
101 #define TORCH_TMR_NO_TIMER 0x40
102 #define TORCH_TIMEOUT_MIN 262000
103 #define TORCH_TIMEOUT_MAX 15728000
105 /* MAX77693 FLASH_TIMER register */
106 #define FLASH_TMR_LEVEL 0x80
107 #define FLASH_TIMEOUT_MIN 62500
108 #define FLASH_TIMEOUT_MAX 1000000
109 #define FLASH_TIMEOUT_STEP 62500
111 /* MAX77693 FLASH_EN register */
112 #define FLASH_EN_OFF 0x0
113 #define FLASH_EN_FLASH 0x1
114 #define FLASH_EN_TORCH 0x2
115 #define FLASH_EN_ON 0x3
116 #define FLASH_EN_SHIFT(x) (6 - ((x) - 1) * 2)
117 #define TORCH_EN_SHIFT(x) (2 - ((x) - 1) * 2)
119 /* MAX77693 MAX_FLASH1 register */
120 #define MAX_FLASH1_MAX_FL_EN 0x80
121 #define MAX_FLASH1_VSYS_MIN 2400
122 #define MAX_FLASH1_VSYS_MAX 3400
123 #define MAX_FLASH1_VSYS_STEP 33
125 /* MAX77693 VOUT_CNTL register */
126 #define FLASH_BOOST_FIXED 0x04
127 #define FLASH_BOOST_LEDNUM_2 0x80
129 /* MAX77693 VOUT_FLASH1 register */
130 #define FLASH_VOUT_MIN 3300
131 #define FLASH_VOUT_MAX 5500
132 #define FLASH_VOUT_STEP 25
133 #define FLASH_VOUT_RMIN 0x0c
135 /* MAX77693 FLASH_STATUS register */
136 #define FLASH_STATUS_FLASH_ON BIT(3)
137 #define FLASH_STATUS_TORCH_ON BIT(2)
139 /* MAX77693 FLASH_INT register */
140 #define FLASH_INT_FLED2_OPEN BIT(0)
141 #define FLASH_INT_FLED2_SHORT BIT(1)
142 #define FLASH_INT_FLED1_OPEN BIT(2)
143 #define FLASH_INT_FLED1_SHORT BIT(3)
144 #define FLASH_INT_OVER_CURRENT BIT(4)
146 /* Fast charge timer in in hours */
147 #define DEFAULT_FAST_CHARGE_TIMER 4
149 #define DEFAULT_TOP_OFF_THRESHOLD_CURRENT 150000
151 #define DEFAULT_TOP_OFF_TIMER 30
153 #define DEFAULT_CONSTANT_VOLT 4200000
155 #define DEFAULT_MIN_SYSTEM_VOLT 3600000
157 #define DEFAULT_THERMAL_REGULATION_TEMP 100
159 #define DEFAULT_BATTERY_OVERCURRENT 3500000
161 #define DEFAULT_CHARGER_INPUT_THRESHOLD_VOLT 4300000
163 /* MAX77693_CHG_REG_CHG_INT_OK register */
164 #define CHG_INT_OK_BYP_SHIFT 0
165 #define CHG_INT_OK_BAT_SHIFT 3
166 #define CHG_INT_OK_CHG_SHIFT 4
167 #define CHG_INT_OK_CHGIN_SHIFT 6
168 #define CHG_INT_OK_DETBAT_SHIFT 7
169 #define CHG_INT_OK_BYP_MASK BIT(CHG_INT_OK_BYP_SHIFT)
170 #define CHG_INT_OK_BAT_MASK BIT(CHG_INT_OK_BAT_SHIFT)
171 #define CHG_INT_OK_CHG_MASK BIT(CHG_INT_OK_CHG_SHIFT)
172 #define CHG_INT_OK_CHGIN_MASK BIT(CHG_INT_OK_CHGIN_SHIFT)
173 #define CHG_INT_OK_DETBAT_MASK BIT(CHG_INT_OK_DETBAT_SHIFT)
175 /* MAX77693_CHG_REG_CHG_DETAILS_00 register */
176 #define CHG_DETAILS_00_CHGIN_SHIFT 5
177 #define CHG_DETAILS_00_CHGIN_MASK (0x3 << CHG_DETAILS_00_CHGIN_SHIFT)
179 /* MAX77693_CHG_REG_CHG_DETAILS_01 register */
180 #define CHG_DETAILS_01_CHG_SHIFT 0
181 #define CHG_DETAILS_01_BAT_SHIFT 4
182 #define CHG_DETAILS_01_TREG_SHIFT 7
183 #define CHG_DETAILS_01_CHG_MASK (0xf << CHG_DETAILS_01_CHG_SHIFT)
184 #define CHG_DETAILS_01_BAT_MASK (0x7 << CHG_DETAILS_01_BAT_SHIFT)
185 #define CHG_DETAILS_01_TREG_MASK BIT(7)
187 /* MAX77693_CHG_REG_CHG_DETAILS_01/CHG field */
188 enum max77693_charger_charging_state {
189 MAX77693_CHARGING_PREQUALIFICATION = 0x0,
190 MAX77693_CHARGING_FAST_CONST_CURRENT,
191 MAX77693_CHARGING_FAST_CONST_VOLTAGE,
192 MAX77693_CHARGING_TOP_OFF,
193 MAX77693_CHARGING_DONE,
194 MAX77693_CHARGING_HIGH_TEMP,
195 MAX77693_CHARGING_TIMER_EXPIRED,
196 MAX77693_CHARGING_THERMISTOR_SUSPEND,
197 MAX77693_CHARGING_OFF,
198 MAX77693_CHARGING_RESERVED,
199 MAX77693_CHARGING_OVER_TEMP,
200 MAX77693_CHARGING_WATCHDOG_EXPIRED,
203 /* MAX77693_CHG_REG_CHG_DETAILS_01/BAT field */
204 enum max77693_charger_battery_state {
205 MAX77693_BATTERY_NOBAT = 0x0,
206 /* Dead-battery or low-battery prequalification */
207 MAX77693_BATTERY_PREQUALIFICATION,
208 MAX77693_BATTERY_TIMER_EXPIRED,
209 MAX77693_BATTERY_GOOD,
210 MAX77693_BATTERY_LOWVOLTAGE,
211 MAX77693_BATTERY_OVERVOLTAGE,
212 MAX77693_BATTERY_OVERCURRENT,
213 MAX77693_BATTERY_RESERVED,
216 /* MAX77693_CHG_REG_CHG_DETAILS_02 register */
217 #define CHG_DETAILS_02_BYP_SHIFT 0
218 #define CHG_DETAILS_02_BYP_MASK (0xf << CHG_DETAILS_02_BYP_SHIFT)
220 /* MAX77693 CHG_CNFG_00 register */
221 #define CHG_CNFG_00_CHG_MASK 0x1
222 #define CHG_CNFG_00_BUCK_MASK 0x4
224 /* MAX77693_CHG_REG_CHG_CNFG_01 register */
225 #define CHG_CNFG_01_FCHGTIME_SHIFT 0
226 #define CHG_CNFG_01_CHGRSTRT_SHIFT 4
227 #define CHG_CNFG_01_PQEN_SHIFT 7
228 #define CHG_CNFG_01_FCHGTIME_MASK (0x7 << CHG_CNFG_01_FCHGTIME_SHIFT)
229 #define CHG_CNFG_01_CHGRSTRT_MASK (0x3 << CHG_CNFG_01_CHGRSTRT_SHIFT)
230 #define CHG_CNFG_01_PQEN_MAKS BIT(CHG_CNFG_01_PQEN_SHIFT)
232 /* MAX77693_CHG_REG_CHG_CNFG_03 register */
233 #define CHG_CNFG_03_TOITH_SHIFT 0
234 #define CHG_CNFG_03_TOTIME_SHIFT 3
235 #define CHG_CNFG_03_TOITH_MASK (0x7 << CHG_CNFG_03_TOITH_SHIFT)
236 #define CHG_CNFG_03_TOTIME_MASK (0x7 << CHG_CNFG_03_TOTIME_SHIFT)
238 /* MAX77693_CHG_REG_CHG_CNFG_04 register */
239 #define CHG_CNFG_04_CHGCVPRM_SHIFT 0
240 #define CHG_CNFG_04_MINVSYS_SHIFT 5
241 #define CHG_CNFG_04_CHGCVPRM_MASK (0x1f << CHG_CNFG_04_CHGCVPRM_SHIFT)
242 #define CHG_CNFG_04_MINVSYS_MASK (0x7 << CHG_CNFG_04_MINVSYS_SHIFT)
244 /* MAX77693_CHG_REG_CHG_CNFG_06 register */
245 #define CHG_CNFG_06_CHGPROT_SHIFT 2
246 #define CHG_CNFG_06_CHGPROT_MASK (0x3 << CHG_CNFG_06_CHGPROT_SHIFT)
248 /* MAX77693_CHG_REG_CHG_CNFG_07 register */
249 #define CHG_CNFG_07_REGTEMP_SHIFT 5
250 #define CHG_CNFG_07_REGTEMP_MASK (0x3 << CHG_CNFG_07_REGTEMP_SHIFT)
252 /* MAX77693_CHG_REG_CHG_CNFG_12 register */
253 #define CHG_CNFG_12_B2SOVRC_SHIFT 0
254 #define CHG_CNFG_12_VCHGINREG_SHIFT 3
255 #define CHG_CNFG_12_B2SOVRC_MASK (0x7 << CHG_CNFG_12_B2SOVRC_SHIFT)
256 #define CHG_CNFG_12_VCHGINREG_MASK (0x3 << CHG_CNFG_12_VCHGINREG_SHIFT)
258 /* MAX77693 CHG_CNFG_09 Register */
259 #define CHG_CNFG_09_CHGIN_ILIM_MASK 0x7F
261 /* MAX77693 CHG_CTRL Register */
262 #define SAFEOUT_CTRL_SAFEOUT1_MASK 0x3
263 #define SAFEOUT_CTRL_SAFEOUT2_MASK 0xC
264 #define SAFEOUT_CTRL_ENSAFEOUT1_MASK 0x40
265 #define SAFEOUT_CTRL_ENSAFEOUT2_MASK 0x80
267 /* Slave addr = 0x4A: MUIC */
268 enum max77693_muic_reg {
269 MAX77693_MUIC_REG_ID = 0x00,
270 MAX77693_MUIC_REG_INT1 = 0x01,
271 MAX77693_MUIC_REG_INT2 = 0x02,
272 MAX77693_MUIC_REG_INT3 = 0x03,
273 MAX77693_MUIC_REG_STATUS1 = 0x04,
274 MAX77693_MUIC_REG_STATUS2 = 0x05,
275 MAX77693_MUIC_REG_STATUS3 = 0x06,
276 MAX77693_MUIC_REG_INTMASK1 = 0x07,
277 MAX77693_MUIC_REG_INTMASK2 = 0x08,
278 MAX77693_MUIC_REG_INTMASK3 = 0x09,
279 MAX77693_MUIC_REG_CDETCTRL1 = 0x0A,
280 MAX77693_MUIC_REG_CDETCTRL2 = 0x0B,
281 MAX77693_MUIC_REG_CTRL1 = 0x0C,
282 MAX77693_MUIC_REG_CTRL2 = 0x0D,
283 MAX77693_MUIC_REG_CTRL3 = 0x0E,
285 MAX77693_MUIC_REG_END,
288 /* MAX77693 INTMASK1~2 Register */
289 #define INTMASK1_ADC1K_SHIFT 3
290 #define INTMASK1_ADCERR_SHIFT 2
291 #define INTMASK1_ADCLOW_SHIFT 1
292 #define INTMASK1_ADC_SHIFT 0
293 #define INTMASK1_ADC1K_MASK (1 << INTMASK1_ADC1K_SHIFT)
294 #define INTMASK1_ADCERR_MASK (1 << INTMASK1_ADCERR_SHIFT)
295 #define INTMASK1_ADCLOW_MASK (1 << INTMASK1_ADCLOW_SHIFT)
296 #define INTMASK1_ADC_MASK (1 << INTMASK1_ADC_SHIFT)
298 #define INTMASK2_VIDRM_SHIFT 5
299 #define INTMASK2_VBVOLT_SHIFT 4
300 #define INTMASK2_DXOVP_SHIFT 3
301 #define INTMASK2_DCDTMR_SHIFT 2
302 #define INTMASK2_CHGDETRUN_SHIFT 1
303 #define INTMASK2_CHGTYP_SHIFT 0
304 #define INTMASK2_VIDRM_MASK (1 << INTMASK2_VIDRM_SHIFT)
305 #define INTMASK2_VBVOLT_MASK (1 << INTMASK2_VBVOLT_SHIFT)
306 #define INTMASK2_DXOVP_MASK (1 << INTMASK2_DXOVP_SHIFT)
307 #define INTMASK2_DCDTMR_MASK (1 << INTMASK2_DCDTMR_SHIFT)
308 #define INTMASK2_CHGDETRUN_MASK (1 << INTMASK2_CHGDETRUN_SHIFT)
309 #define INTMASK2_CHGTYP_MASK (1 << INTMASK2_CHGTYP_SHIFT)
311 /* MAX77693 MUIC - STATUS1~3 Register */
312 #define STATUS1_ADC_SHIFT (0)
313 #define STATUS1_ADCLOW_SHIFT (5)
314 #define STATUS1_ADCERR_SHIFT (6)
315 #define STATUS1_ADC1K_SHIFT (7)
316 #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
317 #define STATUS1_ADCLOW_MASK (0x1 << STATUS1_ADCLOW_SHIFT)
318 #define STATUS1_ADCERR_MASK (0x1 << STATUS1_ADCERR_SHIFT)
319 #define STATUS1_ADC1K_MASK (0x1 << STATUS1_ADC1K_SHIFT)
321 #define STATUS2_CHGTYP_SHIFT (0)
322 #define STATUS2_CHGDETRUN_SHIFT (3)
323 #define STATUS2_DCDTMR_SHIFT (4)
324 #define STATUS2_DXOVP_SHIFT (5)
325 #define STATUS2_VBVOLT_SHIFT (6)
326 #define STATUS2_VIDRM_SHIFT (7)
327 #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
328 #define STATUS2_CHGDETRUN_MASK (0x1 << STATUS2_CHGDETRUN_SHIFT)
329 #define STATUS2_DCDTMR_MASK (0x1 << STATUS2_DCDTMR_SHIFT)
330 #define STATUS2_DXOVP_MASK (0x1 << STATUS2_DXOVP_SHIFT)
331 #define STATUS2_VBVOLT_MASK (0x1 << STATUS2_VBVOLT_SHIFT)
332 #define STATUS2_VIDRM_MASK (0x1 << STATUS2_VIDRM_SHIFT)
334 #define STATUS3_OVP_SHIFT (2)
335 #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
337 /* MAX77693 CDETCTRL1~2 register */
338 #define CDETCTRL1_CHGDETEN_SHIFT (0)
339 #define CDETCTRL1_CHGTYPMAN_SHIFT (1)
340 #define CDETCTRL1_DCDEN_SHIFT (2)
341 #define CDETCTRL1_DCD2SCT_SHIFT (3)
342 #define CDETCTRL1_CDDELAY_SHIFT (4)
343 #define CDETCTRL1_DCDCPL_SHIFT (5)
344 #define CDETCTRL1_CDPDET_SHIFT (7)
345 #define CDETCTRL1_CHGDETEN_MASK (0x1 << CDETCTRL1_CHGDETEN_SHIFT)
346 #define CDETCTRL1_CHGTYPMAN_MASK (0x1 << CDETCTRL1_CHGTYPMAN_SHIFT)
347 #define CDETCTRL1_DCDEN_MASK (0x1 << CDETCTRL1_DCDEN_SHIFT)
348 #define CDETCTRL1_DCD2SCT_MASK (0x1 << CDETCTRL1_DCD2SCT_SHIFT)
349 #define CDETCTRL1_CDDELAY_MASK (0x1 << CDETCTRL1_CDDELAY_SHIFT)
350 #define CDETCTRL1_DCDCPL_MASK (0x1 << CDETCTRL1_DCDCPL_SHIFT)
351 #define CDETCTRL1_CDPDET_MASK (0x1 << CDETCTRL1_CDPDET_SHIFT)
353 #define CDETCTRL2_VIDRMEN_SHIFT (1)
354 #define CDETCTRL2_DXOVPEN_SHIFT (3)
355 #define CDETCTRL2_VIDRMEN_MASK (0x1 << CDETCTRL2_VIDRMEN_SHIFT)
356 #define CDETCTRL2_DXOVPEN_MASK (0x1 << CDETCTRL2_DXOVPEN_SHIFT)
358 /* MAX77693 MUIC - CONTROL1~3 register */
359 #define COMN1SW_SHIFT (0)
360 #define COMP2SW_SHIFT (3)
361 #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
362 #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
363 #define COMP_SW_MASK (COMP2SW_MASK | COMN1SW_MASK)
364 #define CONTROL1_SW_USB ((1 << COMP2SW_SHIFT) \
365 | (1 << COMN1SW_SHIFT))
366 #define CONTROL1_SW_AUDIO ((2 << COMP2SW_SHIFT) \
367 | (2 << COMN1SW_SHIFT))
368 #define CONTROL1_SW_UART ((3 << COMP2SW_SHIFT) \
369 | (3 << COMN1SW_SHIFT))
370 #define CONTROL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
371 | (0 << COMN1SW_SHIFT))
373 #define CONTROL2_LOWPWR_SHIFT (0)
374 #define CONTROL2_ADCEN_SHIFT (1)
375 #define CONTROL2_CPEN_SHIFT (2)
376 #define CONTROL2_SFOUTASRT_SHIFT (3)
377 #define CONTROL2_SFOUTORD_SHIFT (4)
378 #define CONTROL2_ACCDET_SHIFT (5)
379 #define CONTROL2_USBCPINT_SHIFT (6)
380 #define CONTROL2_RCPS_SHIFT (7)
381 #define CONTROL2_LOWPWR_MASK (0x1 << CONTROL2_LOWPWR_SHIFT)
382 #define CONTROL2_ADCEN_MASK (0x1 << CONTROL2_ADCEN_SHIFT)
383 #define CONTROL2_CPEN_MASK (0x1 << CONTROL2_CPEN_SHIFT)
384 #define CONTROL2_SFOUTASRT_MASK (0x1 << CONTROL2_SFOUTASRT_SHIFT)
385 #define CONTROL2_SFOUTORD_MASK (0x1 << CONTROL2_SFOUTORD_SHIFT)
386 #define CONTROL2_ACCDET_MASK (0x1 << CONTROL2_ACCDET_SHIFT)
387 #define CONTROL2_USBCPINT_MASK (0x1 << CONTROL2_USBCPINT_SHIFT)
388 #define CONTROL2_RCPS_MASK (0x1 << CONTROL2_RCPS_SHIFT)
390 #define CONTROL3_JIGSET_SHIFT (0)
391 #define CONTROL3_BTLDSET_SHIFT (2)
392 #define CONTROL3_ADCDBSET_SHIFT (4)
393 #define CONTROL3_JIGSET_MASK (0x3 << CONTROL3_JIGSET_SHIFT)
394 #define CONTROL3_BTLDSET_MASK (0x3 << CONTROL3_BTLDSET_SHIFT)
395 #define CONTROL3_ADCDBSET_MASK (0x3 << CONTROL3_ADCDBSET_SHIFT)
397 /* Slave addr = 0x90: Haptic */
398 enum max77693_haptic_reg {
399 MAX77693_HAPTIC_REG_STATUS = 0x00,
400 MAX77693_HAPTIC_REG_CONFIG1 = 0x01,
401 MAX77693_HAPTIC_REG_CONFIG2 = 0x02,
402 MAX77693_HAPTIC_REG_CONFIG_CHNL = 0x03,
403 MAX77693_HAPTIC_REG_CONFG_CYC1 = 0x04,
404 MAX77693_HAPTIC_REG_CONFG_CYC2 = 0x05,
405 MAX77693_HAPTIC_REG_CONFIG_PER1 = 0x06,
406 MAX77693_HAPTIC_REG_CONFIG_PER2 = 0x07,
407 MAX77693_HAPTIC_REG_CONFIG_PER3 = 0x08,
408 MAX77693_HAPTIC_REG_CONFIG_PER4 = 0x09,
409 MAX77693_HAPTIC_REG_CONFIG_DUTY1 = 0x0A,
410 MAX77693_HAPTIC_REG_CONFIG_DUTY2 = 0x0B,
411 MAX77693_HAPTIC_REG_CONFIG_PWM1 = 0x0C,
412 MAX77693_HAPTIC_REG_CONFIG_PWM2 = 0x0D,
413 MAX77693_HAPTIC_REG_CONFIG_PWM3 = 0x0E,
414 MAX77693_HAPTIC_REG_CONFIG_PWM4 = 0x0F,
415 MAX77693_HAPTIC_REG_REV = 0x10,
417 MAX77693_HAPTIC_REG_END,
420 /* max77693-pmic LSCNFG configuraton register */
421 #define MAX77693_PMIC_LOW_SYS_MASK 0x80
422 #define MAX77693_PMIC_LOW_SYS_SHIFT 7
424 /* max77693-haptic configuration register */
425 #define MAX77693_CONFIG2_MODE 7
426 #define MAX77693_CONFIG2_MEN 6
427 #define MAX77693_CONFIG2_HTYP 5
429 enum max77693_irq_source {
437 MAX77693_IRQ_GROUP_NR,
440 #define SRC_IRQ_CHARGER BIT(0)
441 #define SRC_IRQ_TOP BIT(1)
442 #define SRC_IRQ_FLASH BIT(2)
443 #define SRC_IRQ_MUIC BIT(3)
444 #define SRC_IRQ_ALL (SRC_IRQ_CHARGER | SRC_IRQ_TOP \
445 | SRC_IRQ_FLASH | SRC_IRQ_MUIC)
447 #define LED_IRQ_FLED2_OPEN BIT(0)
448 #define LED_IRQ_FLED2_SHORT BIT(1)
449 #define LED_IRQ_FLED1_OPEN BIT(2)
450 #define LED_IRQ_FLED1_SHORT BIT(3)
451 #define LED_IRQ_MAX_FLASH BIT(4)
453 #define TOPSYS_IRQ_T120C_INT BIT(0)
454 #define TOPSYS_IRQ_T140C_INT BIT(1)
455 #define TOPSYS_IRQ_LOWSYS_INT BIT(3)
457 #define CHG_IRQ_BYP_I BIT(0)
458 #define CHG_IRQ_THM_I BIT(2)
459 #define CHG_IRQ_BAT_I BIT(3)
460 #define CHG_IRQ_CHG_I BIT(4)
461 #define CHG_IRQ_CHGIN_I BIT(6)
463 #define MUIC_IRQ_INT1_ADC BIT(0)
464 #define MUIC_IRQ_INT1_ADC_LOW BIT(1)
465 #define MUIC_IRQ_INT1_ADC_ERR BIT(2)
466 #define MUIC_IRQ_INT1_ADC1K BIT(3)
468 #define MUIC_IRQ_INT2_CHGTYP BIT(0)
469 #define MUIC_IRQ_INT2_CHGDETREUN BIT(1)
470 #define MUIC_IRQ_INT2_DCDTMR BIT(2)
471 #define MUIC_IRQ_INT2_DXOVP BIT(3)
472 #define MUIC_IRQ_INT2_VBVOLT BIT(4)
473 #define MUIC_IRQ_INT2_VIDRM BIT(5)
475 #define MUIC_IRQ_INT3_EOC BIT(0)
476 #define MUIC_IRQ_INT3_CGMBC BIT(1)
477 #define MUIC_IRQ_INT3_OVP BIT(2)
478 #define MUIC_IRQ_INT3_MBCCHG_ERR BIT(3)
479 #define MUIC_IRQ_INT3_CHG_ENABLED BIT(4)
480 #define MUIC_IRQ_INT3_BAT_DET BIT(5)
484 MAX77693_LED_IRQ_FLED2_OPEN,
485 MAX77693_LED_IRQ_FLED2_SHORT,
486 MAX77693_LED_IRQ_FLED1_OPEN,
487 MAX77693_LED_IRQ_FLED1_SHORT,
488 MAX77693_LED_IRQ_MAX_FLASH,
491 MAX77693_TOPSYS_IRQ_T120C_INT,
492 MAX77693_TOPSYS_IRQ_T140C_INT,
493 MAX77693_TOPSYS_IRQ_LOWSYS_INT,
496 MAX77693_CHG_IRQ_BYP_I,
497 MAX77693_CHG_IRQ_THM_I,
498 MAX77693_CHG_IRQ_BAT_I,
499 MAX77693_CHG_IRQ_CHG_I,
500 MAX77693_CHG_IRQ_CHGIN_I,
505 enum max77693_irq_muic {
507 MAX77693_MUIC_IRQ_INT1_ADC,
508 MAX77693_MUIC_IRQ_INT1_ADC_LOW,
509 MAX77693_MUIC_IRQ_INT1_ADC_ERR,
510 MAX77693_MUIC_IRQ_INT1_ADC1K,
513 MAX77693_MUIC_IRQ_INT2_CHGTYP,
514 MAX77693_MUIC_IRQ_INT2_CHGDETREUN,
515 MAX77693_MUIC_IRQ_INT2_DCDTMR,
516 MAX77693_MUIC_IRQ_INT2_DXOVP,
517 MAX77693_MUIC_IRQ_INT2_VBVOLT,
518 MAX77693_MUIC_IRQ_INT2_VIDRM,
521 MAX77693_MUIC_IRQ_INT3_EOC,
522 MAX77693_MUIC_IRQ_INT3_CGMBC,
523 MAX77693_MUIC_IRQ_INT3_OVP,
524 MAX77693_MUIC_IRQ_INT3_MBCCHG_ERR,
525 MAX77693_MUIC_IRQ_INT3_CHG_ENABLED,
526 MAX77693_MUIC_IRQ_INT3_BAT_DET,
528 MAX77693_MUIC_IRQ_NR,
531 struct max77693_dev {
533 struct i2c_client *i2c; /* 0xCC , PMIC, Charger, Flash LED */
534 struct i2c_client *muic; /* 0x4A , MUIC */
535 struct i2c_client *haptic; /* 0x90 , Haptic */
539 struct regmap *regmap;
540 struct regmap *regmap_muic;
541 struct regmap *regmap_haptic;
543 struct regmap_irq_chip_data *irq_data_led;
544 struct regmap_irq_chip_data *irq_data_topsys;
545 struct regmap_irq_chip_data *irq_data_charger;
546 struct regmap_irq_chip_data *irq_data_muic;
550 struct mutex irqlock;
551 int irq_masks_cur[MAX77693_IRQ_GROUP_NR];
552 int irq_masks_cache[MAX77693_IRQ_GROUP_NR];
555 enum max77693_types {
559 extern int max77693_irq_init(struct max77693_dev *max77686);
560 extern void max77693_irq_exit(struct max77693_dev *max77686);
561 extern int max77693_irq_resume(struct max77693_dev *max77686);
563 #endif /* __LINUX_MFD_MAX77693_PRIV_H */