2 * ARIZONA register definitions
4 * Copyright 2012 Wolfson Microelectronics plc
6 * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #ifndef _ARIZONA_REGISTERS_H
14 #define _ARIZONA_REGISTERS_H
19 #define ARIZONA_SOFTWARE_RESET 0x00
20 #define ARIZONA_DEVICE_REVISION 0x01
21 #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
22 #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
23 #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
24 #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
25 #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
26 #define ARIZONA_CTRL_IF_STATUS_1 0x0D
27 #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
28 #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
29 #define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18
30 #define ARIZONA_WRITE_SEQUENCER_PROM 0x1A
31 #define ARIZONA_TONE_GENERATOR_1 0x20
32 #define ARIZONA_TONE_GENERATOR_2 0x21
33 #define ARIZONA_TONE_GENERATOR_3 0x22
34 #define ARIZONA_TONE_GENERATOR_4 0x23
35 #define ARIZONA_TONE_GENERATOR_5 0x24
36 #define ARIZONA_PWM_DRIVE_1 0x30
37 #define ARIZONA_PWM_DRIVE_2 0x31
38 #define ARIZONA_PWM_DRIVE_3 0x32
39 #define ARIZONA_WAKE_CONTROL 0x40
40 #define ARIZONA_SEQUENCE_CONTROL 0x41
41 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1 0x61
42 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62
43 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63
44 #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64
45 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68
46 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69
47 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A
48 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B
49 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C
50 #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D
51 #define ARIZONA_COMFORT_NOISE_GENERATOR 0x70
52 #define ARIZONA_HAPTICS_CONTROL_1 0x90
53 #define ARIZONA_HAPTICS_CONTROL_2 0x91
54 #define ARIZONA_HAPTICS_PHASE_1_INTENSITY 0x92
55 #define ARIZONA_HAPTICS_PHASE_1_DURATION 0x93
56 #define ARIZONA_HAPTICS_PHASE_2_INTENSITY 0x94
57 #define ARIZONA_HAPTICS_PHASE_2_DURATION 0x95
58 #define ARIZONA_HAPTICS_PHASE_3_INTENSITY 0x96
59 #define ARIZONA_HAPTICS_PHASE_3_DURATION 0x97
60 #define ARIZONA_HAPTICS_STATUS 0x98
61 #define ARIZONA_CLOCK_32K_1 0x100
62 #define ARIZONA_SYSTEM_CLOCK_1 0x101
63 #define ARIZONA_SAMPLE_RATE_1 0x102
64 #define ARIZONA_SAMPLE_RATE_2 0x103
65 #define ARIZONA_SAMPLE_RATE_3 0x104
66 #define ARIZONA_SAMPLE_RATE_1_STATUS 0x10A
67 #define ARIZONA_SAMPLE_RATE_2_STATUS 0x10B
68 #define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C
69 #define ARIZONA_ASYNC_CLOCK_1 0x112
70 #define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113
71 #define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B
72 #define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149
73 #define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A
74 #define ARIZONA_RATE_ESTIMATOR_1 0x152
75 #define ARIZONA_RATE_ESTIMATOR_2 0x153
76 #define ARIZONA_RATE_ESTIMATOR_3 0x154
77 #define ARIZONA_RATE_ESTIMATOR_4 0x155
78 #define ARIZONA_RATE_ESTIMATOR_5 0x156
79 #define ARIZONA_DYNAMIC_FREQUENCY_SCALING_1 0x161
80 #define ARIZONA_FLL1_CONTROL_1 0x171
81 #define ARIZONA_FLL1_CONTROL_2 0x172
82 #define ARIZONA_FLL1_CONTROL_3 0x173
83 #define ARIZONA_FLL1_CONTROL_4 0x174
84 #define ARIZONA_FLL1_CONTROL_5 0x175
85 #define ARIZONA_FLL1_CONTROL_6 0x176
86 #define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177
87 #define ARIZONA_FLL1_NCO_TEST_0 0x178
88 #define ARIZONA_FLL1_SYNCHRONISER_1 0x181
89 #define ARIZONA_FLL1_SYNCHRONISER_2 0x182
90 #define ARIZONA_FLL1_SYNCHRONISER_3 0x183
91 #define ARIZONA_FLL1_SYNCHRONISER_4 0x184
92 #define ARIZONA_FLL1_SYNCHRONISER_5 0x185
93 #define ARIZONA_FLL1_SYNCHRONISER_6 0x186
94 #define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189
95 #define ARIZONA_FLL1_GPIO_CLOCK 0x18A
96 #define ARIZONA_FLL2_CONTROL_1 0x191
97 #define ARIZONA_FLL2_CONTROL_2 0x192
98 #define ARIZONA_FLL2_CONTROL_3 0x193
99 #define ARIZONA_FLL2_CONTROL_4 0x194
100 #define ARIZONA_FLL2_CONTROL_5 0x195
101 #define ARIZONA_FLL2_CONTROL_6 0x196
102 #define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197
103 #define ARIZONA_FLL2_NCO_TEST_0 0x198
104 #define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1
105 #define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2
106 #define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3
107 #define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4
108 #define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5
109 #define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6
110 #define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9
111 #define ARIZONA_FLL2_GPIO_CLOCK 0x1AA
112 #define ARIZONA_MIC_CHARGE_PUMP_1 0x200
113 #define ARIZONA_LDO1_CONTROL_1 0x210
114 #define ARIZONA_LDO1_CONTROL_2 0x212
115 #define ARIZONA_LDO2_CONTROL_1 0x213
116 #define ARIZONA_MIC_BIAS_CTRL_1 0x218
117 #define ARIZONA_MIC_BIAS_CTRL_2 0x219
118 #define ARIZONA_MIC_BIAS_CTRL_3 0x21A
119 #define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293
120 #define ARIZONA_HEADPHONE_DETECT_1 0x29B
121 #define ARIZONA_HEADPHONE_DETECT_2 0x29C
122 #define ARIZONA_HP_DACVAL 0x29F
123 #define ARIZONA_MICD_CLAMP_CONTROL 0x2A2
124 #define ARIZONA_MIC_DETECT_1 0x2A3
125 #define ARIZONA_MIC_DETECT_2 0x2A4
126 #define ARIZONA_MIC_DETECT_3 0x2A5
127 #define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
128 #define ARIZONA_ISOLATION_CONTROL 0x2CB
129 #define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
130 #define ARIZONA_INPUT_ENABLES 0x300
131 #define ARIZONA_INPUT_ENABLES_STATUS 0x301
132 #define ARIZONA_INPUT_RATE 0x308
133 #define ARIZONA_INPUT_VOLUME_RAMP 0x309
134 #define ARIZONA_IN1L_CONTROL 0x310
135 #define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311
136 #define ARIZONA_DMIC1L_CONTROL 0x312
137 #define ARIZONA_IN1R_CONTROL 0x314
138 #define ARIZONA_ADC_DIGITAL_VOLUME_1R 0x315
139 #define ARIZONA_DMIC1R_CONTROL 0x316
140 #define ARIZONA_IN2L_CONTROL 0x318
141 #define ARIZONA_ADC_DIGITAL_VOLUME_2L 0x319
142 #define ARIZONA_DMIC2L_CONTROL 0x31A
143 #define ARIZONA_IN2R_CONTROL 0x31C
144 #define ARIZONA_ADC_DIGITAL_VOLUME_2R 0x31D
145 #define ARIZONA_DMIC2R_CONTROL 0x31E
146 #define ARIZONA_IN3L_CONTROL 0x320
147 #define ARIZONA_ADC_DIGITAL_VOLUME_3L 0x321
148 #define ARIZONA_DMIC3L_CONTROL 0x322
149 #define ARIZONA_IN3R_CONTROL 0x324
150 #define ARIZONA_ADC_DIGITAL_VOLUME_3R 0x325
151 #define ARIZONA_DMIC3R_CONTROL 0x326
152 #define ARIZONA_IN4L_CONTROL 0x328
153 #define ARIZONA_ADC_DIGITAL_VOLUME_4L 0x329
154 #define ARIZONA_DMIC4L_CONTROL 0x32A
155 #define ARIZONA_ADC_DIGITAL_VOLUME_4R 0x32D
156 #define ARIZONA_DMIC4R_CONTROL 0x32E
157 #define ARIZONA_OUTPUT_ENABLES_1 0x400
158 #define ARIZONA_OUTPUT_STATUS_1 0x401
159 #define ARIZONA_RAW_OUTPUT_STATUS_1 0x406
160 #define ARIZONA_OUTPUT_RATE_1 0x408
161 #define ARIZONA_OUTPUT_VOLUME_RAMP 0x409
162 #define ARIZONA_OUTPUT_PATH_CONFIG_1L 0x410
163 #define ARIZONA_DAC_DIGITAL_VOLUME_1L 0x411
164 #define ARIZONA_DAC_VOLUME_LIMIT_1L 0x412
165 #define ARIZONA_NOISE_GATE_SELECT_1L 0x413
166 #define ARIZONA_OUTPUT_PATH_CONFIG_1R 0x414
167 #define ARIZONA_DAC_DIGITAL_VOLUME_1R 0x415
168 #define ARIZONA_DAC_VOLUME_LIMIT_1R 0x416
169 #define ARIZONA_NOISE_GATE_SELECT_1R 0x417
170 #define ARIZONA_OUTPUT_PATH_CONFIG_2L 0x418
171 #define ARIZONA_DAC_DIGITAL_VOLUME_2L 0x419
172 #define ARIZONA_DAC_VOLUME_LIMIT_2L 0x41A
173 #define ARIZONA_NOISE_GATE_SELECT_2L 0x41B
174 #define ARIZONA_OUTPUT_PATH_CONFIG_2R 0x41C
175 #define ARIZONA_DAC_DIGITAL_VOLUME_2R 0x41D
176 #define ARIZONA_DAC_VOLUME_LIMIT_2R 0x41E
177 #define ARIZONA_NOISE_GATE_SELECT_2R 0x41F
178 #define ARIZONA_OUTPUT_PATH_CONFIG_3L 0x420
179 #define ARIZONA_DAC_DIGITAL_VOLUME_3L 0x421
180 #define ARIZONA_DAC_VOLUME_LIMIT_3L 0x422
181 #define ARIZONA_NOISE_GATE_SELECT_3L 0x423
182 #define ARIZONA_OUTPUT_PATH_CONFIG_3R 0x424
183 #define ARIZONA_DAC_DIGITAL_VOLUME_3R 0x425
184 #define ARIZONA_DAC_VOLUME_LIMIT_3R 0x426
185 #define ARIZONA_NOISE_GATE_SELECT_3R 0x427
186 #define ARIZONA_OUTPUT_PATH_CONFIG_4L 0x428
187 #define ARIZONA_DAC_DIGITAL_VOLUME_4L 0x429
188 #define ARIZONA_OUT_VOLUME_4L 0x42A
189 #define ARIZONA_NOISE_GATE_SELECT_4L 0x42B
190 #define ARIZONA_OUTPUT_PATH_CONFIG_4R 0x42C
191 #define ARIZONA_DAC_DIGITAL_VOLUME_4R 0x42D
192 #define ARIZONA_OUT_VOLUME_4R 0x42E
193 #define ARIZONA_NOISE_GATE_SELECT_4R 0x42F
194 #define ARIZONA_OUTPUT_PATH_CONFIG_5L 0x430
195 #define ARIZONA_DAC_DIGITAL_VOLUME_5L 0x431
196 #define ARIZONA_DAC_VOLUME_LIMIT_5L 0x432
197 #define ARIZONA_NOISE_GATE_SELECT_5L 0x433
198 #define ARIZONA_OUTPUT_PATH_CONFIG_5R 0x434
199 #define ARIZONA_DAC_DIGITAL_VOLUME_5R 0x435
200 #define ARIZONA_DAC_VOLUME_LIMIT_5R 0x436
201 #define ARIZONA_NOISE_GATE_SELECT_5R 0x437
202 #define ARIZONA_OUTPUT_PATH_CONFIG_6L 0x438
203 #define ARIZONA_DAC_DIGITAL_VOLUME_6L 0x439
204 #define ARIZONA_DAC_VOLUME_LIMIT_6L 0x43A
205 #define ARIZONA_NOISE_GATE_SELECT_6L 0x43B
206 #define ARIZONA_OUTPUT_PATH_CONFIG_6R 0x43C
207 #define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D
208 #define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E
209 #define ARIZONA_NOISE_GATE_SELECT_6R 0x43F
210 #define ARIZONA_DAC_AEC_CONTROL_1 0x450
211 #define ARIZONA_NOISE_GATE_CONTROL 0x458
212 #define ARIZONA_PDM_SPK1_CTRL_1 0x490
213 #define ARIZONA_PDM_SPK1_CTRL_2 0x491
214 #define ARIZONA_PDM_SPK2_CTRL_1 0x492
215 #define ARIZONA_PDM_SPK2_CTRL_2 0x493
216 #define ARIZONA_DAC_COMP_1 0x4DC
217 #define ARIZONA_DAC_COMP_2 0x4DD
218 #define ARIZONA_DAC_COMP_3 0x4DE
219 #define ARIZONA_DAC_COMP_4 0x4DF
220 #define ARIZONA_AIF1_BCLK_CTRL 0x500
221 #define ARIZONA_AIF1_TX_PIN_CTRL 0x501
222 #define ARIZONA_AIF1_RX_PIN_CTRL 0x502
223 #define ARIZONA_AIF1_RATE_CTRL 0x503
224 #define ARIZONA_AIF1_FORMAT 0x504
225 #define ARIZONA_AIF1_TX_BCLK_RATE 0x505
226 #define ARIZONA_AIF1_RX_BCLK_RATE 0x506
227 #define ARIZONA_AIF1_FRAME_CTRL_1 0x507
228 #define ARIZONA_AIF1_FRAME_CTRL_2 0x508
229 #define ARIZONA_AIF1_FRAME_CTRL_3 0x509
230 #define ARIZONA_AIF1_FRAME_CTRL_4 0x50A
231 #define ARIZONA_AIF1_FRAME_CTRL_5 0x50B
232 #define ARIZONA_AIF1_FRAME_CTRL_6 0x50C
233 #define ARIZONA_AIF1_FRAME_CTRL_7 0x50D
234 #define ARIZONA_AIF1_FRAME_CTRL_8 0x50E
235 #define ARIZONA_AIF1_FRAME_CTRL_9 0x50F
236 #define ARIZONA_AIF1_FRAME_CTRL_10 0x510
237 #define ARIZONA_AIF1_FRAME_CTRL_11 0x511
238 #define ARIZONA_AIF1_FRAME_CTRL_12 0x512
239 #define ARIZONA_AIF1_FRAME_CTRL_13 0x513
240 #define ARIZONA_AIF1_FRAME_CTRL_14 0x514
241 #define ARIZONA_AIF1_FRAME_CTRL_15 0x515
242 #define ARIZONA_AIF1_FRAME_CTRL_16 0x516
243 #define ARIZONA_AIF1_FRAME_CTRL_17 0x517
244 #define ARIZONA_AIF1_FRAME_CTRL_18 0x518
245 #define ARIZONA_AIF1_TX_ENABLES 0x519
246 #define ARIZONA_AIF1_RX_ENABLES 0x51A
247 #define ARIZONA_AIF1_FORCE_WRITE 0x51B
248 #define ARIZONA_AIF2_BCLK_CTRL 0x540
249 #define ARIZONA_AIF2_TX_PIN_CTRL 0x541
250 #define ARIZONA_AIF2_RX_PIN_CTRL 0x542
251 #define ARIZONA_AIF2_RATE_CTRL 0x543
252 #define ARIZONA_AIF2_FORMAT 0x544
253 #define ARIZONA_AIF2_TX_BCLK_RATE 0x545
254 #define ARIZONA_AIF2_RX_BCLK_RATE 0x546
255 #define ARIZONA_AIF2_FRAME_CTRL_1 0x547
256 #define ARIZONA_AIF2_FRAME_CTRL_2 0x548
257 #define ARIZONA_AIF2_FRAME_CTRL_3 0x549
258 #define ARIZONA_AIF2_FRAME_CTRL_4 0x54A
259 #define ARIZONA_AIF2_FRAME_CTRL_11 0x551
260 #define ARIZONA_AIF2_FRAME_CTRL_12 0x552
261 #define ARIZONA_AIF2_TX_ENABLES 0x559
262 #define ARIZONA_AIF2_RX_ENABLES 0x55A
263 #define ARIZONA_AIF2_FORCE_WRITE 0x55B
264 #define ARIZONA_AIF3_BCLK_CTRL 0x580
265 #define ARIZONA_AIF3_TX_PIN_CTRL 0x581
266 #define ARIZONA_AIF3_RX_PIN_CTRL 0x582
267 #define ARIZONA_AIF3_RATE_CTRL 0x583
268 #define ARIZONA_AIF3_FORMAT 0x584
269 #define ARIZONA_AIF3_TX_BCLK_RATE 0x585
270 #define ARIZONA_AIF3_RX_BCLK_RATE 0x586
271 #define ARIZONA_AIF3_FRAME_CTRL_1 0x587
272 #define ARIZONA_AIF3_FRAME_CTRL_2 0x588
273 #define ARIZONA_AIF3_FRAME_CTRL_3 0x589
274 #define ARIZONA_AIF3_FRAME_CTRL_4 0x58A
275 #define ARIZONA_AIF3_FRAME_CTRL_11 0x591
276 #define ARIZONA_AIF3_FRAME_CTRL_12 0x592
277 #define ARIZONA_AIF3_TX_ENABLES 0x599
278 #define ARIZONA_AIF3_RX_ENABLES 0x59A
279 #define ARIZONA_AIF3_FORCE_WRITE 0x59B
280 #define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3
281 #define ARIZONA_SLIMBUS_RATES_1 0x5E5
282 #define ARIZONA_SLIMBUS_RATES_2 0x5E6
283 #define ARIZONA_SLIMBUS_RATES_3 0x5E7
284 #define ARIZONA_SLIMBUS_RATES_4 0x5E8
285 #define ARIZONA_SLIMBUS_RATES_5 0x5E9
286 #define ARIZONA_SLIMBUS_RATES_6 0x5EA
287 #define ARIZONA_SLIMBUS_RATES_7 0x5EB
288 #define ARIZONA_SLIMBUS_RATES_8 0x5EC
289 #define ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE 0x5F5
290 #define ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE 0x5F6
291 #define ARIZONA_SLIMBUS_RX_PORT_STATUS 0x5F7
292 #define ARIZONA_SLIMBUS_TX_PORT_STATUS 0x5F8
293 #define ARIZONA_PWM1MIX_INPUT_1_SOURCE 0x640
294 #define ARIZONA_PWM1MIX_INPUT_1_VOLUME 0x641
295 #define ARIZONA_PWM1MIX_INPUT_2_SOURCE 0x642
296 #define ARIZONA_PWM1MIX_INPUT_2_VOLUME 0x643
297 #define ARIZONA_PWM1MIX_INPUT_3_SOURCE 0x644
298 #define ARIZONA_PWM1MIX_INPUT_3_VOLUME 0x645
299 #define ARIZONA_PWM1MIX_INPUT_4_SOURCE 0x646
300 #define ARIZONA_PWM1MIX_INPUT_4_VOLUME 0x647
301 #define ARIZONA_PWM2MIX_INPUT_1_SOURCE 0x648
302 #define ARIZONA_PWM2MIX_INPUT_1_VOLUME 0x649
303 #define ARIZONA_PWM2MIX_INPUT_2_SOURCE 0x64A
304 #define ARIZONA_PWM2MIX_INPUT_2_VOLUME 0x64B
305 #define ARIZONA_PWM2MIX_INPUT_3_SOURCE 0x64C
306 #define ARIZONA_PWM2MIX_INPUT_3_VOLUME 0x64D
307 #define ARIZONA_PWM2MIX_INPUT_4_SOURCE 0x64E
308 #define ARIZONA_PWM2MIX_INPUT_4_VOLUME 0x64F
309 #define ARIZONA_MICMIX_INPUT_1_SOURCE 0x660
310 #define ARIZONA_MICMIX_INPUT_1_VOLUME 0x661
311 #define ARIZONA_MICMIX_INPUT_2_SOURCE 0x662
312 #define ARIZONA_MICMIX_INPUT_2_VOLUME 0x663
313 #define ARIZONA_MICMIX_INPUT_3_SOURCE 0x664
314 #define ARIZONA_MICMIX_INPUT_3_VOLUME 0x665
315 #define ARIZONA_MICMIX_INPUT_4_SOURCE 0x666
316 #define ARIZONA_MICMIX_INPUT_4_VOLUME 0x667
317 #define ARIZONA_NOISEMIX_INPUT_1_SOURCE 0x668
318 #define ARIZONA_NOISEMIX_INPUT_1_VOLUME 0x669
319 #define ARIZONA_NOISEMIX_INPUT_2_SOURCE 0x66A
320 #define ARIZONA_NOISEMIX_INPUT_2_VOLUME 0x66B
321 #define ARIZONA_NOISEMIX_INPUT_3_SOURCE 0x66C
322 #define ARIZONA_NOISEMIX_INPUT_3_VOLUME 0x66D
323 #define ARIZONA_NOISEMIX_INPUT_4_SOURCE 0x66E
324 #define ARIZONA_NOISEMIX_INPUT_4_VOLUME 0x66F
325 #define ARIZONA_OUT1LMIX_INPUT_1_SOURCE 0x680
326 #define ARIZONA_OUT1LMIX_INPUT_1_VOLUME 0x681
327 #define ARIZONA_OUT1LMIX_INPUT_2_SOURCE 0x682
328 #define ARIZONA_OUT1LMIX_INPUT_2_VOLUME 0x683
329 #define ARIZONA_OUT1LMIX_INPUT_3_SOURCE 0x684
330 #define ARIZONA_OUT1LMIX_INPUT_3_VOLUME 0x685
331 #define ARIZONA_OUT1LMIX_INPUT_4_SOURCE 0x686
332 #define ARIZONA_OUT1LMIX_INPUT_4_VOLUME 0x687
333 #define ARIZONA_OUT1RMIX_INPUT_1_SOURCE 0x688
334 #define ARIZONA_OUT1RMIX_INPUT_1_VOLUME 0x689
335 #define ARIZONA_OUT1RMIX_INPUT_2_SOURCE 0x68A
336 #define ARIZONA_OUT1RMIX_INPUT_2_VOLUME 0x68B
337 #define ARIZONA_OUT1RMIX_INPUT_3_SOURCE 0x68C
338 #define ARIZONA_OUT1RMIX_INPUT_3_VOLUME 0x68D
339 #define ARIZONA_OUT1RMIX_INPUT_4_SOURCE 0x68E
340 #define ARIZONA_OUT1RMIX_INPUT_4_VOLUME 0x68F
341 #define ARIZONA_OUT2LMIX_INPUT_1_SOURCE 0x690
342 #define ARIZONA_OUT2LMIX_INPUT_1_VOLUME 0x691
343 #define ARIZONA_OUT2LMIX_INPUT_2_SOURCE 0x692
344 #define ARIZONA_OUT2LMIX_INPUT_2_VOLUME 0x693
345 #define ARIZONA_OUT2LMIX_INPUT_3_SOURCE 0x694
346 #define ARIZONA_OUT2LMIX_INPUT_3_VOLUME 0x695
347 #define ARIZONA_OUT2LMIX_INPUT_4_SOURCE 0x696
348 #define ARIZONA_OUT2LMIX_INPUT_4_VOLUME 0x697
349 #define ARIZONA_OUT2RMIX_INPUT_1_SOURCE 0x698
350 #define ARIZONA_OUT2RMIX_INPUT_1_VOLUME 0x699
351 #define ARIZONA_OUT2RMIX_INPUT_2_SOURCE 0x69A
352 #define ARIZONA_OUT2RMIX_INPUT_2_VOLUME 0x69B
353 #define ARIZONA_OUT2RMIX_INPUT_3_SOURCE 0x69C
354 #define ARIZONA_OUT2RMIX_INPUT_3_VOLUME 0x69D
355 #define ARIZONA_OUT2RMIX_INPUT_4_SOURCE 0x69E
356 #define ARIZONA_OUT2RMIX_INPUT_4_VOLUME 0x69F
357 #define ARIZONA_OUT3LMIX_INPUT_1_SOURCE 0x6A0
358 #define ARIZONA_OUT3LMIX_INPUT_1_VOLUME 0x6A1
359 #define ARIZONA_OUT3LMIX_INPUT_2_SOURCE 0x6A2
360 #define ARIZONA_OUT3LMIX_INPUT_2_VOLUME 0x6A3
361 #define ARIZONA_OUT3LMIX_INPUT_3_SOURCE 0x6A4
362 #define ARIZONA_OUT3LMIX_INPUT_3_VOLUME 0x6A5
363 #define ARIZONA_OUT3LMIX_INPUT_4_SOURCE 0x6A6
364 #define ARIZONA_OUT3LMIX_INPUT_4_VOLUME 0x6A7
365 #define ARIZONA_OUT3RMIX_INPUT_1_SOURCE 0x6A8
366 #define ARIZONA_OUT3RMIX_INPUT_1_VOLUME 0x6A9
367 #define ARIZONA_OUT3RMIX_INPUT_2_SOURCE 0x6AA
368 #define ARIZONA_OUT3RMIX_INPUT_2_VOLUME 0x6AB
369 #define ARIZONA_OUT3RMIX_INPUT_3_SOURCE 0x6AC
370 #define ARIZONA_OUT3RMIX_INPUT_3_VOLUME 0x6AD
371 #define ARIZONA_OUT3RMIX_INPUT_4_SOURCE 0x6AE
372 #define ARIZONA_OUT3RMIX_INPUT_4_VOLUME 0x6AF
373 #define ARIZONA_OUT4LMIX_INPUT_1_SOURCE 0x6B0
374 #define ARIZONA_OUT4LMIX_INPUT_1_VOLUME 0x6B1
375 #define ARIZONA_OUT4LMIX_INPUT_2_SOURCE 0x6B2
376 #define ARIZONA_OUT4LMIX_INPUT_2_VOLUME 0x6B3
377 #define ARIZONA_OUT4LMIX_INPUT_3_SOURCE 0x6B4
378 #define ARIZONA_OUT4LMIX_INPUT_3_VOLUME 0x6B5
379 #define ARIZONA_OUT4LMIX_INPUT_4_SOURCE 0x6B6
380 #define ARIZONA_OUT4LMIX_INPUT_4_VOLUME 0x6B7
381 #define ARIZONA_OUT4RMIX_INPUT_1_SOURCE 0x6B8
382 #define ARIZONA_OUT4RMIX_INPUT_1_VOLUME 0x6B9
383 #define ARIZONA_OUT4RMIX_INPUT_2_SOURCE 0x6BA
384 #define ARIZONA_OUT4RMIX_INPUT_2_VOLUME 0x6BB
385 #define ARIZONA_OUT4RMIX_INPUT_3_SOURCE 0x6BC
386 #define ARIZONA_OUT4RMIX_INPUT_3_VOLUME 0x6BD
387 #define ARIZONA_OUT4RMIX_INPUT_4_SOURCE 0x6BE
388 #define ARIZONA_OUT4RMIX_INPUT_4_VOLUME 0x6BF
389 #define ARIZONA_OUT5LMIX_INPUT_1_SOURCE 0x6C0
390 #define ARIZONA_OUT5LMIX_INPUT_1_VOLUME 0x6C1
391 #define ARIZONA_OUT5LMIX_INPUT_2_SOURCE 0x6C2
392 #define ARIZONA_OUT5LMIX_INPUT_2_VOLUME 0x6C3
393 #define ARIZONA_OUT5LMIX_INPUT_3_SOURCE 0x6C4
394 #define ARIZONA_OUT5LMIX_INPUT_3_VOLUME 0x6C5
395 #define ARIZONA_OUT5LMIX_INPUT_4_SOURCE 0x6C6
396 #define ARIZONA_OUT5LMIX_INPUT_4_VOLUME 0x6C7
397 #define ARIZONA_OUT5RMIX_INPUT_1_SOURCE 0x6C8
398 #define ARIZONA_OUT5RMIX_INPUT_1_VOLUME 0x6C9
399 #define ARIZONA_OUT5RMIX_INPUT_2_SOURCE 0x6CA
400 #define ARIZONA_OUT5RMIX_INPUT_2_VOLUME 0x6CB
401 #define ARIZONA_OUT5RMIX_INPUT_3_SOURCE 0x6CC
402 #define ARIZONA_OUT5RMIX_INPUT_3_VOLUME 0x6CD
403 #define ARIZONA_OUT5RMIX_INPUT_4_SOURCE 0x6CE
404 #define ARIZONA_OUT5RMIX_INPUT_4_VOLUME 0x6CF
405 #define ARIZONA_OUT6LMIX_INPUT_1_SOURCE 0x6D0
406 #define ARIZONA_OUT6LMIX_INPUT_1_VOLUME 0x6D1
407 #define ARIZONA_OUT6LMIX_INPUT_2_SOURCE 0x6D2
408 #define ARIZONA_OUT6LMIX_INPUT_2_VOLUME 0x6D3
409 #define ARIZONA_OUT6LMIX_INPUT_3_SOURCE 0x6D4
410 #define ARIZONA_OUT6LMIX_INPUT_3_VOLUME 0x6D5
411 #define ARIZONA_OUT6LMIX_INPUT_4_SOURCE 0x6D6
412 #define ARIZONA_OUT6LMIX_INPUT_4_VOLUME 0x6D7
413 #define ARIZONA_OUT6RMIX_INPUT_1_SOURCE 0x6D8
414 #define ARIZONA_OUT6RMIX_INPUT_1_VOLUME 0x6D9
415 #define ARIZONA_OUT6RMIX_INPUT_2_SOURCE 0x6DA
416 #define ARIZONA_OUT6RMIX_INPUT_2_VOLUME 0x6DB
417 #define ARIZONA_OUT6RMIX_INPUT_3_SOURCE 0x6DC
418 #define ARIZONA_OUT6RMIX_INPUT_3_VOLUME 0x6DD
419 #define ARIZONA_OUT6RMIX_INPUT_4_SOURCE 0x6DE
420 #define ARIZONA_OUT6RMIX_INPUT_4_VOLUME 0x6DF
421 #define ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE 0x700
422 #define ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME 0x701
423 #define ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE 0x702
424 #define ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME 0x703
425 #define ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE 0x704
426 #define ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME 0x705
427 #define ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE 0x706
428 #define ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME 0x707
429 #define ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE 0x708
430 #define ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME 0x709
431 #define ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE 0x70A
432 #define ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME 0x70B
433 #define ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE 0x70C
434 #define ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME 0x70D
435 #define ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE 0x70E
436 #define ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME 0x70F
437 #define ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE 0x710
438 #define ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME 0x711
439 #define ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE 0x712
440 #define ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME 0x713
441 #define ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE 0x714
442 #define ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME 0x715
443 #define ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE 0x716
444 #define ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME 0x717
445 #define ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE 0x718
446 #define ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME 0x719
447 #define ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE 0x71A
448 #define ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME 0x71B
449 #define ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE 0x71C
450 #define ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME 0x71D
451 #define ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE 0x71E
452 #define ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME 0x71F
453 #define ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE 0x720
454 #define ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME 0x721
455 #define ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE 0x722
456 #define ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME 0x723
457 #define ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE 0x724
458 #define ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME 0x725
459 #define ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE 0x726
460 #define ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME 0x727
461 #define ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE 0x728
462 #define ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME 0x729
463 #define ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE 0x72A
464 #define ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME 0x72B
465 #define ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE 0x72C
466 #define ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME 0x72D
467 #define ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE 0x72E
468 #define ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME 0x72F
469 #define ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE 0x730
470 #define ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME 0x731
471 #define ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE 0x732
472 #define ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME 0x733
473 #define ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE 0x734
474 #define ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME 0x735
475 #define ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE 0x736
476 #define ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME 0x737
477 #define ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE 0x738
478 #define ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME 0x739
479 #define ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE 0x73A
480 #define ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME 0x73B
481 #define ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE 0x73C
482 #define ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME 0x73D
483 #define ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE 0x73E
484 #define ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME 0x73F
485 #define ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE 0x740
486 #define ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME 0x741
487 #define ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE 0x742
488 #define ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME 0x743
489 #define ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE 0x744
490 #define ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME 0x745
491 #define ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE 0x746
492 #define ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME 0x747
493 #define ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE 0x748
494 #define ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME 0x749
495 #define ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE 0x74A
496 #define ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME 0x74B
497 #define ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE 0x74C
498 #define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D
499 #define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E
500 #define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F
501 #define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780
502 #define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781
503 #define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782
504 #define ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME 0x783
505 #define ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE 0x784
506 #define ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME 0x785
507 #define ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE 0x786
508 #define ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME 0x787
509 #define ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE 0x788
510 #define ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME 0x789
511 #define ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE 0x78A
512 #define ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME 0x78B
513 #define ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE 0x78C
514 #define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
515 #define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
516 #define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
517 #define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE 0x7C0
518 #define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME 0x7C1
519 #define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE 0x7C2
520 #define ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME 0x7C3
521 #define ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE 0x7C4
522 #define ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME 0x7C5
523 #define ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE 0x7C6
524 #define ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME 0x7C7
525 #define ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE 0x7C8
526 #define ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME 0x7C9
527 #define ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE 0x7CA
528 #define ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME 0x7CB
529 #define ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE 0x7CC
530 #define ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME 0x7CD
531 #define ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE 0x7CE
532 #define ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME 0x7CF
533 #define ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE 0x7D0
534 #define ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME 0x7D1
535 #define ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE 0x7D2
536 #define ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME 0x7D3
537 #define ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE 0x7D4
538 #define ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME 0x7D5
539 #define ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE 0x7D6
540 #define ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME 0x7D7
541 #define ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE 0x7D8
542 #define ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME 0x7D9
543 #define ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE 0x7DA
544 #define ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME 0x7DB
545 #define ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE 0x7DC
546 #define ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME 0x7DD
547 #define ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE 0x7DE
548 #define ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME 0x7DF
549 #define ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE 0x7E0
550 #define ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME 0x7E1
551 #define ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE 0x7E2
552 #define ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME 0x7E3
553 #define ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE 0x7E4
554 #define ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME 0x7E5
555 #define ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE 0x7E6
556 #define ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME 0x7E7
557 #define ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE 0x7E8
558 #define ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME 0x7E9
559 #define ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE 0x7EA
560 #define ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME 0x7EB
561 #define ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE 0x7EC
562 #define ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME 0x7ED
563 #define ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE 0x7EE
564 #define ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME 0x7EF
565 #define ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE 0x7F0
566 #define ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME 0x7F1
567 #define ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE 0x7F2
568 #define ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME 0x7F3
569 #define ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE 0x7F4
570 #define ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME 0x7F5
571 #define ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE 0x7F6
572 #define ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME 0x7F7
573 #define ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE 0x7F8
574 #define ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME 0x7F9
575 #define ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE 0x7FA
576 #define ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME 0x7FB
577 #define ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE 0x7FC
578 #define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD
579 #define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE
580 #define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF
581 #define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880
582 #define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881
583 #define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882
584 #define ARIZONA_EQ1MIX_INPUT_2_VOLUME 0x883
585 #define ARIZONA_EQ1MIX_INPUT_3_SOURCE 0x884
586 #define ARIZONA_EQ1MIX_INPUT_3_VOLUME 0x885
587 #define ARIZONA_EQ1MIX_INPUT_4_SOURCE 0x886
588 #define ARIZONA_EQ1MIX_INPUT_4_VOLUME 0x887
589 #define ARIZONA_EQ2MIX_INPUT_1_SOURCE 0x888
590 #define ARIZONA_EQ2MIX_INPUT_1_VOLUME 0x889
591 #define ARIZONA_EQ2MIX_INPUT_2_SOURCE 0x88A
592 #define ARIZONA_EQ2MIX_INPUT_2_VOLUME 0x88B
593 #define ARIZONA_EQ2MIX_INPUT_3_SOURCE 0x88C
594 #define ARIZONA_EQ2MIX_INPUT_3_VOLUME 0x88D
595 #define ARIZONA_EQ2MIX_INPUT_4_SOURCE 0x88E
596 #define ARIZONA_EQ2MIX_INPUT_4_VOLUME 0x88F
597 #define ARIZONA_EQ3MIX_INPUT_1_SOURCE 0x890
598 #define ARIZONA_EQ3MIX_INPUT_1_VOLUME 0x891
599 #define ARIZONA_EQ3MIX_INPUT_2_SOURCE 0x892
600 #define ARIZONA_EQ3MIX_INPUT_2_VOLUME 0x893
601 #define ARIZONA_EQ3MIX_INPUT_3_SOURCE 0x894
602 #define ARIZONA_EQ3MIX_INPUT_3_VOLUME 0x895
603 #define ARIZONA_EQ3MIX_INPUT_4_SOURCE 0x896
604 #define ARIZONA_EQ3MIX_INPUT_4_VOLUME 0x897
605 #define ARIZONA_EQ4MIX_INPUT_1_SOURCE 0x898
606 #define ARIZONA_EQ4MIX_INPUT_1_VOLUME 0x899
607 #define ARIZONA_EQ4MIX_INPUT_2_SOURCE 0x89A
608 #define ARIZONA_EQ4MIX_INPUT_2_VOLUME 0x89B
609 #define ARIZONA_EQ4MIX_INPUT_3_SOURCE 0x89C
610 #define ARIZONA_EQ4MIX_INPUT_3_VOLUME 0x89D
611 #define ARIZONA_EQ4MIX_INPUT_4_SOURCE 0x89E
612 #define ARIZONA_EQ4MIX_INPUT_4_VOLUME 0x89F
613 #define ARIZONA_DRC1LMIX_INPUT_1_SOURCE 0x8C0
614 #define ARIZONA_DRC1LMIX_INPUT_1_VOLUME 0x8C1
615 #define ARIZONA_DRC1LMIX_INPUT_2_SOURCE 0x8C2
616 #define ARIZONA_DRC1LMIX_INPUT_2_VOLUME 0x8C3
617 #define ARIZONA_DRC1LMIX_INPUT_3_SOURCE 0x8C4
618 #define ARIZONA_DRC1LMIX_INPUT_3_VOLUME 0x8C5
619 #define ARIZONA_DRC1LMIX_INPUT_4_SOURCE 0x8C6
620 #define ARIZONA_DRC1LMIX_INPUT_4_VOLUME 0x8C7
621 #define ARIZONA_DRC1RMIX_INPUT_1_SOURCE 0x8C8
622 #define ARIZONA_DRC1RMIX_INPUT_1_VOLUME 0x8C9
623 #define ARIZONA_DRC1RMIX_INPUT_2_SOURCE 0x8CA
624 #define ARIZONA_DRC1RMIX_INPUT_2_VOLUME 0x8CB
625 #define ARIZONA_DRC1RMIX_INPUT_3_SOURCE 0x8CC
626 #define ARIZONA_DRC1RMIX_INPUT_3_VOLUME 0x8CD
627 #define ARIZONA_DRC1RMIX_INPUT_4_SOURCE 0x8CE
628 #define ARIZONA_DRC1RMIX_INPUT_4_VOLUME 0x8CF
629 #define ARIZONA_DRC2LMIX_INPUT_1_SOURCE 0x8D0
630 #define ARIZONA_DRC2LMIX_INPUT_1_VOLUME 0x8D1
631 #define ARIZONA_DRC2LMIX_INPUT_2_SOURCE 0x8D2
632 #define ARIZONA_DRC2LMIX_INPUT_2_VOLUME 0x8D3
633 #define ARIZONA_DRC2LMIX_INPUT_3_SOURCE 0x8D4
634 #define ARIZONA_DRC2LMIX_INPUT_3_VOLUME 0x8D5
635 #define ARIZONA_DRC2LMIX_INPUT_4_SOURCE 0x8D6
636 #define ARIZONA_DRC2LMIX_INPUT_4_VOLUME 0x8D7
637 #define ARIZONA_DRC2RMIX_INPUT_1_SOURCE 0x8D8
638 #define ARIZONA_DRC2RMIX_INPUT_1_VOLUME 0x8D9
639 #define ARIZONA_DRC2RMIX_INPUT_2_SOURCE 0x8DA
640 #define ARIZONA_DRC2RMIX_INPUT_2_VOLUME 0x8DB
641 #define ARIZONA_DRC2RMIX_INPUT_3_SOURCE 0x8DC
642 #define ARIZONA_DRC2RMIX_INPUT_3_VOLUME 0x8DD
643 #define ARIZONA_DRC2RMIX_INPUT_4_SOURCE 0x8DE
644 #define ARIZONA_DRC2RMIX_INPUT_4_VOLUME 0x8DF
645 #define ARIZONA_HPLP1MIX_INPUT_1_SOURCE 0x900
646 #define ARIZONA_HPLP1MIX_INPUT_1_VOLUME 0x901
647 #define ARIZONA_HPLP1MIX_INPUT_2_SOURCE 0x902
648 #define ARIZONA_HPLP1MIX_INPUT_2_VOLUME 0x903
649 #define ARIZONA_HPLP1MIX_INPUT_3_SOURCE 0x904
650 #define ARIZONA_HPLP1MIX_INPUT_3_VOLUME 0x905
651 #define ARIZONA_HPLP1MIX_INPUT_4_SOURCE 0x906
652 #define ARIZONA_HPLP1MIX_INPUT_4_VOLUME 0x907
653 #define ARIZONA_HPLP2MIX_INPUT_1_SOURCE 0x908
654 #define ARIZONA_HPLP2MIX_INPUT_1_VOLUME 0x909
655 #define ARIZONA_HPLP2MIX_INPUT_2_SOURCE 0x90A
656 #define ARIZONA_HPLP2MIX_INPUT_2_VOLUME 0x90B
657 #define ARIZONA_HPLP2MIX_INPUT_3_SOURCE 0x90C
658 #define ARIZONA_HPLP2MIX_INPUT_3_VOLUME 0x90D
659 #define ARIZONA_HPLP2MIX_INPUT_4_SOURCE 0x90E
660 #define ARIZONA_HPLP2MIX_INPUT_4_VOLUME 0x90F
661 #define ARIZONA_HPLP3MIX_INPUT_1_SOURCE 0x910
662 #define ARIZONA_HPLP3MIX_INPUT_1_VOLUME 0x911
663 #define ARIZONA_HPLP3MIX_INPUT_2_SOURCE 0x912
664 #define ARIZONA_HPLP3MIX_INPUT_2_VOLUME 0x913
665 #define ARIZONA_HPLP3MIX_INPUT_3_SOURCE 0x914
666 #define ARIZONA_HPLP3MIX_INPUT_3_VOLUME 0x915
667 #define ARIZONA_HPLP3MIX_INPUT_4_SOURCE 0x916
668 #define ARIZONA_HPLP3MIX_INPUT_4_VOLUME 0x917
669 #define ARIZONA_HPLP4MIX_INPUT_1_SOURCE 0x918
670 #define ARIZONA_HPLP4MIX_INPUT_1_VOLUME 0x919
671 #define ARIZONA_HPLP4MIX_INPUT_2_SOURCE 0x91A
672 #define ARIZONA_HPLP4MIX_INPUT_2_VOLUME 0x91B
673 #define ARIZONA_HPLP4MIX_INPUT_3_SOURCE 0x91C
674 #define ARIZONA_HPLP4MIX_INPUT_3_VOLUME 0x91D
675 #define ARIZONA_HPLP4MIX_INPUT_4_SOURCE 0x91E
676 #define ARIZONA_HPLP4MIX_INPUT_4_VOLUME 0x91F
677 #define ARIZONA_DSP1LMIX_INPUT_1_SOURCE 0x940
678 #define ARIZONA_DSP1LMIX_INPUT_1_VOLUME 0x941
679 #define ARIZONA_DSP1LMIX_INPUT_2_SOURCE 0x942
680 #define ARIZONA_DSP1LMIX_INPUT_2_VOLUME 0x943
681 #define ARIZONA_DSP1LMIX_INPUT_3_SOURCE 0x944
682 #define ARIZONA_DSP1LMIX_INPUT_3_VOLUME 0x945
683 #define ARIZONA_DSP1LMIX_INPUT_4_SOURCE 0x946
684 #define ARIZONA_DSP1LMIX_INPUT_4_VOLUME 0x947
685 #define ARIZONA_DSP1RMIX_INPUT_1_SOURCE 0x948
686 #define ARIZONA_DSP1RMIX_INPUT_1_VOLUME 0x949
687 #define ARIZONA_DSP1RMIX_INPUT_2_SOURCE 0x94A
688 #define ARIZONA_DSP1RMIX_INPUT_2_VOLUME 0x94B
689 #define ARIZONA_DSP1RMIX_INPUT_3_SOURCE 0x94C
690 #define ARIZONA_DSP1RMIX_INPUT_3_VOLUME 0x94D
691 #define ARIZONA_DSP1RMIX_INPUT_4_SOURCE 0x94E
692 #define ARIZONA_DSP1RMIX_INPUT_4_VOLUME 0x94F
693 #define ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE 0x950
694 #define ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE 0x958
695 #define ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE 0x960
696 #define ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE 0x968
697 #define ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE 0x970
698 #define ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE 0x978
699 #define ARIZONA_DSP2LMIX_INPUT_1_SOURCE 0x980
700 #define ARIZONA_DSP2LMIX_INPUT_1_VOLUME 0x981
701 #define ARIZONA_DSP2LMIX_INPUT_2_SOURCE 0x982
702 #define ARIZONA_DSP2LMIX_INPUT_2_VOLUME 0x983
703 #define ARIZONA_DSP2LMIX_INPUT_3_SOURCE 0x984
704 #define ARIZONA_DSP2LMIX_INPUT_3_VOLUME 0x985
705 #define ARIZONA_DSP2LMIX_INPUT_4_SOURCE 0x986
706 #define ARIZONA_DSP2LMIX_INPUT_4_VOLUME 0x987
707 #define ARIZONA_DSP2RMIX_INPUT_1_SOURCE 0x988
708 #define ARIZONA_DSP2RMIX_INPUT_1_VOLUME 0x989
709 #define ARIZONA_DSP2RMIX_INPUT_2_SOURCE 0x98A
710 #define ARIZONA_DSP2RMIX_INPUT_2_VOLUME 0x98B
711 #define ARIZONA_DSP2RMIX_INPUT_3_SOURCE 0x98C
712 #define ARIZONA_DSP2RMIX_INPUT_3_VOLUME 0x98D
713 #define ARIZONA_DSP2RMIX_INPUT_4_SOURCE 0x98E
714 #define ARIZONA_DSP2RMIX_INPUT_4_VOLUME 0x98F
715 #define ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE 0x990
716 #define ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE 0x998
717 #define ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0
718 #define ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8
719 #define ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0
720 #define ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8
721 #define ARIZONA_DSP3LMIX_INPUT_1_SOURCE 0x9C0
722 #define ARIZONA_DSP3LMIX_INPUT_1_VOLUME 0x9C1
723 #define ARIZONA_DSP3LMIX_INPUT_2_SOURCE 0x9C2
724 #define ARIZONA_DSP3LMIX_INPUT_2_VOLUME 0x9C3
725 #define ARIZONA_DSP3LMIX_INPUT_3_SOURCE 0x9C4
726 #define ARIZONA_DSP3LMIX_INPUT_3_VOLUME 0x9C5
727 #define ARIZONA_DSP3LMIX_INPUT_4_SOURCE 0x9C6
728 #define ARIZONA_DSP3LMIX_INPUT_4_VOLUME 0x9C7
729 #define ARIZONA_DSP3RMIX_INPUT_1_SOURCE 0x9C8
730 #define ARIZONA_DSP3RMIX_INPUT_1_VOLUME 0x9C9
731 #define ARIZONA_DSP3RMIX_INPUT_2_SOURCE 0x9CA
732 #define ARIZONA_DSP3RMIX_INPUT_2_VOLUME 0x9CB
733 #define ARIZONA_DSP3RMIX_INPUT_3_SOURCE 0x9CC
734 #define ARIZONA_DSP3RMIX_INPUT_3_VOLUME 0x9CD
735 #define ARIZONA_DSP3RMIX_INPUT_4_SOURCE 0x9CE
736 #define ARIZONA_DSP3RMIX_INPUT_4_VOLUME 0x9CF
737 #define ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0
738 #define ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8
739 #define ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0
740 #define ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8
741 #define ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0
742 #define ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8
743 #define ARIZONA_DSP4LMIX_INPUT_1_SOURCE 0xA00
744 #define ARIZONA_DSP4LMIX_INPUT_1_VOLUME 0xA01
745 #define ARIZONA_DSP4LMIX_INPUT_2_SOURCE 0xA02
746 #define ARIZONA_DSP4LMIX_INPUT_2_VOLUME 0xA03
747 #define ARIZONA_DSP4LMIX_INPUT_3_SOURCE 0xA04
748 #define ARIZONA_DSP4LMIX_INPUT_3_VOLUME 0xA05
749 #define ARIZONA_DSP4LMIX_INPUT_4_SOURCE 0xA06
750 #define ARIZONA_DSP4LMIX_INPUT_4_VOLUME 0xA07
751 #define ARIZONA_DSP4RMIX_INPUT_1_SOURCE 0xA08
752 #define ARIZONA_DSP4RMIX_INPUT_1_VOLUME 0xA09
753 #define ARIZONA_DSP4RMIX_INPUT_2_SOURCE 0xA0A
754 #define ARIZONA_DSP4RMIX_INPUT_2_VOLUME 0xA0B
755 #define ARIZONA_DSP4RMIX_INPUT_3_SOURCE 0xA0C
756 #define ARIZONA_DSP4RMIX_INPUT_3_VOLUME 0xA0D
757 #define ARIZONA_DSP4RMIX_INPUT_4_SOURCE 0xA0E
758 #define ARIZONA_DSP4RMIX_INPUT_4_VOLUME 0xA0F
759 #define ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE 0xA10
760 #define ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE 0xA18
761 #define ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE 0xA20
762 #define ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE 0xA28
763 #define ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE 0xA30
764 #define ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE 0xA38
765 #define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE 0xA80
766 #define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE 0xA88
767 #define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE 0xA90
768 #define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE 0xA98
769 #define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00
770 #define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08
771 #define ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10
772 #define ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18
773 #define ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20
774 #define ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28
775 #define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30
776 #define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38
777 #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
778 #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
779 #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
780 #define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
781 #define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30
782 #define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38
783 #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
784 #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
785 #define ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50
786 #define ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58
787 #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
788 #define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
789 #define ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70
790 #define ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78
791 #define ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE 0xB80
792 #define ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE 0xB88
793 #define ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE 0xB90
794 #define ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE 0xB98
795 #define ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE 0xBA0
796 #define ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE 0xBA8
797 #define ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE 0xBB0
798 #define ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE 0xBB8
799 #define ARIZONA_GPIO1_CTRL 0xC00
800 #define ARIZONA_GPIO2_CTRL 0xC01
801 #define ARIZONA_GPIO3_CTRL 0xC02
802 #define ARIZONA_GPIO4_CTRL 0xC03
803 #define ARIZONA_GPIO5_CTRL 0xC04
804 #define ARIZONA_IRQ_CTRL_1 0xC0F
805 #define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10
806 #define ARIZONA_MISC_PAD_CTRL_1 0xC20
807 #define ARIZONA_MISC_PAD_CTRL_2 0xC21
808 #define ARIZONA_MISC_PAD_CTRL_3 0xC22
809 #define ARIZONA_MISC_PAD_CTRL_4 0xC23
810 #define ARIZONA_MISC_PAD_CTRL_5 0xC24
811 #define ARIZONA_MISC_PAD_CTRL_6 0xC25
812 #define ARIZONA_MISC_PAD_CTRL_7 0xC30
813 #define ARIZONA_MISC_PAD_CTRL_8 0xC31
814 #define ARIZONA_MISC_PAD_CTRL_9 0xC32
815 #define ARIZONA_MISC_PAD_CTRL_10 0xC33
816 #define ARIZONA_MISC_PAD_CTRL_11 0xC34
817 #define ARIZONA_MISC_PAD_CTRL_12 0xC35
818 #define ARIZONA_MISC_PAD_CTRL_13 0xC36
819 #define ARIZONA_MISC_PAD_CTRL_14 0xC37
820 #define ARIZONA_MISC_PAD_CTRL_15 0xC38
821 #define ARIZONA_MISC_PAD_CTRL_16 0xC39
822 #define ARIZONA_MISC_PAD_CTRL_17 0xC3A
823 #define ARIZONA_MISC_PAD_CTRL_18 0xC3B
824 #define ARIZONA_INTERRUPT_STATUS_1 0xD00
825 #define ARIZONA_INTERRUPT_STATUS_2 0xD01
826 #define ARIZONA_INTERRUPT_STATUS_3 0xD02
827 #define ARIZONA_INTERRUPT_STATUS_4 0xD03
828 #define ARIZONA_INTERRUPT_STATUS_5 0xD04
829 #define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08
830 #define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09
831 #define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A
832 #define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B
833 #define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C
834 #define ARIZONA_INTERRUPT_CONTROL 0xD0F
835 #define ARIZONA_IRQ2_STATUS_1 0xD10
836 #define ARIZONA_IRQ2_STATUS_2 0xD11
837 #define ARIZONA_IRQ2_STATUS_3 0xD12
838 #define ARIZONA_IRQ2_STATUS_4 0xD13
839 #define ARIZONA_IRQ2_STATUS_5 0xD14
840 #define ARIZONA_IRQ2_STATUS_1_MASK 0xD18
841 #define ARIZONA_IRQ2_STATUS_2_MASK 0xD19
842 #define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A
843 #define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B
844 #define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C
845 #define ARIZONA_IRQ2_CONTROL 0xD1F
846 #define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20
847 #define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21
848 #define ARIZONA_INTERRUPT_RAW_STATUS_4 0xD22
849 #define ARIZONA_INTERRUPT_RAW_STATUS_5 0xD23
850 #define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24
851 #define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25
852 #define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26
853 #define ARIZONA_IRQ_PIN_STATUS 0xD40
854 #define ARIZONA_ADSP2_IRQ0 0xD41
855 #define ARIZONA_AOD_WKUP_AND_TRIG 0xD50
856 #define ARIZONA_AOD_IRQ1 0xD51
857 #define ARIZONA_AOD_IRQ2 0xD52
858 #define ARIZONA_AOD_IRQ_MASK_IRQ1 0xD53
859 #define ARIZONA_AOD_IRQ_MASK_IRQ2 0xD54
860 #define ARIZONA_AOD_IRQ_RAW_STATUS 0xD55
861 #define ARIZONA_JACK_DETECT_DEBOUNCE 0xD56
862 #define ARIZONA_FX_CTRL1 0xE00
863 #define ARIZONA_FX_CTRL2 0xE01
864 #define ARIZONA_EQ1_1 0xE10
865 #define ARIZONA_EQ1_2 0xE11
866 #define ARIZONA_EQ1_3 0xE12
867 #define ARIZONA_EQ1_4 0xE13
868 #define ARIZONA_EQ1_5 0xE14
869 #define ARIZONA_EQ1_6 0xE15
870 #define ARIZONA_EQ1_7 0xE16
871 #define ARIZONA_EQ1_8 0xE17
872 #define ARIZONA_EQ1_9 0xE18
873 #define ARIZONA_EQ1_10 0xE19
874 #define ARIZONA_EQ1_11 0xE1A
875 #define ARIZONA_EQ1_12 0xE1B
876 #define ARIZONA_EQ1_13 0xE1C
877 #define ARIZONA_EQ1_14 0xE1D
878 #define ARIZONA_EQ1_15 0xE1E
879 #define ARIZONA_EQ1_16 0xE1F
880 #define ARIZONA_EQ1_17 0xE20
881 #define ARIZONA_EQ1_18 0xE21
882 #define ARIZONA_EQ1_19 0xE22
883 #define ARIZONA_EQ1_20 0xE23
884 #define ARIZONA_EQ1_21 0xE24
885 #define ARIZONA_EQ2_1 0xE26
886 #define ARIZONA_EQ2_2 0xE27
887 #define ARIZONA_EQ2_3 0xE28
888 #define ARIZONA_EQ2_4 0xE29
889 #define ARIZONA_EQ2_5 0xE2A
890 #define ARIZONA_EQ2_6 0xE2B
891 #define ARIZONA_EQ2_7 0xE2C
892 #define ARIZONA_EQ2_8 0xE2D
893 #define ARIZONA_EQ2_9 0xE2E
894 #define ARIZONA_EQ2_10 0xE2F
895 #define ARIZONA_EQ2_11 0xE30
896 #define ARIZONA_EQ2_12 0xE31
897 #define ARIZONA_EQ2_13 0xE32
898 #define ARIZONA_EQ2_14 0xE33
899 #define ARIZONA_EQ2_15 0xE34
900 #define ARIZONA_EQ2_16 0xE35
901 #define ARIZONA_EQ2_17 0xE36
902 #define ARIZONA_EQ2_18 0xE37
903 #define ARIZONA_EQ2_19 0xE38
904 #define ARIZONA_EQ2_20 0xE39
905 #define ARIZONA_EQ2_21 0xE3A
906 #define ARIZONA_EQ3_1 0xE3C
907 #define ARIZONA_EQ3_2 0xE3D
908 #define ARIZONA_EQ3_3 0xE3E
909 #define ARIZONA_EQ3_4 0xE3F
910 #define ARIZONA_EQ3_5 0xE40
911 #define ARIZONA_EQ3_6 0xE41
912 #define ARIZONA_EQ3_7 0xE42
913 #define ARIZONA_EQ3_8 0xE43
914 #define ARIZONA_EQ3_9 0xE44
915 #define ARIZONA_EQ3_10 0xE45
916 #define ARIZONA_EQ3_11 0xE46
917 #define ARIZONA_EQ3_12 0xE47
918 #define ARIZONA_EQ3_13 0xE48
919 #define ARIZONA_EQ3_14 0xE49
920 #define ARIZONA_EQ3_15 0xE4A
921 #define ARIZONA_EQ3_16 0xE4B
922 #define ARIZONA_EQ3_17 0xE4C
923 #define ARIZONA_EQ3_18 0xE4D
924 #define ARIZONA_EQ3_19 0xE4E
925 #define ARIZONA_EQ3_20 0xE4F
926 #define ARIZONA_EQ3_21 0xE50
927 #define ARIZONA_EQ4_1 0xE52
928 #define ARIZONA_EQ4_2 0xE53
929 #define ARIZONA_EQ4_3 0xE54
930 #define ARIZONA_EQ4_4 0xE55
931 #define ARIZONA_EQ4_5 0xE56
932 #define ARIZONA_EQ4_6 0xE57
933 #define ARIZONA_EQ4_7 0xE58
934 #define ARIZONA_EQ4_8 0xE59
935 #define ARIZONA_EQ4_9 0xE5A
936 #define ARIZONA_EQ4_10 0xE5B
937 #define ARIZONA_EQ4_11 0xE5C
938 #define ARIZONA_EQ4_12 0xE5D
939 #define ARIZONA_EQ4_13 0xE5E
940 #define ARIZONA_EQ4_14 0xE5F
941 #define ARIZONA_EQ4_15 0xE60
942 #define ARIZONA_EQ4_16 0xE61
943 #define ARIZONA_EQ4_17 0xE62
944 #define ARIZONA_EQ4_18 0xE63
945 #define ARIZONA_EQ4_19 0xE64
946 #define ARIZONA_EQ4_20 0xE65
947 #define ARIZONA_EQ4_21 0xE66
948 #define ARIZONA_DRC1_CTRL1 0xE80
949 #define ARIZONA_DRC1_CTRL2 0xE81
950 #define ARIZONA_DRC1_CTRL3 0xE82
951 #define ARIZONA_DRC1_CTRL4 0xE83
952 #define ARIZONA_DRC1_CTRL5 0xE84
953 #define ARIZONA_DRC2_CTRL1 0xE89
954 #define ARIZONA_DRC2_CTRL2 0xE8A
955 #define ARIZONA_DRC2_CTRL3 0xE8B
956 #define ARIZONA_DRC2_CTRL4 0xE8C
957 #define ARIZONA_DRC2_CTRL5 0xE8D
958 #define ARIZONA_HPLPF1_1 0xEC0
959 #define ARIZONA_HPLPF1_2 0xEC1
960 #define ARIZONA_HPLPF2_1 0xEC4
961 #define ARIZONA_HPLPF2_2 0xEC5
962 #define ARIZONA_HPLPF3_1 0xEC8
963 #define ARIZONA_HPLPF3_2 0xEC9
964 #define ARIZONA_HPLPF4_1 0xECC
965 #define ARIZONA_HPLPF4_2 0xECD
966 #define ARIZONA_ASRC_ENABLE 0xEE0
967 #define ARIZONA_ASRC_STATUS 0xEE1
968 #define ARIZONA_ASRC_RATE1 0xEE2
969 #define ARIZONA_ASRC_RATE2 0xEE3
970 #define ARIZONA_ISRC_1_CTRL_1 0xEF0
971 #define ARIZONA_ISRC_1_CTRL_2 0xEF1
972 #define ARIZONA_ISRC_1_CTRL_3 0xEF2
973 #define ARIZONA_ISRC_2_CTRL_1 0xEF3
974 #define ARIZONA_ISRC_2_CTRL_2 0xEF4
975 #define ARIZONA_ISRC_2_CTRL_3 0xEF5
976 #define ARIZONA_ISRC_3_CTRL_1 0xEF6
977 #define ARIZONA_ISRC_3_CTRL_2 0xEF7
978 #define ARIZONA_ISRC_3_CTRL_3 0xEF8
979 #define ARIZONA_CLOCK_CONTROL 0xF00
980 #define ARIZONA_ANC_SRC 0xF01
981 #define ARIZONA_DSP_STATUS 0xF02
982 #define ARIZONA_DSP1_CONTROL_1 0x1100
983 #define ARIZONA_DSP1_CLOCKING_1 0x1101
984 #define ARIZONA_DSP1_STATUS_1 0x1104
985 #define ARIZONA_DSP1_STATUS_2 0x1105
986 #define ARIZONA_DSP1_STATUS_3 0x1106
987 #define ARIZONA_DSP1_SCRATCH_0 0x1140
988 #define ARIZONA_DSP1_SCRATCH_1 0x1141
989 #define ARIZONA_DSP1_SCRATCH_2 0x1142
990 #define ARIZONA_DSP1_SCRATCH_3 0x1143
991 #define ARIZONA_DSP2_CONTROL_1 0x1200
992 #define ARIZONA_DSP2_CLOCKING_1 0x1201
993 #define ARIZONA_DSP2_STATUS_1 0x1204
994 #define ARIZONA_DSP2_STATUS_2 0x1205
995 #define ARIZONA_DSP2_SCRATCH_0 0x1240
996 #define ARIZONA_DSP2_SCRATCH_1 0x1241
997 #define ARIZONA_DSP2_SCRATCH_2 0x1242
998 #define ARIZONA_DSP2_SCRATCH_3 0x1243
999 #define ARIZONA_DSP3_CONTROL_1 0x1300
1000 #define ARIZONA_DSP3_CLOCKING_1 0x1301
1001 #define ARIZONA_DSP3_STATUS_1 0x1304
1002 #define ARIZONA_DSP3_STATUS_2 0x1305
1003 #define ARIZONA_DSP3_SCRATCH_0 0x1340
1004 #define ARIZONA_DSP3_SCRATCH_1 0x1341
1005 #define ARIZONA_DSP3_SCRATCH_2 0x1342
1006 #define ARIZONA_DSP3_SCRATCH_3 0x1343
1007 #define ARIZONA_DSP4_CONTROL_1 0x1400
1008 #define ARIZONA_DSP4_CLOCKING_1 0x1401
1009 #define ARIZONA_DSP4_STATUS_1 0x1404
1010 #define ARIZONA_DSP4_STATUS_2 0x1405
1011 #define ARIZONA_DSP4_SCRATCH_0 0x1440
1012 #define ARIZONA_DSP4_SCRATCH_1 0x1441
1013 #define ARIZONA_DSP4_SCRATCH_2 0x1442
1014 #define ARIZONA_DSP4_SCRATCH_3 0x1443
1017 * Field Definitions.
1021 * R0 (0x00) - software reset
1023 #define ARIZONA_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
1024 #define ARIZONA_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
1025 #define ARIZONA_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
1028 * R1 (0x01) - Device Revision
1030 #define ARIZONA_DEVICE_REVISION_MASK 0x00FF /* DEVICE_REVISION - [7:0] */
1031 #define ARIZONA_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [7:0] */
1032 #define ARIZONA_DEVICE_REVISION_WIDTH 8 /* DEVICE_REVISION - [7:0] */
1035 * R8 (0x08) - Ctrl IF SPI CFG 1
1037 #define ARIZONA_SPI_CFG 0x0010 /* SPI_CFG */
1038 #define ARIZONA_SPI_CFG_MASK 0x0010 /* SPI_CFG */
1039 #define ARIZONA_SPI_CFG_SHIFT 4 /* SPI_CFG */
1040 #define ARIZONA_SPI_CFG_WIDTH 1 /* SPI_CFG */
1041 #define ARIZONA_SPI_4WIRE 0x0008 /* SPI_4WIRE */
1042 #define ARIZONA_SPI_4WIRE_MASK 0x0008 /* SPI_4WIRE */
1043 #define ARIZONA_SPI_4WIRE_SHIFT 3 /* SPI_4WIRE */
1044 #define ARIZONA_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
1045 #define ARIZONA_SPI_AUTO_INC_MASK 0x0003 /* SPI_AUTO_INC - [1:0] */
1046 #define ARIZONA_SPI_AUTO_INC_SHIFT 0 /* SPI_AUTO_INC - [1:0] */
1047 #define ARIZONA_SPI_AUTO_INC_WIDTH 2 /* SPI_AUTO_INC - [1:0] */
1050 * R9 (0x09) - Ctrl IF I2C1 CFG 1
1052 #define ARIZONA_I2C1_AUTO_INC_MASK 0x0003 /* I2C1_AUTO_INC - [1:0] */
1053 #define ARIZONA_I2C1_AUTO_INC_SHIFT 0 /* I2C1_AUTO_INC - [1:0] */
1054 #define ARIZONA_I2C1_AUTO_INC_WIDTH 2 /* I2C1_AUTO_INC - [1:0] */
1057 * R13 (0x0D) - Ctrl IF Status 1
1059 #define ARIZONA_I2C1_BUSY 0x0020 /* I2C1_BUSY */
1060 #define ARIZONA_I2C1_BUSY_MASK 0x0020 /* I2C1_BUSY */
1061 #define ARIZONA_I2C1_BUSY_SHIFT 5 /* I2C1_BUSY */
1062 #define ARIZONA_I2C1_BUSY_WIDTH 1 /* I2C1_BUSY */
1063 #define ARIZONA_SPI_BUSY 0x0010 /* SPI_BUSY */
1064 #define ARIZONA_SPI_BUSY_MASK 0x0010 /* SPI_BUSY */
1065 #define ARIZONA_SPI_BUSY_SHIFT 4 /* SPI_BUSY */
1066 #define ARIZONA_SPI_BUSY_WIDTH 1 /* SPI_BUSY */
1069 * R22 (0x16) - Write Sequencer Ctrl 0
1071 #define ARIZONA_WSEQ_ABORT 0x0800 /* WSEQ_ABORT */
1072 #define ARIZONA_WSEQ_ABORT_MASK 0x0800 /* WSEQ_ABORT */
1073 #define ARIZONA_WSEQ_ABORT_SHIFT 11 /* WSEQ_ABORT */
1074 #define ARIZONA_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
1075 #define ARIZONA_WSEQ_START 0x0400 /* WSEQ_START */
1076 #define ARIZONA_WSEQ_START_MASK 0x0400 /* WSEQ_START */
1077 #define ARIZONA_WSEQ_START_SHIFT 10 /* WSEQ_START */
1078 #define ARIZONA_WSEQ_START_WIDTH 1 /* WSEQ_START */
1079 #define ARIZONA_WSEQ_ENA 0x0200 /* WSEQ_ENA */
1080 #define ARIZONA_WSEQ_ENA_MASK 0x0200 /* WSEQ_ENA */
1081 #define ARIZONA_WSEQ_ENA_SHIFT 9 /* WSEQ_ENA */
1082 #define ARIZONA_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
1083 #define ARIZONA_WSEQ_START_INDEX_MASK 0x01FF /* WSEQ_START_INDEX - [8:0] */
1084 #define ARIZONA_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [8:0] */
1085 #define ARIZONA_WSEQ_START_INDEX_WIDTH 9 /* WSEQ_START_INDEX - [8:0] */
1088 * R23 (0x17) - Write Sequencer Ctrl 1
1090 #define ARIZONA_WSEQ_BUSY 0x0200 /* WSEQ_BUSY */
1091 #define ARIZONA_WSEQ_BUSY_MASK 0x0200 /* WSEQ_BUSY */
1092 #define ARIZONA_WSEQ_BUSY_SHIFT 9 /* WSEQ_BUSY */
1093 #define ARIZONA_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
1094 #define ARIZONA_WSEQ_CURRENT_INDEX_MASK 0x01FF /* WSEQ_CURRENT_INDEX - [8:0] */
1095 #define ARIZONA_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [8:0] */
1096 #define ARIZONA_WSEQ_CURRENT_INDEX_WIDTH 9 /* WSEQ_CURRENT_INDEX - [8:0] */
1099 * R24 (0x18) - Write Sequencer Ctrl 2
1101 #define ARIZONA_LOAD_DEFAULTS 0x0002 /* LOAD_DEFAULTS */
1102 #define ARIZONA_LOAD_DEFAULTS_MASK 0x0002 /* LOAD_DEFAULTS */
1103 #define ARIZONA_LOAD_DEFAULTS_SHIFT 1 /* LOAD_DEFAULTS */
1104 #define ARIZONA_LOAD_DEFAULTS_WIDTH 1 /* LOAD_DEFAULTS */
1105 #define ARIZONA_WSEQ_LOAD_MEM 0x0001 /* WSEQ_LOAD_MEM */
1106 #define ARIZONA_WSEQ_LOAD_MEM_MASK 0x0001 /* WSEQ_LOAD_MEM */
1107 #define ARIZONA_WSEQ_LOAD_MEM_SHIFT 0 /* WSEQ_LOAD_MEM */
1108 #define ARIZONA_WSEQ_LOAD_MEM_WIDTH 1 /* WSEQ_LOAD_MEM */
1111 * R26 (0x1A) - Write Sequencer PROM
1113 #define ARIZONA_WSEQ_OTP_WRITE 0x0001 /* WSEQ_OTP_WRITE */
1114 #define ARIZONA_WSEQ_OTP_WRITE_MASK 0x0001 /* WSEQ_OTP_WRITE */
1115 #define ARIZONA_WSEQ_OTP_WRITE_SHIFT 0 /* WSEQ_OTP_WRITE */
1116 #define ARIZONA_WSEQ_OTP_WRITE_WIDTH 1 /* WSEQ_OTP_WRITE */
1119 * R32 (0x20) - Tone Generator 1
1121 #define ARIZONA_TONE_RATE_MASK 0x7800 /* TONE_RATE - [14:11] */
1122 #define ARIZONA_TONE_RATE_SHIFT 11 /* TONE_RATE - [14:11] */
1123 #define ARIZONA_TONE_RATE_WIDTH 4 /* TONE_RATE - [14:11] */
1124 #define ARIZONA_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */
1125 #define ARIZONA_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */
1126 #define ARIZONA_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */
1127 #define ARIZONA_TONE2_OVD 0x0020 /* TONE2_OVD */
1128 #define ARIZONA_TONE2_OVD_MASK 0x0020 /* TONE2_OVD */
1129 #define ARIZONA_TONE2_OVD_SHIFT 5 /* TONE2_OVD */
1130 #define ARIZONA_TONE2_OVD_WIDTH 1 /* TONE2_OVD */
1131 #define ARIZONA_TONE1_OVD 0x0010 /* TONE1_OVD */
1132 #define ARIZONA_TONE1_OVD_MASK 0x0010 /* TONE1_OVD */
1133 #define ARIZONA_TONE1_OVD_SHIFT 4 /* TONE1_OVD */
1134 #define ARIZONA_TONE1_OVD_WIDTH 1 /* TONE1_OVD */
1135 #define ARIZONA_TONE2_ENA 0x0002 /* TONE2_ENA */
1136 #define ARIZONA_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */
1137 #define ARIZONA_TONE2_ENA_SHIFT 1 /* TONE2_ENA */
1138 #define ARIZONA_TONE2_ENA_WIDTH 1 /* TONE2_ENA */
1139 #define ARIZONA_TONE1_ENA 0x0001 /* TONE1_ENA */
1140 #define ARIZONA_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */
1141 #define ARIZONA_TONE1_ENA_SHIFT 0 /* TONE1_ENA */
1142 #define ARIZONA_TONE1_ENA_WIDTH 1 /* TONE1_ENA */
1145 * R33 (0x21) - Tone Generator 2
1147 #define ARIZONA_TONE1_LVL_0_MASK 0xFFFF /* TONE1_LVL - [15:0] */
1148 #define ARIZONA_TONE1_LVL_0_SHIFT 0 /* TONE1_LVL - [15:0] */
1149 #define ARIZONA_TONE1_LVL_0_WIDTH 16 /* TONE1_LVL - [15:0] */
1152 * R34 (0x22) - Tone Generator 3
1154 #define ARIZONA_TONE1_LVL_MASK 0x00FF /* TONE1_LVL - [7:0] */
1155 #define ARIZONA_TONE1_LVL_SHIFT 0 /* TONE1_LVL - [7:0] */
1156 #define ARIZONA_TONE1_LVL_WIDTH 8 /* TONE1_LVL - [7:0] */
1159 * R35 (0x23) - Tone Generator 4
1161 #define ARIZONA_TONE2_LVL_0_MASK 0xFFFF /* TONE2_LVL - [15:0] */
1162 #define ARIZONA_TONE2_LVL_0_SHIFT 0 /* TONE2_LVL - [15:0] */
1163 #define ARIZONA_TONE2_LVL_0_WIDTH 16 /* TONE2_LVL - [15:0] */
1166 * R36 (0x24) - Tone Generator 5
1168 #define ARIZONA_TONE2_LVL_MASK 0x00FF /* TONE2_LVL - [7:0] */
1169 #define ARIZONA_TONE2_LVL_SHIFT 0 /* TONE2_LVL - [7:0] */
1170 #define ARIZONA_TONE2_LVL_WIDTH 8 /* TONE2_LVL - [7:0] */
1173 * R48 (0x30) - PWM Drive 1
1175 #define ARIZONA_PWM_RATE_MASK 0x7800 /* PWM_RATE - [14:11] */
1176 #define ARIZONA_PWM_RATE_SHIFT 11 /* PWM_RATE - [14:11] */
1177 #define ARIZONA_PWM_RATE_WIDTH 4 /* PWM_RATE - [14:11] */
1178 #define ARIZONA_PWM_CLK_SEL_MASK 0x0700 /* PWM_CLK_SEL - [10:8] */
1179 #define ARIZONA_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [10:8] */
1180 #define ARIZONA_PWM_CLK_SEL_WIDTH 3 /* PWM_CLK_SEL - [10:8] */
1181 #define ARIZONA_PWM2_OVD 0x0020 /* PWM2_OVD */
1182 #define ARIZONA_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */
1183 #define ARIZONA_PWM2_OVD_SHIFT 5 /* PWM2_OVD */
1184 #define ARIZONA_PWM2_OVD_WIDTH 1 /* PWM2_OVD */
1185 #define ARIZONA_PWM1_OVD 0x0010 /* PWM1_OVD */
1186 #define ARIZONA_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */
1187 #define ARIZONA_PWM1_OVD_SHIFT 4 /* PWM1_OVD */
1188 #define ARIZONA_PWM1_OVD_WIDTH 1 /* PWM1_OVD */
1189 #define ARIZONA_PWM2_ENA 0x0002 /* PWM2_ENA */
1190 #define ARIZONA_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */
1191 #define ARIZONA_PWM2_ENA_SHIFT 1 /* PWM2_ENA */
1192 #define ARIZONA_PWM2_ENA_WIDTH 1 /* PWM2_ENA */
1193 #define ARIZONA_PWM1_ENA 0x0001 /* PWM1_ENA */
1194 #define ARIZONA_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */
1195 #define ARIZONA_PWM1_ENA_SHIFT 0 /* PWM1_ENA */
1196 #define ARIZONA_PWM1_ENA_WIDTH 1 /* PWM1_ENA */
1199 * R49 (0x31) - PWM Drive 2
1201 #define ARIZONA_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */
1202 #define ARIZONA_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */
1203 #define ARIZONA_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */
1206 * R50 (0x32) - PWM Drive 3
1208 #define ARIZONA_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */
1209 #define ARIZONA_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */
1210 #define ARIZONA_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */
1213 * R64 (0x40) - Wake control
1215 #define ARIZONA_WKUP_MICD_CLAMP_FALL 0x0080 /* WKUP_MICD_CLAMP_FALL */
1216 #define ARIZONA_WKUP_MICD_CLAMP_FALL_MASK 0x0080 /* WKUP_MICD_CLAMP_FALL */
1217 #define ARIZONA_WKUP_MICD_CLAMP_FALL_SHIFT 7 /* WKUP_MICD_CLAMP_FALL */
1218 #define ARIZONA_WKUP_MICD_CLAMP_FALL_WIDTH 1 /* WKUP_MICD_CLAMP_FALL */
1219 #define ARIZONA_WKUP_MICD_CLAMP_RISE 0x0040 /* WKUP_MICD_CLAMP_RISE */
1220 #define ARIZONA_WKUP_MICD_CLAMP_RISE_MASK 0x0040 /* WKUP_MICD_CLAMP_RISE */
1221 #define ARIZONA_WKUP_MICD_CLAMP_RISE_SHIFT 6 /* WKUP_MICD_CLAMP_RISE */
1222 #define ARIZONA_WKUP_MICD_CLAMP_RISE_WIDTH 1 /* WKUP_MICD_CLAMP_RISE */
1223 #define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */
1224 #define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */
1225 #define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */
1226 #define ARIZONA_WKUP_GP5_FALL_WIDTH 1 /* WKUP_GP5_FALL */
1227 #define ARIZONA_WKUP_GP5_RISE 0x0010 /* WKUP_GP5_RISE */
1228 #define ARIZONA_WKUP_GP5_RISE_MASK 0x0010 /* WKUP_GP5_RISE */
1229 #define ARIZONA_WKUP_GP5_RISE_SHIFT 4 /* WKUP_GP5_RISE */
1230 #define ARIZONA_WKUP_GP5_RISE_WIDTH 1 /* WKUP_GP5_RISE */
1231 #define ARIZONA_WKUP_JD1_FALL 0x0008 /* WKUP_JD1_FALL */
1232 #define ARIZONA_WKUP_JD1_FALL_MASK 0x0008 /* WKUP_JD1_FALL */
1233 #define ARIZONA_WKUP_JD1_FALL_SHIFT 3 /* WKUP_JD1_FALL */
1234 #define ARIZONA_WKUP_JD1_FALL_WIDTH 1 /* WKUP_JD1_FALL */
1235 #define ARIZONA_WKUP_JD1_RISE 0x0004 /* WKUP_JD1_RISE */
1236 #define ARIZONA_WKUP_JD1_RISE_MASK 0x0004 /* WKUP_JD1_RISE */
1237 #define ARIZONA_WKUP_JD1_RISE_SHIFT 2 /* WKUP_JD1_RISE */
1238 #define ARIZONA_WKUP_JD1_RISE_WIDTH 1 /* WKUP_JD1_RISE */
1239 #define ARIZONA_WKUP_JD2_FALL 0x0002 /* WKUP_JD2_FALL */
1240 #define ARIZONA_WKUP_JD2_FALL_MASK 0x0002 /* WKUP_JD2_FALL */
1241 #define ARIZONA_WKUP_JD2_FALL_SHIFT 1 /* WKUP_JD2_FALL */
1242 #define ARIZONA_WKUP_JD2_FALL_WIDTH 1 /* WKUP_JD2_FALL */
1243 #define ARIZONA_WKUP_JD2_RISE 0x0001 /* WKUP_JD2_RISE */
1244 #define ARIZONA_WKUP_JD2_RISE_MASK 0x0001 /* WKUP_JD2_RISE */
1245 #define ARIZONA_WKUP_JD2_RISE_SHIFT 0 /* WKUP_JD2_RISE */
1246 #define ARIZONA_WKUP_JD2_RISE_WIDTH 1 /* WKUP_JD2_RISE */
1249 * R65 (0x41) - Sequence control
1251 #define ARIZONA_WSEQ_ENA_GP5_FALL 0x0020 /* WSEQ_ENA_GP5_FALL */
1252 #define ARIZONA_WSEQ_ENA_GP5_FALL_MASK 0x0020 /* WSEQ_ENA_GP5_FALL */
1253 #define ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT 5 /* WSEQ_ENA_GP5_FALL */
1254 #define ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH 1 /* WSEQ_ENA_GP5_FALL */
1255 #define ARIZONA_WSEQ_ENA_GP5_RISE 0x0010 /* WSEQ_ENA_GP5_RISE */
1256 #define ARIZONA_WSEQ_ENA_GP5_RISE_MASK 0x0010 /* WSEQ_ENA_GP5_RISE */
1257 #define ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT 4 /* WSEQ_ENA_GP5_RISE */
1258 #define ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH 1 /* WSEQ_ENA_GP5_RISE */
1259 #define ARIZONA_WSEQ_ENA_JD1_FALL 0x0008 /* WSEQ_ENA_JD1_FALL */
1260 #define ARIZONA_WSEQ_ENA_JD1_FALL_MASK 0x0008 /* WSEQ_ENA_JD1_FALL */
1261 #define ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT 3 /* WSEQ_ENA_JD1_FALL */
1262 #define ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH 1 /* WSEQ_ENA_JD1_FALL */
1263 #define ARIZONA_WSEQ_ENA_JD1_RISE 0x0004 /* WSEQ_ENA_JD1_RISE */
1264 #define ARIZONA_WSEQ_ENA_JD1_RISE_MASK 0x0004 /* WSEQ_ENA_JD1_RISE */
1265 #define ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT 2 /* WSEQ_ENA_JD1_RISE */
1266 #define ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH 1 /* WSEQ_ENA_JD1_RISE */
1267 #define ARIZONA_WSEQ_ENA_JD2_FALL 0x0002 /* WSEQ_ENA_JD2_FALL */
1268 #define ARIZONA_WSEQ_ENA_JD2_FALL_MASK 0x0002 /* WSEQ_ENA_JD2_FALL */
1269 #define ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT 1 /* WSEQ_ENA_JD2_FALL */
1270 #define ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH 1 /* WSEQ_ENA_JD2_FALL */
1271 #define ARIZONA_WSEQ_ENA_JD2_RISE 0x0001 /* WSEQ_ENA_JD2_RISE */
1272 #define ARIZONA_WSEQ_ENA_JD2_RISE_MASK 0x0001 /* WSEQ_ENA_JD2_RISE */
1273 #define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT 0 /* WSEQ_ENA_JD2_RISE */
1274 #define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH 1 /* WSEQ_ENA_JD2_RISE */
1277 * R97 (0x61) - Sample Rate Sequence Select 1
1279 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
1280 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
1281 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
1284 * R98 (0x62) - Sample Rate Sequence Select 2
1286 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
1287 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
1288 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
1291 * R99 (0x63) - Sample Rate Sequence Select 3
1293 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
1294 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
1295 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
1298 * R100 (0x64) - Sample Rate Sequence Select 4
1300 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
1301 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
1302 #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
1305 * R104 (0x68) - Always On Triggers Sequence Select 1
1307 #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
1308 #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
1309 #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
1312 * R105 (0x69) - Always On Triggers Sequence Select 2
1314 #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
1315 #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
1316 #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
1319 * R106 (0x6A) - Always On Triggers Sequence Select 3
1321 #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
1322 #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
1323 #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
1326 * R107 (0x6B) - Always On Triggers Sequence Select 4
1328 #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
1329 #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
1330 #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
1333 * R108 (0x6C) - Always On Triggers Sequence Select 5
1335 #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
1336 #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
1337 #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
1340 * R109 (0x6D) - Always On Triggers Sequence Select 6
1342 #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
1343 #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
1344 #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
1347 * R112 (0x70) - Comfort Noise Generator
1349 #define ARIZONA_NOISE_GEN_RATE_MASK 0x7800 /* NOISE_GEN_RATE - [14:11] */
1350 #define ARIZONA_NOISE_GEN_RATE_SHIFT 11 /* NOISE_GEN_RATE - [14:11] */
1351 #define ARIZONA_NOISE_GEN_RATE_WIDTH 4 /* NOISE_GEN_RATE - [14:11] */
1352 #define ARIZONA_NOISE_GEN_ENA 0x0020 /* NOISE_GEN_ENA */
1353 #define ARIZONA_NOISE_GEN_ENA_MASK 0x0020 /* NOISE_GEN_ENA */
1354 #define ARIZONA_NOISE_GEN_ENA_SHIFT 5 /* NOISE_GEN_ENA */
1355 #define ARIZONA_NOISE_GEN_ENA_WIDTH 1 /* NOISE_GEN_ENA */
1356 #define ARIZONA_NOISE_GEN_GAIN_MASK 0x001F /* NOISE_GEN_GAIN - [4:0] */
1357 #define ARIZONA_NOISE_GEN_GAIN_SHIFT 0 /* NOISE_GEN_GAIN - [4:0] */
1358 #define ARIZONA_NOISE_GEN_GAIN_WIDTH 5 /* NOISE_GEN_GAIN - [4:0] */
1361 * R144 (0x90) - Haptics Control 1
1363 #define ARIZONA_HAP_RATE_MASK 0x7800 /* HAP_RATE - [14:11] */
1364 #define ARIZONA_HAP_RATE_SHIFT 11 /* HAP_RATE - [14:11] */
1365 #define ARIZONA_HAP_RATE_WIDTH 4 /* HAP_RATE - [14:11] */
1366 #define ARIZONA_ONESHOT_TRIG 0x0010 /* ONESHOT_TRIG */
1367 #define ARIZONA_ONESHOT_TRIG_MASK 0x0010 /* ONESHOT_TRIG */
1368 #define ARIZONA_ONESHOT_TRIG_SHIFT 4 /* ONESHOT_TRIG */
1369 #define ARIZONA_ONESHOT_TRIG_WIDTH 1 /* ONESHOT_TRIG */
1370 #define ARIZONA_HAP_CTRL_MASK 0x000C /* HAP_CTRL - [3:2] */
1371 #define ARIZONA_HAP_CTRL_SHIFT 2 /* HAP_CTRL - [3:2] */
1372 #define ARIZONA_HAP_CTRL_WIDTH 2 /* HAP_CTRL - [3:2] */
1373 #define ARIZONA_HAP_ACT 0x0002 /* HAP_ACT */
1374 #define ARIZONA_HAP_ACT_MASK 0x0002 /* HAP_ACT */
1375 #define ARIZONA_HAP_ACT_SHIFT 1 /* HAP_ACT */
1376 #define ARIZONA_HAP_ACT_WIDTH 1 /* HAP_ACT */
1379 * R145 (0x91) - Haptics Control 2
1381 #define ARIZONA_LRA_FREQ_MASK 0x7FFF /* LRA_FREQ - [14:0] */
1382 #define ARIZONA_LRA_FREQ_SHIFT 0 /* LRA_FREQ - [14:0] */
1383 #define ARIZONA_LRA_FREQ_WIDTH 15 /* LRA_FREQ - [14:0] */
1386 * R146 (0x92) - Haptics phase 1 intensity
1388 #define ARIZONA_PHASE1_INTENSITY_MASK 0x00FF /* PHASE1_INTENSITY - [7:0] */
1389 #define ARIZONA_PHASE1_INTENSITY_SHIFT 0 /* PHASE1_INTENSITY - [7:0] */
1390 #define ARIZONA_PHASE1_INTENSITY_WIDTH 8 /* PHASE1_INTENSITY - [7:0] */
1393 * R147 (0x93) - Haptics phase 1 duration
1395 #define ARIZONA_PHASE1_DURATION_MASK 0x01FF /* PHASE1_DURATION - [8:0] */
1396 #define ARIZONA_PHASE1_DURATION_SHIFT 0 /* PHASE1_DURATION - [8:0] */
1397 #define ARIZONA_PHASE1_DURATION_WIDTH 9 /* PHASE1_DURATION - [8:0] */
1400 * R148 (0x94) - Haptics phase 2 intensity
1402 #define ARIZONA_PHASE2_INTENSITY_MASK 0x00FF /* PHASE2_INTENSITY - [7:0] */
1403 #define ARIZONA_PHASE2_INTENSITY_SHIFT 0 /* PHASE2_INTENSITY - [7:0] */
1404 #define ARIZONA_PHASE2_INTENSITY_WIDTH 8 /* PHASE2_INTENSITY - [7:0] */
1407 * R149 (0x95) - Haptics phase 2 duration
1409 #define ARIZONA_PHASE2_DURATION_MASK 0x07FF /* PHASE2_DURATION - [10:0] */
1410 #define ARIZONA_PHASE2_DURATION_SHIFT 0 /* PHASE2_DURATION - [10:0] */
1411 #define ARIZONA_PHASE2_DURATION_WIDTH 11 /* PHASE2_DURATION - [10:0] */
1414 * R150 (0x96) - Haptics phase 3 intensity
1416 #define ARIZONA_PHASE3_INTENSITY_MASK 0x00FF /* PHASE3_INTENSITY - [7:0] */
1417 #define ARIZONA_PHASE3_INTENSITY_SHIFT 0 /* PHASE3_INTENSITY - [7:0] */
1418 #define ARIZONA_PHASE3_INTENSITY_WIDTH 8 /* PHASE3_INTENSITY - [7:0] */
1421 * R151 (0x97) - Haptics phase 3 duration
1423 #define ARIZONA_PHASE3_DURATION_MASK 0x01FF /* PHASE3_DURATION - [8:0] */
1424 #define ARIZONA_PHASE3_DURATION_SHIFT 0 /* PHASE3_DURATION - [8:0] */
1425 #define ARIZONA_PHASE3_DURATION_WIDTH 9 /* PHASE3_DURATION - [8:0] */
1428 * R152 (0x98) - Haptics Status
1430 #define ARIZONA_ONESHOT_STS 0x0001 /* ONESHOT_STS */
1431 #define ARIZONA_ONESHOT_STS_MASK 0x0001 /* ONESHOT_STS */
1432 #define ARIZONA_ONESHOT_STS_SHIFT 0 /* ONESHOT_STS */
1433 #define ARIZONA_ONESHOT_STS_WIDTH 1 /* ONESHOT_STS */
1436 * R256 (0x100) - Clock 32k 1
1438 #define ARIZONA_CLK_32K_ENA 0x0040 /* CLK_32K_ENA */
1439 #define ARIZONA_CLK_32K_ENA_MASK 0x0040 /* CLK_32K_ENA */
1440 #define ARIZONA_CLK_32K_ENA_SHIFT 6 /* CLK_32K_ENA */
1441 #define ARIZONA_CLK_32K_ENA_WIDTH 1 /* CLK_32K_ENA */
1442 #define ARIZONA_CLK_32K_SRC_MASK 0x0003 /* CLK_32K_SRC - [1:0] */
1443 #define ARIZONA_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [1:0] */
1444 #define ARIZONA_CLK_32K_SRC_WIDTH 2 /* CLK_32K_SRC - [1:0] */
1447 * R257 (0x101) - System Clock 1
1449 #define ARIZONA_SYSCLK_FRAC 0x8000 /* SYSCLK_FRAC */
1450 #define ARIZONA_SYSCLK_FRAC_MASK 0x8000 /* SYSCLK_FRAC */
1451 #define ARIZONA_SYSCLK_FRAC_SHIFT 15 /* SYSCLK_FRAC */
1452 #define ARIZONA_SYSCLK_FRAC_WIDTH 1 /* SYSCLK_FRAC */
1453 #define ARIZONA_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
1454 #define ARIZONA_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
1455 #define ARIZONA_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
1456 #define ARIZONA_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
1457 #define ARIZONA_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
1458 #define ARIZONA_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
1459 #define ARIZONA_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
1460 #define ARIZONA_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
1461 #define ARIZONA_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
1462 #define ARIZONA_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
1465 * R258 (0x102) - Sample rate 1
1467 #define ARIZONA_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
1468 #define ARIZONA_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
1469 #define ARIZONA_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
1472 * R259 (0x103) - Sample rate 2
1474 #define ARIZONA_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */
1475 #define ARIZONA_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */
1476 #define ARIZONA_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */
1479 * R260 (0x104) - Sample rate 3
1481 #define ARIZONA_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */
1482 #define ARIZONA_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */
1483 #define ARIZONA_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */
1486 * R266 (0x10A) - Sample rate 1 status
1488 #define ARIZONA_SAMPLE_RATE_1_STS_MASK 0x001F /* SAMPLE_RATE_1_STS - [4:0] */
1489 #define ARIZONA_SAMPLE_RATE_1_STS_SHIFT 0 /* SAMPLE_RATE_1_STS - [4:0] */
1490 #define ARIZONA_SAMPLE_RATE_1_STS_WIDTH 5 /* SAMPLE_RATE_1_STS - [4:0] */
1493 * R267 (0x10B) - Sample rate 2 status
1495 #define ARIZONA_SAMPLE_RATE_2_STS_MASK 0x001F /* SAMPLE_RATE_2_STS - [4:0] */
1496 #define ARIZONA_SAMPLE_RATE_2_STS_SHIFT 0 /* SAMPLE_RATE_2_STS - [4:0] */
1497 #define ARIZONA_SAMPLE_RATE_2_STS_WIDTH 5 /* SAMPLE_RATE_2_STS - [4:0] */
1500 * R268 (0x10C) - Sample rate 3 status
1502 #define ARIZONA_SAMPLE_RATE_3_STS_MASK 0x001F /* SAMPLE_RATE_3_STS - [4:0] */
1503 #define ARIZONA_SAMPLE_RATE_3_STS_SHIFT 0 /* SAMPLE_RATE_3_STS - [4:0] */
1504 #define ARIZONA_SAMPLE_RATE_3_STS_WIDTH 5 /* SAMPLE_RATE_3_STS - [4:0] */
1507 * R274 (0x112) - Async clock 1
1509 #define ARIZONA_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */
1510 #define ARIZONA_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */
1511 #define ARIZONA_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */
1512 #define ARIZONA_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */
1513 #define ARIZONA_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */
1514 #define ARIZONA_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */
1515 #define ARIZONA_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */
1516 #define ARIZONA_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */
1517 #define ARIZONA_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */
1518 #define ARIZONA_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */
1521 * R275 (0x113) - Async sample rate 1
1523 #define ARIZONA_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */
1524 #define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */
1525 #define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */
1528 * R283 (0x11B) - Async sample rate 1 status
1530 #define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_STS - [4:0] */
1531 #define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
1532 #define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
1535 * R329 (0x149) - Output system clock
1537 #define ARIZONA_OPCLK_ENA 0x8000 /* OPCLK_ENA */
1538 #define ARIZONA_OPCLK_ENA_MASK 0x8000 /* OPCLK_ENA */
1539 #define ARIZONA_OPCLK_ENA_SHIFT 15 /* OPCLK_ENA */
1540 #define ARIZONA_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
1541 #define ARIZONA_OPCLK_DIV_MASK 0x00F8 /* OPCLK_DIV - [7:3] */
1542 #define ARIZONA_OPCLK_DIV_SHIFT 3 /* OPCLK_DIV - [7:3] */
1543 #define ARIZONA_OPCLK_DIV_WIDTH 5 /* OPCLK_DIV - [7:3] */
1544 #define ARIZONA_OPCLK_SEL_MASK 0x0007 /* OPCLK_SEL - [2:0] */
1545 #define ARIZONA_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [2:0] */
1546 #define ARIZONA_OPCLK_SEL_WIDTH 3 /* OPCLK_SEL - [2:0] */
1549 * R330 (0x14A) - Output async clock
1551 #define ARIZONA_OPCLK_ASYNC_ENA 0x8000 /* OPCLK_ASYNC_ENA */
1552 #define ARIZONA_OPCLK_ASYNC_ENA_MASK 0x8000 /* OPCLK_ASYNC_ENA */
1553 #define ARIZONA_OPCLK_ASYNC_ENA_SHIFT 15 /* OPCLK_ASYNC_ENA */
1554 #define ARIZONA_OPCLK_ASYNC_ENA_WIDTH 1 /* OPCLK_ASYNC_ENA */
1555 #define ARIZONA_OPCLK_ASYNC_DIV_MASK 0x00F8 /* OPCLK_ASYNC_DIV - [7:3] */
1556 #define ARIZONA_OPCLK_ASYNC_DIV_SHIFT 3 /* OPCLK_ASYNC_DIV - [7:3] */
1557 #define ARIZONA_OPCLK_ASYNC_DIV_WIDTH 5 /* OPCLK_ASYNC_DIV - [7:3] */
1558 #define ARIZONA_OPCLK_ASYNC_SEL_MASK 0x0007 /* OPCLK_ASYNC_SEL - [2:0] */
1559 #define ARIZONA_OPCLK_ASYNC_SEL_SHIFT 0 /* OPCLK_ASYNC_SEL - [2:0] */
1560 #define ARIZONA_OPCLK_ASYNC_SEL_WIDTH 3 /* OPCLK_ASYNC_SEL - [2:0] */
1563 * R338 (0x152) - Rate Estimator 1
1565 #define ARIZONA_TRIG_ON_STARTUP 0x0010 /* TRIG_ON_STARTUP */
1566 #define ARIZONA_TRIG_ON_STARTUP_MASK 0x0010 /* TRIG_ON_STARTUP */
1567 #define ARIZONA_TRIG_ON_STARTUP_SHIFT 4 /* TRIG_ON_STARTUP */
1568 #define ARIZONA_TRIG_ON_STARTUP_WIDTH 1 /* TRIG_ON_STARTUP */
1569 #define ARIZONA_LRCLK_SRC_MASK 0x000E /* LRCLK_SRC - [3:1] */
1570 #define ARIZONA_LRCLK_SRC_SHIFT 1 /* LRCLK_SRC - [3:1] */
1571 #define ARIZONA_LRCLK_SRC_WIDTH 3 /* LRCLK_SRC - [3:1] */
1572 #define ARIZONA_RATE_EST_ENA 0x0001 /* RATE_EST_ENA */
1573 #define ARIZONA_RATE_EST_ENA_MASK 0x0001 /* RATE_EST_ENA */
1574 #define ARIZONA_RATE_EST_ENA_SHIFT 0 /* RATE_EST_ENA */
1575 #define ARIZONA_RATE_EST_ENA_WIDTH 1 /* RATE_EST_ENA */
1578 * R339 (0x153) - Rate Estimator 2
1580 #define ARIZONA_SAMPLE_RATE_DETECT_A_MASK 0x001F /* SAMPLE_RATE_DETECT_A - [4:0] */
1581 #define ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT 0 /* SAMPLE_RATE_DETECT_A - [4:0] */
1582 #define ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH 5 /* SAMPLE_RATE_DETECT_A - [4:0] */
1585 * R340 (0x154) - Rate Estimator 3
1587 #define ARIZONA_SAMPLE_RATE_DETECT_B_MASK 0x001F /* SAMPLE_RATE_DETECT_B - [4:0] */
1588 #define ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT 0 /* SAMPLE_RATE_DETECT_B - [4:0] */
1589 #define ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH 5 /* SAMPLE_RATE_DETECT_B - [4:0] */
1592 * R341 (0x155) - Rate Estimator 4
1594 #define ARIZONA_SAMPLE_RATE_DETECT_C_MASK 0x001F /* SAMPLE_RATE_DETECT_C - [4:0] */
1595 #define ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT 0 /* SAMPLE_RATE_DETECT_C - [4:0] */
1596 #define ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH 5 /* SAMPLE_RATE_DETECT_C - [4:0] */
1599 * R342 (0x156) - Rate Estimator 5
1601 #define ARIZONA_SAMPLE_RATE_DETECT_D_MASK 0x001F /* SAMPLE_RATE_DETECT_D - [4:0] */
1602 #define ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT 0 /* SAMPLE_RATE_DETECT_D - [4:0] */
1603 #define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */
1606 * R353 (0x161) - Dynamic Frequency Scaling 1
1608 #define ARIZONA_SUBSYS_MAX_FREQ 0x0001 /* SUBSYS_MAX_FREQ */
1609 #define ARIZONA_SUBSYS_MAX_FREQ_SHIFT 0 /* SUBSYS_MAX_FREQ */
1610 #define ARIZONA_SUBSYS_MAX_FREQ_WIDTH 1 /* SUBSYS_MAX_FREQ */
1613 * R369 (0x171) - FLL1 Control 1
1615 #define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */
1616 #define ARIZONA_FLL1_FREERUN_MASK 0x0002 /* FLL1_FREERUN */
1617 #define ARIZONA_FLL1_FREERUN_SHIFT 1 /* FLL1_FREERUN */
1618 #define ARIZONA_FLL1_FREERUN_WIDTH 1 /* FLL1_FREERUN */
1619 #define ARIZONA_FLL1_ENA 0x0001 /* FLL1_ENA */
1620 #define ARIZONA_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
1621 #define ARIZONA_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
1622 #define ARIZONA_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
1625 * R370 (0x172) - FLL1 Control 2
1627 #define ARIZONA_FLL1_CTRL_UPD 0x8000 /* FLL1_CTRL_UPD */
1628 #define ARIZONA_FLL1_CTRL_UPD_MASK 0x8000 /* FLL1_CTRL_UPD */
1629 #define ARIZONA_FLL1_CTRL_UPD_SHIFT 15 /* FLL1_CTRL_UPD */
1630 #define ARIZONA_FLL1_CTRL_UPD_WIDTH 1 /* FLL1_CTRL_UPD */
1631 #define ARIZONA_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */
1632 #define ARIZONA_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */
1633 #define ARIZONA_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */
1636 * R371 (0x173) - FLL1 Control 3
1638 #define ARIZONA_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
1639 #define ARIZONA_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
1640 #define ARIZONA_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
1643 * R372 (0x174) - FLL1 Control 4
1645 #define ARIZONA_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
1646 #define ARIZONA_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
1647 #define ARIZONA_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
1650 * R373 (0x175) - FLL1 Control 5
1652 #define ARIZONA_FLL1_FRATIO_MASK 0x0700 /* FLL1_FRATIO - [10:8] */
1653 #define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [10:8] */
1654 #define ARIZONA_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [10:8] */
1655 #define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */
1656 #define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */
1657 #define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */
1660 * R374 (0x176) - FLL1 Control 6
1662 #define ARIZONA_FLL1_CLK_REF_DIV_MASK 0x00C0 /* FLL1_CLK_REF_DIV - [7:6] */
1663 #define ARIZONA_FLL1_CLK_REF_DIV_SHIFT 6 /* FLL1_CLK_REF_DIV - [7:6] */
1664 #define ARIZONA_FLL1_CLK_REF_DIV_WIDTH 2 /* FLL1_CLK_REF_DIV - [7:6] */
1665 #define ARIZONA_FLL1_CLK_REF_SRC_MASK 0x000F /* FLL1_CLK_REF_SRC - [3:0] */
1666 #define ARIZONA_FLL1_CLK_REF_SRC_SHIFT 0 /* FLL1_CLK_REF_SRC - [3:0] */
1667 #define ARIZONA_FLL1_CLK_REF_SRC_WIDTH 4 /* FLL1_CLK_REF_SRC - [3:0] */
1670 * R375 (0x177) - FLL1 Loop Filter Test 1
1672 #define ARIZONA_FLL1_FRC_INTEG_UPD 0x8000 /* FLL1_FRC_INTEG_UPD */
1673 #define ARIZONA_FLL1_FRC_INTEG_UPD_MASK 0x8000 /* FLL1_FRC_INTEG_UPD */
1674 #define ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT 15 /* FLL1_FRC_INTEG_UPD */
1675 #define ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH 1 /* FLL1_FRC_INTEG_UPD */
1676 #define ARIZONA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF /* FLL1_FRC_INTEG_VAL - [11:0] */
1677 #define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT 0 /* FLL1_FRC_INTEG_VAL - [11:0] */
1678 #define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */
1681 * R385 (0x181) - FLL1 Synchroniser 1
1683 #define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */
1684 #define ARIZONA_FLL1_SYNC_ENA_MASK 0x0001 /* FLL1_SYNC_ENA */
1685 #define ARIZONA_FLL1_SYNC_ENA_SHIFT 0 /* FLL1_SYNC_ENA */
1686 #define ARIZONA_FLL1_SYNC_ENA_WIDTH 1 /* FLL1_SYNC_ENA */
1689 * R386 (0x182) - FLL1 Synchroniser 2
1691 #define ARIZONA_FLL1_SYNC_N_MASK 0x03FF /* FLL1_SYNC_N - [9:0] */
1692 #define ARIZONA_FLL1_SYNC_N_SHIFT 0 /* FLL1_SYNC_N - [9:0] */
1693 #define ARIZONA_FLL1_SYNC_N_WIDTH 10 /* FLL1_SYNC_N - [9:0] */
1696 * R387 (0x183) - FLL1 Synchroniser 3
1698 #define ARIZONA_FLL1_SYNC_THETA_MASK 0xFFFF /* FLL1_SYNC_THETA - [15:0] */
1699 #define ARIZONA_FLL1_SYNC_THETA_SHIFT 0 /* FLL1_SYNC_THETA - [15:0] */
1700 #define ARIZONA_FLL1_SYNC_THETA_WIDTH 16 /* FLL1_SYNC_THETA - [15:0] */
1703 * R388 (0x184) - FLL1 Synchroniser 4
1705 #define ARIZONA_FLL1_SYNC_LAMBDA_MASK 0xFFFF /* FLL1_SYNC_LAMBDA - [15:0] */
1706 #define ARIZONA_FLL1_SYNC_LAMBDA_SHIFT 0 /* FLL1_SYNC_LAMBDA - [15:0] */
1707 #define ARIZONA_FLL1_SYNC_LAMBDA_WIDTH 16 /* FLL1_SYNC_LAMBDA - [15:0] */
1710 * R389 (0x185) - FLL1 Synchroniser 5
1712 #define ARIZONA_FLL1_SYNC_FRATIO_MASK 0x0700 /* FLL1_SYNC_FRATIO - [10:8] */
1713 #define ARIZONA_FLL1_SYNC_FRATIO_SHIFT 8 /* FLL1_SYNC_FRATIO - [10:8] */
1714 #define ARIZONA_FLL1_SYNC_FRATIO_WIDTH 3 /* FLL1_SYNC_FRATIO - [10:8] */
1717 * R390 (0x186) - FLL1 Synchroniser 6
1719 #define ARIZONA_FLL1_CLK_SYNC_DIV_MASK 0x00C0 /* FLL1_CLK_SYNC_DIV - [7:6] */
1720 #define ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT 6 /* FLL1_CLK_SYNC_DIV - [7:6] */
1721 #define ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH 2 /* FLL1_CLK_SYNC_DIV - [7:6] */
1722 #define ARIZONA_FLL1_CLK_SYNC_SRC_MASK 0x000F /* FLL1_CLK_SYNC_SRC - [3:0] */
1723 #define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT 0 /* FLL1_CLK_SYNC_SRC - [3:0] */
1724 #define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */
1727 * R393 (0x189) - FLL1 Spread Spectrum
1729 #define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */
1730 #define ARIZONA_FLL1_SS_AMPL_SHIFT 4 /* FLL1_SS_AMPL - [5:4] */
1731 #define ARIZONA_FLL1_SS_AMPL_WIDTH 2 /* FLL1_SS_AMPL - [5:4] */
1732 #define ARIZONA_FLL1_SS_FREQ_MASK 0x000C /* FLL1_SS_FREQ - [3:2] */
1733 #define ARIZONA_FLL1_SS_FREQ_SHIFT 2 /* FLL1_SS_FREQ - [3:2] */
1734 #define ARIZONA_FLL1_SS_FREQ_WIDTH 2 /* FLL1_SS_FREQ - [3:2] */
1735 #define ARIZONA_FLL1_SS_SEL_MASK 0x0003 /* FLL1_SS_SEL - [1:0] */
1736 #define ARIZONA_FLL1_SS_SEL_SHIFT 0 /* FLL1_SS_SEL - [1:0] */
1737 #define ARIZONA_FLL1_SS_SEL_WIDTH 2 /* FLL1_SS_SEL - [1:0] */
1740 * R394 (0x18A) - FLL1 GPIO Clock
1742 #define ARIZONA_FLL1_GPDIV_MASK 0x00FE /* FLL1_GPDIV - [7:1] */
1743 #define ARIZONA_FLL1_GPDIV_SHIFT 1 /* FLL1_GPDIV - [7:1] */
1744 #define ARIZONA_FLL1_GPDIV_WIDTH 7 /* FLL1_GPDIV - [7:1] */
1745 #define ARIZONA_FLL1_GPDIV_ENA 0x0001 /* FLL1_GPDIV_ENA */
1746 #define ARIZONA_FLL1_GPDIV_ENA_MASK 0x0001 /* FLL1_GPDIV_ENA */
1747 #define ARIZONA_FLL1_GPDIV_ENA_SHIFT 0 /* FLL1_GPDIV_ENA */
1748 #define ARIZONA_FLL1_GPDIV_ENA_WIDTH 1 /* FLL1_GPDIV_ENA */
1751 * R401 (0x191) - FLL2 Control 1
1753 #define ARIZONA_FLL2_FREERUN 0x0002 /* FLL2_FREERUN */
1754 #define ARIZONA_FLL2_FREERUN_MASK 0x0002 /* FLL2_FREERUN */
1755 #define ARIZONA_FLL2_FREERUN_SHIFT 1 /* FLL2_FREERUN */
1756 #define ARIZONA_FLL2_FREERUN_WIDTH 1 /* FLL2_FREERUN */
1757 #define ARIZONA_FLL2_ENA 0x0001 /* FLL2_ENA */
1758 #define ARIZONA_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
1759 #define ARIZONA_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
1760 #define ARIZONA_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
1763 * R402 (0x192) - FLL2 Control 2
1765 #define ARIZONA_FLL2_CTRL_UPD 0x8000 /* FLL2_CTRL_UPD */
1766 #define ARIZONA_FLL2_CTRL_UPD_MASK 0x8000 /* FLL2_CTRL_UPD */
1767 #define ARIZONA_FLL2_CTRL_UPD_SHIFT 15 /* FLL2_CTRL_UPD */
1768 #define ARIZONA_FLL2_CTRL_UPD_WIDTH 1 /* FLL2_CTRL_UPD */
1769 #define ARIZONA_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */
1770 #define ARIZONA_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */
1771 #define ARIZONA_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */
1774 * R403 (0x193) - FLL2 Control 3
1776 #define ARIZONA_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */
1777 #define ARIZONA_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */
1778 #define ARIZONA_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */
1781 * R404 (0x194) - FLL2 Control 4
1783 #define ARIZONA_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
1784 #define ARIZONA_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
1785 #define ARIZONA_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
1788 * R405 (0x195) - FLL2 Control 5
1790 #define ARIZONA_FLL2_FRATIO_MASK 0x0700 /* FLL2_FRATIO - [10:8] */
1791 #define ARIZONA_FLL2_FRATIO_SHIFT 8 /* FLL2_FRATIO - [10:8] */
1792 #define ARIZONA_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [10:8] */
1793 #define ARIZONA_FLL2_OUTDIV_MASK 0x000E /* FLL2_OUTDIV - [3:1] */
1794 #define ARIZONA_FLL2_OUTDIV_SHIFT 1 /* FLL2_OUTDIV - [3:1] */
1795 #define ARIZONA_FLL2_OUTDIV_WIDTH 3 /* FLL2_OUTDIV - [3:1] */
1798 * R406 (0x196) - FLL2 Control 6
1800 #define ARIZONA_FLL2_CLK_REF_DIV_MASK 0x00C0 /* FLL2_CLK_REF_DIV - [7:6] */
1801 #define ARIZONA_FLL2_CLK_REF_DIV_SHIFT 6 /* FLL2_CLK_REF_DIV - [7:6] */
1802 #define ARIZONA_FLL2_CLK_REF_DIV_WIDTH 2 /* FLL2_CLK_REF_DIV - [7:6] */
1803 #define ARIZONA_FLL2_CLK_REF_SRC_MASK 0x000F /* FLL2_CLK_REF_SRC - [3:0] */
1804 #define ARIZONA_FLL2_CLK_REF_SRC_SHIFT 0 /* FLL2_CLK_REF_SRC - [3:0] */
1805 #define ARIZONA_FLL2_CLK_REF_SRC_WIDTH 4 /* FLL2_CLK_REF_SRC - [3:0] */
1808 * R407 (0x197) - FLL2 Loop Filter Test 1
1810 #define ARIZONA_FLL2_FRC_INTEG_UPD 0x8000 /* FLL2_FRC_INTEG_UPD */
1811 #define ARIZONA_FLL2_FRC_INTEG_UPD_MASK 0x8000 /* FLL2_FRC_INTEG_UPD */
1812 #define ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT 15 /* FLL2_FRC_INTEG_UPD */
1813 #define ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH 1 /* FLL2_FRC_INTEG_UPD */
1814 #define ARIZONA_FLL2_FRC_INTEG_VAL_MASK 0x0FFF /* FLL2_FRC_INTEG_VAL - [11:0] */
1815 #define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT 0 /* FLL2_FRC_INTEG_VAL - [11:0] */
1816 #define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */
1819 * R417 (0x1A1) - FLL2 Synchroniser 1
1821 #define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */
1822 #define ARIZONA_FLL2_SYNC_ENA_MASK 0x0001 /* FLL2_SYNC_ENA */
1823 #define ARIZONA_FLL2_SYNC_ENA_SHIFT 0 /* FLL2_SYNC_ENA */
1824 #define ARIZONA_FLL2_SYNC_ENA_WIDTH 1 /* FLL2_SYNC_ENA */
1827 * R418 (0x1A2) - FLL2 Synchroniser 2
1829 #define ARIZONA_FLL2_SYNC_N_MASK 0x03FF /* FLL2_SYNC_N - [9:0] */
1830 #define ARIZONA_FLL2_SYNC_N_SHIFT 0 /* FLL2_SYNC_N - [9:0] */
1831 #define ARIZONA_FLL2_SYNC_N_WIDTH 10 /* FLL2_SYNC_N - [9:0] */
1834 * R419 (0x1A3) - FLL2 Synchroniser 3
1836 #define ARIZONA_FLL2_SYNC_THETA_MASK 0xFFFF /* FLL2_SYNC_THETA - [15:0] */
1837 #define ARIZONA_FLL2_SYNC_THETA_SHIFT 0 /* FLL2_SYNC_THETA - [15:0] */
1838 #define ARIZONA_FLL2_SYNC_THETA_WIDTH 16 /* FLL2_SYNC_THETA - [15:0] */
1841 * R420 (0x1A4) - FLL2 Synchroniser 4
1843 #define ARIZONA_FLL2_SYNC_LAMBDA_MASK 0xFFFF /* FLL2_SYNC_LAMBDA - [15:0] */
1844 #define ARIZONA_FLL2_SYNC_LAMBDA_SHIFT 0 /* FLL2_SYNC_LAMBDA - [15:0] */
1845 #define ARIZONA_FLL2_SYNC_LAMBDA_WIDTH 16 /* FLL2_SYNC_LAMBDA - [15:0] */
1848 * R421 (0x1A5) - FLL2 Synchroniser 5
1850 #define ARIZONA_FLL2_SYNC_FRATIO_MASK 0x0700 /* FLL2_SYNC_FRATIO - [10:8] */
1851 #define ARIZONA_FLL2_SYNC_FRATIO_SHIFT 8 /* FLL2_SYNC_FRATIO - [10:8] */
1852 #define ARIZONA_FLL2_SYNC_FRATIO_WIDTH 3 /* FLL2_SYNC_FRATIO - [10:8] */
1855 * R422 (0x1A6) - FLL2 Synchroniser 6
1857 #define ARIZONA_FLL2_CLK_SYNC_DIV_MASK 0x00C0 /* FLL2_CLK_SYNC_DIV - [7:6] */
1858 #define ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT 6 /* FLL2_CLK_SYNC_DIV - [7:6] */
1859 #define ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH 2 /* FLL2_CLK_SYNC_DIV - [7:6] */
1860 #define ARIZONA_FLL2_CLK_SYNC_SRC_MASK 0x000F /* FLL2_CLK_SYNC_SRC - [3:0] */
1861 #define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT 0 /* FLL2_CLK_SYNC_SRC - [3:0] */
1862 #define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */
1865 * R425 (0x1A9) - FLL2 Spread Spectrum
1867 #define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */
1868 #define ARIZONA_FLL2_SS_AMPL_SHIFT 4 /* FLL2_SS_AMPL - [5:4] */
1869 #define ARIZONA_FLL2_SS_AMPL_WIDTH 2 /* FLL2_SS_AMPL - [5:4] */
1870 #define ARIZONA_FLL2_SS_FREQ_MASK 0x000C /* FLL2_SS_FREQ - [3:2] */
1871 #define ARIZONA_FLL2_SS_FREQ_SHIFT 2 /* FLL2_SS_FREQ - [3:2] */
1872 #define ARIZONA_FLL2_SS_FREQ_WIDTH 2 /* FLL2_SS_FREQ - [3:2] */
1873 #define ARIZONA_FLL2_SS_SEL_MASK 0x0003 /* FLL2_SS_SEL - [1:0] */
1874 #define ARIZONA_FLL2_SS_SEL_SHIFT 0 /* FLL2_SS_SEL - [1:0] */
1875 #define ARIZONA_FLL2_SS_SEL_WIDTH 2 /* FLL2_SS_SEL - [1:0] */
1878 * R426 (0x1AA) - FLL2 GPIO Clock
1880 #define ARIZONA_FLL2_GPDIV_MASK 0x00FE /* FLL2_GPDIV - [7:1] */
1881 #define ARIZONA_FLL2_GPDIV_SHIFT 1 /* FLL2_GPDIV - [7:1] */
1882 #define ARIZONA_FLL2_GPDIV_WIDTH 7 /* FLL2_GPDIV - [7:1] */
1883 #define ARIZONA_FLL2_GPDIV_ENA 0x0001 /* FLL2_GPDIV_ENA */
1884 #define ARIZONA_FLL2_GPDIV_ENA_MASK 0x0001 /* FLL2_GPDIV_ENA */
1885 #define ARIZONA_FLL2_GPDIV_ENA_SHIFT 0 /* FLL2_GPDIV_ENA */
1886 #define ARIZONA_FLL2_GPDIV_ENA_WIDTH 1 /* FLL2_GPDIV_ENA */
1889 * R512 (0x200) - Mic Charge Pump 1
1891 #define ARIZONA_CPMIC_DISCH 0x0004 /* CPMIC_DISCH */
1892 #define ARIZONA_CPMIC_DISCH_MASK 0x0004 /* CPMIC_DISCH */
1893 #define ARIZONA_CPMIC_DISCH_SHIFT 2 /* CPMIC_DISCH */
1894 #define ARIZONA_CPMIC_DISCH_WIDTH 1 /* CPMIC_DISCH */
1895 #define ARIZONA_CPMIC_BYPASS 0x0002 /* CPMIC_BYPASS */
1896 #define ARIZONA_CPMIC_BYPASS_MASK 0x0002 /* CPMIC_BYPASS */
1897 #define ARIZONA_CPMIC_BYPASS_SHIFT 1 /* CPMIC_BYPASS */
1898 #define ARIZONA_CPMIC_BYPASS_WIDTH 1 /* CPMIC_BYPASS */
1899 #define ARIZONA_CPMIC_ENA 0x0001 /* CPMIC_ENA */
1900 #define ARIZONA_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */
1901 #define ARIZONA_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */
1902 #define ARIZONA_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */
1905 * R528 (0x210) - LDO1 Control 1
1907 #define ARIZONA_LDO1_VSEL_MASK 0x07E0 /* LDO1_VSEL - [10:5] */
1908 #define ARIZONA_LDO1_VSEL_SHIFT 5 /* LDO1_VSEL - [10:5] */
1909 #define ARIZONA_LDO1_VSEL_WIDTH 6 /* LDO1_VSEL - [10:5] */
1910 #define ARIZONA_LDO1_FAST 0x0010 /* LDO1_FAST */
1911 #define ARIZONA_LDO1_FAST_MASK 0x0010 /* LDO1_FAST */
1912 #define ARIZONA_LDO1_FAST_SHIFT 4 /* LDO1_FAST */
1913 #define ARIZONA_LDO1_FAST_WIDTH 1 /* LDO1_FAST */
1914 #define ARIZONA_LDO1_DISCH 0x0004 /* LDO1_DISCH */
1915 #define ARIZONA_LDO1_DISCH_MASK 0x0004 /* LDO1_DISCH */
1916 #define ARIZONA_LDO1_DISCH_SHIFT 2 /* LDO1_DISCH */
1917 #define ARIZONA_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
1918 #define ARIZONA_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */
1919 #define ARIZONA_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */
1920 #define ARIZONA_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */
1921 #define ARIZONA_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */
1922 #define ARIZONA_LDO1_ENA 0x0001 /* LDO1_ENA */
1923 #define ARIZONA_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
1924 #define ARIZONA_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
1925 #define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
1928 * R530 (0x212) - LDO1 Control 2
1930 #define ARIZONA_LDO1_HI_PWR 0x0001 /* LDO1_HI_PWR */
1931 #define ARIZONA_LDO1_HI_PWR_SHIFT 0 /* LDO1_HI_PWR */
1932 #define ARIZONA_LDO1_HI_PWR_WIDTH 1 /* LDO1_HI_PWR */
1935 * R531 (0x213) - LDO2 Control 1
1937 #define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */
1938 #define ARIZONA_LDO2_VSEL_SHIFT 5 /* LDO2_VSEL - [10:5] */
1939 #define ARIZONA_LDO2_VSEL_WIDTH 6 /* LDO2_VSEL - [10:5] */
1940 #define ARIZONA_LDO2_FAST 0x0010 /* LDO2_FAST */
1941 #define ARIZONA_LDO2_FAST_MASK 0x0010 /* LDO2_FAST */
1942 #define ARIZONA_LDO2_FAST_SHIFT 4 /* LDO2_FAST */
1943 #define ARIZONA_LDO2_FAST_WIDTH 1 /* LDO2_FAST */
1944 #define ARIZONA_LDO2_DISCH 0x0004 /* LDO2_DISCH */
1945 #define ARIZONA_LDO2_DISCH_MASK 0x0004 /* LDO2_DISCH */
1946 #define ARIZONA_LDO2_DISCH_SHIFT 2 /* LDO2_DISCH */
1947 #define ARIZONA_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
1948 #define ARIZONA_LDO2_BYPASS 0x0002 /* LDO2_BYPASS */
1949 #define ARIZONA_LDO2_BYPASS_MASK 0x0002 /* LDO2_BYPASS */
1950 #define ARIZONA_LDO2_BYPASS_SHIFT 1 /* LDO2_BYPASS */
1951 #define ARIZONA_LDO2_BYPASS_WIDTH 1 /* LDO2_BYPASS */
1952 #define ARIZONA_LDO2_ENA 0x0001 /* LDO2_ENA */
1953 #define ARIZONA_LDO2_ENA_MASK 0x0001 /* LDO2_ENA */
1954 #define ARIZONA_LDO2_ENA_SHIFT 0 /* LDO2_ENA */
1955 #define ARIZONA_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
1958 * R536 (0x218) - Mic Bias Ctrl 1
1960 #define ARIZONA_MICB1_EXT_CAP 0x8000 /* MICB1_EXT_CAP */
1961 #define ARIZONA_MICB1_EXT_CAP_MASK 0x8000 /* MICB1_EXT_CAP */
1962 #define ARIZONA_MICB1_EXT_CAP_SHIFT 15 /* MICB1_EXT_CAP */
1963 #define ARIZONA_MICB1_EXT_CAP_WIDTH 1 /* MICB1_EXT_CAP */
1964 #define ARIZONA_MICB1_LVL_MASK 0x01E0 /* MICB1_LVL - [8:5] */
1965 #define ARIZONA_MICB1_LVL_SHIFT 5 /* MICB1_LVL - [8:5] */
1966 #define ARIZONA_MICB1_LVL_WIDTH 4 /* MICB1_LVL - [8:5] */
1967 #define ARIZONA_MICB1_FAST 0x0010 /* MICB1_FAST */
1968 #define ARIZONA_MICB1_FAST_MASK 0x0010 /* MICB1_FAST */
1969 #define ARIZONA_MICB1_FAST_SHIFT 4 /* MICB1_FAST */
1970 #define ARIZONA_MICB1_FAST_WIDTH 1 /* MICB1_FAST */
1971 #define ARIZONA_MICB1_RATE 0x0008 /* MICB1_RATE */
1972 #define ARIZONA_MICB1_RATE_MASK 0x0008 /* MICB1_RATE */
1973 #define ARIZONA_MICB1_RATE_SHIFT 3 /* MICB1_RATE */
1974 #define ARIZONA_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
1975 #define ARIZONA_MICB1_DISCH 0x0004 /* MICB1_DISCH */
1976 #define ARIZONA_MICB1_DISCH_MASK 0x0004 /* MICB1_DISCH */
1977 #define ARIZONA_MICB1_DISCH_SHIFT 2 /* MICB1_DISCH */
1978 #define ARIZONA_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
1979 #define ARIZONA_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */
1980 #define ARIZONA_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */
1981 #define ARIZONA_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */
1982 #define ARIZONA_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */
1983 #define ARIZONA_MICB1_ENA 0x0001 /* MICB1_ENA */
1984 #define ARIZONA_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
1985 #define ARIZONA_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
1986 #define ARIZONA_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
1989 * R537 (0x219) - Mic Bias Ctrl 2
1991 #define ARIZONA_MICB2_EXT_CAP 0x8000 /* MICB2_EXT_CAP */
1992 #define ARIZONA_MICB2_EXT_CAP_MASK 0x8000 /* MICB2_EXT_CAP */
1993 #define ARIZONA_MICB2_EXT_CAP_SHIFT 15 /* MICB2_EXT_CAP */
1994 #define ARIZONA_MICB2_EXT_CAP_WIDTH 1 /* MICB2_EXT_CAP */
1995 #define ARIZONA_MICB2_LVL_MASK 0x01E0 /* MICB2_LVL - [8:5] */
1996 #define ARIZONA_MICB2_LVL_SHIFT 5 /* MICB2_LVL - [8:5] */
1997 #define ARIZONA_MICB2_LVL_WIDTH 4 /* MICB2_LVL - [8:5] */
1998 #define ARIZONA_MICB2_FAST 0x0010 /* MICB2_FAST */
1999 #define ARIZONA_MICB2_FAST_MASK 0x0010 /* MICB2_FAST */
2000 #define ARIZONA_MICB2_FAST_SHIFT 4 /* MICB2_FAST */
2001 #define ARIZONA_MICB2_FAST_WIDTH 1 /* MICB2_FAST */
2002 #define ARIZONA_MICB2_RATE 0x0008 /* MICB2_RATE */
2003 #define ARIZONA_MICB2_RATE_MASK 0x0008 /* MICB2_RATE */
2004 #define ARIZONA_MICB2_RATE_SHIFT 3 /* MICB2_RATE */
2005 #define ARIZONA_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
2006 #define ARIZONA_MICB2_DISCH 0x0004 /* MICB2_DISCH */
2007 #define ARIZONA_MICB2_DISCH_MASK 0x0004 /* MICB2_DISCH */
2008 #define ARIZONA_MICB2_DISCH_SHIFT 2 /* MICB2_DISCH */
2009 #define ARIZONA_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
2010 #define ARIZONA_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */
2011 #define ARIZONA_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */
2012 #define ARIZONA_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */
2013 #define ARIZONA_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */
2014 #define ARIZONA_MICB2_ENA 0x0001 /* MICB2_ENA */
2015 #define ARIZONA_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
2016 #define ARIZONA_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
2017 #define ARIZONA_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
2020 * R538 (0x21A) - Mic Bias Ctrl 3
2022 #define ARIZONA_MICB3_EXT_CAP 0x8000 /* MICB3_EXT_CAP */
2023 #define ARIZONA_MICB3_EXT_CAP_MASK 0x8000 /* MICB3_EXT_CAP */
2024 #define ARIZONA_MICB3_EXT_CAP_SHIFT 15 /* MICB3_EXT_CAP */
2025 #define ARIZONA_MICB3_EXT_CAP_WIDTH 1 /* MICB3_EXT_CAP */
2026 #define ARIZONA_MICB3_LVL_MASK 0x01E0 /* MICB3_LVL - [8:5] */
2027 #define ARIZONA_MICB3_LVL_SHIFT 5 /* MICB3_LVL - [8:5] */
2028 #define ARIZONA_MICB3_LVL_WIDTH 4 /* MICB3_LVL - [8:5] */
2029 #define ARIZONA_MICB3_FAST 0x0010 /* MICB3_FAST */
2030 #define ARIZONA_MICB3_FAST_MASK 0x0010 /* MICB3_FAST */
2031 #define ARIZONA_MICB3_FAST_SHIFT 4 /* MICB3_FAST */
2032 #define ARIZONA_MICB3_FAST_WIDTH 1 /* MICB3_FAST */
2033 #define ARIZONA_MICB3_RATE 0x0008 /* MICB3_RATE */
2034 #define ARIZONA_MICB3_RATE_MASK 0x0008 /* MICB3_RATE */
2035 #define ARIZONA_MICB3_RATE_SHIFT 3 /* MICB3_RATE */
2036 #define ARIZONA_MICB3_RATE_WIDTH 1 /* MICB3_RATE */
2037 #define ARIZONA_MICB3_DISCH 0x0004 /* MICB3_DISCH */
2038 #define ARIZONA_MICB3_DISCH_MASK 0x0004 /* MICB3_DISCH */
2039 #define ARIZONA_MICB3_DISCH_SHIFT 2 /* MICB3_DISCH */
2040 #define ARIZONA_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */
2041 #define ARIZONA_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */
2042 #define ARIZONA_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */
2043 #define ARIZONA_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */
2044 #define ARIZONA_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */
2045 #define ARIZONA_MICB3_ENA 0x0001 /* MICB3_ENA */
2046 #define ARIZONA_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */
2047 #define ARIZONA_MICB3_ENA_SHIFT 0 /* MICB3_ENA */
2048 #define ARIZONA_MICB3_ENA_WIDTH 1 /* MICB3_ENA */
2051 * R659 (0x293) - Accessory Detect Mode 1
2053 #define ARIZONA_ACCDET_SRC 0x2000 /* ACCDET_SRC */
2054 #define ARIZONA_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */
2055 #define ARIZONA_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */
2056 #define ARIZONA_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */
2057 #define ARIZONA_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */
2058 #define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */
2059 #define ARIZONA_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */
2062 * R667 (0x29B) - Headphone Detect 1
2064 #define ARIZONA_HP_IMPEDANCE_RANGE_MASK 0x0600 /* HP_IMPEDANCE_RANGE - [10:9] */
2065 #define ARIZONA_HP_IMPEDANCE_RANGE_SHIFT 9 /* HP_IMPEDANCE_RANGE - [10:9] */
2066 #define ARIZONA_HP_IMPEDANCE_RANGE_WIDTH 2 /* HP_IMPEDANCE_RANGE - [10:9] */
2067 #define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */
2068 #define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */
2069 #define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */
2070 #define ARIZONA_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
2071 #define ARIZONA_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
2072 #define ARIZONA_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
2073 #define ARIZONA_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
2074 #define ARIZONA_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
2075 #define ARIZONA_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
2076 #define ARIZONA_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
2077 #define ARIZONA_HP_IDAC_STEER 0x0004 /* HP_IDAC_STEER */
2078 #define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */
2079 #define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */
2080 #define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */
2081 #define ARIZONA_HP_RATE 0x0002 /* HP_RATE */
2082 #define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */
2083 #define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */
2084 #define ARIZONA_HP_RATE_WIDTH 1 /* HP_RATE */
2085 #define ARIZONA_HP_POLL 0x0001 /* HP_POLL */
2086 #define ARIZONA_HP_POLL_MASK 0x0001 /* HP_POLL */
2087 #define ARIZONA_HP_POLL_SHIFT 0 /* HP_POLL */
2088 #define ARIZONA_HP_POLL_WIDTH 1 /* HP_POLL */
2091 * R668 (0x29C) - Headphone Detect 2
2093 #define ARIZONA_HP_DONE 0x0080 /* HP_DONE */
2094 #define ARIZONA_HP_DONE_MASK 0x0080 /* HP_DONE */
2095 #define ARIZONA_HP_DONE_SHIFT 7 /* HP_DONE */
2096 #define ARIZONA_HP_DONE_WIDTH 1 /* HP_DONE */
2097 #define ARIZONA_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
2098 #define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
2099 #define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
2101 #define ARIZONA_HP_DONE_B 0x8000 /* HP_DONE */
2102 #define ARIZONA_HP_DONE_B_MASK 0x8000 /* HP_DONE */
2103 #define ARIZONA_HP_DONE_B_SHIFT 15 /* HP_DONE */
2104 #define ARIZONA_HP_DONE_B_WIDTH 1 /* HP_DONE */
2105 #define ARIZONA_HP_LVL_B_MASK 0x7FFF /* HP_LVL - [14:0] */
2106 #define ARIZONA_HP_LVL_B_SHIFT 0 /* HP_LVL - [14:0] */
2107 #define ARIZONA_HP_LVL_B_WIDTH 15 /* HP_LVL - [14:0] */
2110 * R674 (0x2A2) - MICD clamp control
2112 #define ARIZONA_MICD_CLAMP_MODE_MASK 0x000F /* MICD_CLAMP_MODE - [3:0] */
2113 #define ARIZONA_MICD_CLAMP_MODE_SHIFT 0 /* MICD_CLAMP_MODE - [3:0] */
2114 #define ARIZONA_MICD_CLAMP_MODE_WIDTH 4 /* MICD_CLAMP_MODE - [3:0] */
2117 * R675 (0x2A3) - Mic Detect 1
2119 #define ARIZONA_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
2120 #define ARIZONA_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
2121 #define ARIZONA_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
2122 #define ARIZONA_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
2123 #define ARIZONA_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
2124 #define ARIZONA_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
2125 #define ARIZONA_MICD_BIAS_SRC_MASK 0x0030 /* MICD_BIAS_SRC - [5:4] */
2126 #define ARIZONA_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [5:4] */
2127 #define ARIZONA_MICD_BIAS_SRC_WIDTH 2 /* MICD_BIAS_SRC - [5:4] */
2128 #define ARIZONA_MICD_DBTIME 0x0002 /* MICD_DBTIME */
2129 #define ARIZONA_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
2130 #define ARIZONA_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
2131 #define ARIZONA_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
2132 #define ARIZONA_MICD_ENA 0x0001 /* MICD_ENA */
2133 #define ARIZONA_MICD_ENA_MASK 0x0001 /* MICD_ENA */
2134 #define ARIZONA_MICD_ENA_SHIFT 0 /* MICD_ENA */
2135 #define ARIZONA_MICD_ENA_WIDTH 1 /* MICD_ENA */
2138 * R676 (0x2A4) - Mic Detect 2
2140 #define ARIZONA_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
2141 #define ARIZONA_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
2142 #define ARIZONA_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
2145 * R677 (0x2A5) - Mic Detect 3
2147 #define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
2148 #define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
2149 #define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
2150 #define ARIZONA_MICD_VALID 0x0002 /* MICD_VALID */
2151 #define ARIZONA_MICD_VALID_MASK 0x0002 /* MICD_VALID */
2152 #define ARIZONA_MICD_VALID_SHIFT 1 /* MICD_VALID */
2153 #define ARIZONA_MICD_VALID_WIDTH 1 /* MICD_VALID */
2154 #define ARIZONA_MICD_STS 0x0001 /* MICD_STS */
2155 #define ARIZONA_MICD_STS_MASK 0x0001 /* MICD_STS */
2156 #define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */
2157 #define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */
2160 * R707 (0x2C3) - Mic noise mix control 1
2162 #define ARIZONA_MICMUTE_RATE_MASK 0x7800 /* MICMUTE_RATE - [14:11] */
2163 #define ARIZONA_MICMUTE_RATE_SHIFT 11 /* MICMUTE_RATE - [14:11] */
2164 #define ARIZONA_MICMUTE_RATE_WIDTH 4 /* MICMUTE_RATE - [14:11] */
2165 #define ARIZONA_MICMUTE_MIX_ENA 0x0040 /* MICMUTE_MIX_ENA */
2166 #define ARIZONA_MICMUTE_MIX_ENA_MASK 0x0040 /* MICMUTE_MIX_ENA */
2167 #define ARIZONA_MICMUTE_MIX_ENA_SHIFT 6 /* MICMUTE_MIX_ENA */
2168 #define ARIZONA_MICMUTE_MIX_ENA_WIDTH 1 /* MICMUTE_MIX_ENA */
2171 * R715 (0x2CB) - Isolation control
2173 #define ARIZONA_ISOLATE_DCVDD1 0x0001 /* ISOLATE_DCVDD1 */
2174 #define ARIZONA_ISOLATE_DCVDD1_MASK 0x0001 /* ISOLATE_DCVDD1 */
2175 #define ARIZONA_ISOLATE_DCVDD1_SHIFT 0 /* ISOLATE_DCVDD1 */
2176 #define ARIZONA_ISOLATE_DCVDD1_WIDTH 1 /* ISOLATE_DCVDD1 */
2179 * R723 (0x2D3) - Jack detect analogue
2181 #define ARIZONA_JD2_ENA 0x0002 /* JD2_ENA */
2182 #define ARIZONA_JD2_ENA_MASK 0x0002 /* JD2_ENA */
2183 #define ARIZONA_JD2_ENA_SHIFT 1 /* JD2_ENA */
2184 #define ARIZONA_JD2_ENA_WIDTH 1 /* JD2_ENA */
2185 #define ARIZONA_JD1_ENA 0x0001 /* JD1_ENA */
2186 #define ARIZONA_JD1_ENA_MASK 0x0001 /* JD1_ENA */
2187 #define ARIZONA_JD1_ENA_SHIFT 0 /* JD1_ENA */
2188 #define ARIZONA_JD1_ENA_WIDTH 1 /* JD1_ENA */
2191 * R768 (0x300) - Input Enables
2193 #define ARIZONA_IN4L_ENA 0x0080 /* IN4L_ENA */
2194 #define ARIZONA_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */
2195 #define ARIZONA_IN4L_ENA_SHIFT 7 /* IN4L_ENA */
2196 #define ARIZONA_IN4L_ENA_WIDTH 1 /* IN4L_ENA */
2197 #define ARIZONA_IN4R_ENA 0x0040 /* IN4R_ENA */
2198 #define ARIZONA_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */
2199 #define ARIZONA_IN4R_ENA_SHIFT 6 /* IN4R_ENA */
2200 #define ARIZONA_IN4R_ENA_WIDTH 1 /* IN4R_ENA */
2201 #define ARIZONA_IN3L_ENA 0x0020 /* IN3L_ENA */
2202 #define ARIZONA_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
2203 #define ARIZONA_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
2204 #define ARIZONA_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
2205 #define ARIZONA_IN3R_ENA 0x0010 /* IN3R_ENA */
2206 #define ARIZONA_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
2207 #define ARIZONA_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
2208 #define ARIZONA_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
2209 #define ARIZONA_IN2L_ENA 0x0008 /* IN2L_ENA */
2210 #define ARIZONA_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
2211 #define ARIZONA_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
2212 #define ARIZONA_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
2213 #define ARIZONA_IN2R_ENA 0x0004 /* IN2R_ENA */
2214 #define ARIZONA_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
2215 #define ARIZONA_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
2216 #define ARIZONA_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
2217 #define ARIZONA_IN1L_ENA 0x0002 /* IN1L_ENA */
2218 #define ARIZONA_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
2219 #define ARIZONA_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
2220 #define ARIZONA_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
2221 #define ARIZONA_IN1R_ENA 0x0001 /* IN1R_ENA */
2222 #define ARIZONA_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
2223 #define ARIZONA_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
2224 #define ARIZONA_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
2227 * R776 (0x308) - Input Rate
2229 #define ARIZONA_IN_RATE_MASK 0x7800 /* IN_RATE - [14:11] */
2230 #define ARIZONA_IN_RATE_SHIFT 11 /* IN_RATE - [14:11] */
2231 #define ARIZONA_IN_RATE_WIDTH 4 /* IN_RATE - [14:11] */
2234 * R777 (0x309) - Input Volume Ramp
2236 #define ARIZONA_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
2237 #define ARIZONA_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
2238 #define ARIZONA_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
2239 #define ARIZONA_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
2240 #define ARIZONA_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
2241 #define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
2244 * R784 (0x310) - IN1L Control
2246 #define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */
2247 #define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */
2248 #define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */
2249 #define ARIZONA_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
2250 #define ARIZONA_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
2251 #define ARIZONA_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
2252 #define ARIZONA_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
2253 #define ARIZONA_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
2254 #define ARIZONA_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
2255 #define ARIZONA_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
2256 #define ARIZONA_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
2257 #define ARIZONA_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
2260 * R785 (0x311) - ADC Digital Volume 1L
2262 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2263 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2264 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2265 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2266 #define ARIZONA_IN1L_MUTE 0x0100 /* IN1L_MUTE */
2267 #define ARIZONA_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
2268 #define ARIZONA_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
2269 #define ARIZONA_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
2270 #define ARIZONA_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */
2271 #define ARIZONA_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */
2272 #define ARIZONA_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */
2275 * R786 (0x312) - DMIC1L Control
2277 #define ARIZONA_IN1_DMICL_DLY_MASK 0x003F /* IN1_DMICL_DLY - [5:0] */
2278 #define ARIZONA_IN1_DMICL_DLY_SHIFT 0 /* IN1_DMICL_DLY - [5:0] */
2279 #define ARIZONA_IN1_DMICL_DLY_WIDTH 6 /* IN1_DMICL_DLY - [5:0] */
2282 * R788 (0x314) - IN1R Control
2284 #define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
2285 #define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
2286 #define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
2289 * R789 (0x315) - ADC Digital Volume 1R
2291 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2292 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2293 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2294 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2295 #define ARIZONA_IN1R_MUTE 0x0100 /* IN1R_MUTE */
2296 #define ARIZONA_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
2297 #define ARIZONA_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
2298 #define ARIZONA_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
2299 #define ARIZONA_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */
2300 #define ARIZONA_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */
2301 #define ARIZONA_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */
2304 * R790 (0x316) - DMIC1R Control
2306 #define ARIZONA_IN1_DMICR_DLY_MASK 0x003F /* IN1_DMICR_DLY - [5:0] */
2307 #define ARIZONA_IN1_DMICR_DLY_SHIFT 0 /* IN1_DMICR_DLY - [5:0] */
2308 #define ARIZONA_IN1_DMICR_DLY_WIDTH 6 /* IN1_DMICR_DLY - [5:0] */
2311 * R792 (0x318) - IN2L Control
2313 #define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */
2314 #define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */
2315 #define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */
2316 #define ARIZONA_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
2317 #define ARIZONA_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
2318 #define ARIZONA_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
2319 #define ARIZONA_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
2320 #define ARIZONA_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
2321 #define ARIZONA_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
2322 #define ARIZONA_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
2323 #define ARIZONA_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
2324 #define ARIZONA_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
2327 * R793 (0x319) - ADC Digital Volume 2L
2329 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2330 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2331 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2332 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2333 #define ARIZONA_IN2L_MUTE 0x0100 /* IN2L_MUTE */
2334 #define ARIZONA_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
2335 #define ARIZONA_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
2336 #define ARIZONA_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
2337 #define ARIZONA_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */
2338 #define ARIZONA_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */
2339 #define ARIZONA_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */
2342 * R794 (0x31A) - DMIC2L Control
2344 #define ARIZONA_IN2_DMICL_DLY_MASK 0x003F /* IN2_DMICL_DLY - [5:0] */
2345 #define ARIZONA_IN2_DMICL_DLY_SHIFT 0 /* IN2_DMICL_DLY - [5:0] */
2346 #define ARIZONA_IN2_DMICL_DLY_WIDTH 6 /* IN2_DMICL_DLY - [5:0] */
2349 * R796 (0x31C) - IN2R Control
2351 #define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
2352 #define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
2353 #define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
2356 * R797 (0x31D) - ADC Digital Volume 2R
2358 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2359 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2360 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2361 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2362 #define ARIZONA_IN2R_MUTE 0x0100 /* IN2R_MUTE */
2363 #define ARIZONA_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
2364 #define ARIZONA_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
2365 #define ARIZONA_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
2366 #define ARIZONA_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */
2367 #define ARIZONA_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */
2368 #define ARIZONA_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */
2371 * R798 (0x31E) - DMIC2R Control
2373 #define ARIZONA_IN2_DMICR_DLY_MASK 0x003F /* IN2_DMICR_DLY - [5:0] */
2374 #define ARIZONA_IN2_DMICR_DLY_SHIFT 0 /* IN2_DMICR_DLY - [5:0] */
2375 #define ARIZONA_IN2_DMICR_DLY_WIDTH 6 /* IN2_DMICR_DLY - [5:0] */
2378 * R800 (0x320) - IN3L Control
2380 #define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */
2381 #define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */
2382 #define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */
2383 #define ARIZONA_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
2384 #define ARIZONA_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
2385 #define ARIZONA_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
2386 #define ARIZONA_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
2387 #define ARIZONA_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
2388 #define ARIZONA_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
2389 #define ARIZONA_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
2390 #define ARIZONA_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
2391 #define ARIZONA_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
2394 * R801 (0x321) - ADC Digital Volume 3L
2396 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2397 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2398 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2399 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2400 #define ARIZONA_IN3L_MUTE 0x0100 /* IN3L_MUTE */
2401 #define ARIZONA_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
2402 #define ARIZONA_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
2403 #define ARIZONA_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
2404 #define ARIZONA_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */
2405 #define ARIZONA_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */
2406 #define ARIZONA_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */
2409 * R802 (0x322) - DMIC3L Control
2411 #define ARIZONA_IN3_DMICL_DLY_MASK 0x003F /* IN3_DMICL_DLY - [5:0] */
2412 #define ARIZONA_IN3_DMICL_DLY_SHIFT 0 /* IN3_DMICL_DLY - [5:0] */
2413 #define ARIZONA_IN3_DMICL_DLY_WIDTH 6 /* IN3_DMICL_DLY - [5:0] */
2416 * R804 (0x324) - IN3R Control
2418 #define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
2419 #define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
2420 #define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
2423 * R805 (0x325) - ADC Digital Volume 3R
2425 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2426 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2427 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2428 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2429 #define ARIZONA_IN3R_MUTE 0x0100 /* IN3R_MUTE */
2430 #define ARIZONA_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
2431 #define ARIZONA_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
2432 #define ARIZONA_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
2433 #define ARIZONA_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */
2434 #define ARIZONA_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */
2435 #define ARIZONA_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */
2438 * R806 (0x326) - DMIC3R Control
2440 #define ARIZONA_IN3_DMICR_DLY_MASK 0x003F /* IN3_DMICR_DLY - [5:0] */
2441 #define ARIZONA_IN3_DMICR_DLY_SHIFT 0 /* IN3_DMICR_DLY - [5:0] */
2442 #define ARIZONA_IN3_DMICR_DLY_WIDTH 6 /* IN3_DMICR_DLY - [5:0] */
2445 * R808 (0x328) - IN4 Control
2447 #define ARIZONA_IN4_OSR_MASK 0x6000 /* IN4_OSR - [14:13] */
2448 #define ARIZONA_IN4_OSR_SHIFT 13 /* IN4_OSR - [14:13] */
2449 #define ARIZONA_IN4_OSR_WIDTH 2 /* IN4_OSR - [14:13] */
2450 #define ARIZONA_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */
2451 #define ARIZONA_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */
2452 #define ARIZONA_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */
2455 * R809 (0x329) - ADC Digital Volume 4L
2457 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2458 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2459 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2460 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2461 #define ARIZONA_IN4L_MUTE 0x0100 /* IN4L_MUTE */
2462 #define ARIZONA_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */
2463 #define ARIZONA_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */
2464 #define ARIZONA_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */
2465 #define ARIZONA_IN4L_DIG_VOL_MASK 0x00FF /* IN4L_DIG_VOL - [7:0] */
2466 #define ARIZONA_IN4L_DIG_VOL_SHIFT 0 /* IN4L_DIG_VOL - [7:0] */
2467 #define ARIZONA_IN4L_DIG_VOL_WIDTH 8 /* IN4L_DIG_VOL - [7:0] */
2470 * R810 (0x32A) - DMIC4L Control
2472 #define ARIZONA_IN4L_DMIC_DLY_MASK 0x003F /* IN4L_DMIC_DLY - [5:0] */
2473 #define ARIZONA_IN4L_DMIC_DLY_SHIFT 0 /* IN4L_DMIC_DLY - [5:0] */
2474 #define ARIZONA_IN4L_DMIC_DLY_WIDTH 6 /* IN4L_DMIC_DLY - [5:0] */
2477 * R813 (0x32D) - ADC Digital Volume 4R
2479 #define ARIZONA_IN_VU 0x0200 /* IN_VU */
2480 #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
2481 #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
2482 #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
2483 #define ARIZONA_IN4R_MUTE 0x0100 /* IN4R_MUTE */
2484 #define ARIZONA_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */
2485 #define ARIZONA_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */
2486 #define ARIZONA_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */
2487 #define ARIZONA_IN4R_DIG_VOL_MASK 0x00FF /* IN4R_DIG_VOL - [7:0] */
2488 #define ARIZONA_IN4R_DIG_VOL_SHIFT 0 /* IN4R_DIG_VOL - [7:0] */
2489 #define ARIZONA_IN4R_DIG_VOL_WIDTH 8 /* IN4R_DIG_VOL - [7:0] */
2492 * R814 (0x32E) - DMIC4R Control
2494 #define ARIZONA_IN4R_DMIC_DLY_MASK 0x003F /* IN4R_DMIC_DLY - [5:0] */
2495 #define ARIZONA_IN4R_DMIC_DLY_SHIFT 0 /* IN4R_DMIC_DLY - [5:0] */
2496 #define ARIZONA_IN4R_DMIC_DLY_WIDTH 6 /* IN4R_DMIC_DLY - [5:0] */
2499 * R1024 (0x400) - Output Enables 1
2501 #define ARIZONA_OUT6L_ENA 0x0800 /* OUT6L_ENA */
2502 #define ARIZONA_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */
2503 #define ARIZONA_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */
2504 #define ARIZONA_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */
2505 #define ARIZONA_OUT6R_ENA 0x0400 /* OUT6R_ENA */
2506 #define ARIZONA_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */
2507 #define ARIZONA_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */
2508 #define ARIZONA_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */
2509 #define ARIZONA_OUT5L_ENA 0x0200 /* OUT5L_ENA */
2510 #define ARIZONA_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */
2511 #define ARIZONA_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */
2512 #define ARIZONA_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */
2513 #define ARIZONA_OUT5R_ENA 0x0100 /* OUT5R_ENA */
2514 #define ARIZONA_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */
2515 #define ARIZONA_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */
2516 #define ARIZONA_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */
2517 #define ARIZONA_OUT4L_ENA 0x0080 /* OUT4L_ENA */
2518 #define ARIZONA_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */
2519 #define ARIZONA_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */
2520 #define ARIZONA_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */
2521 #define ARIZONA_OUT4R_ENA 0x0040 /* OUT4R_ENA */
2522 #define ARIZONA_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */
2523 #define ARIZONA_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */
2524 #define ARIZONA_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */
2525 #define ARIZONA_OUT3L_ENA 0x0020 /* OUT3L_ENA */
2526 #define ARIZONA_OUT3L_ENA_MASK 0x0020 /* OUT3L_ENA */
2527 #define ARIZONA_OUT3L_ENA_SHIFT 5 /* OUT3L_ENA */
2528 #define ARIZONA_OUT3L_ENA_WIDTH 1 /* OUT3L_ENA */
2529 #define ARIZONA_OUT3R_ENA 0x0010 /* OUT3R_ENA */
2530 #define ARIZONA_OUT3R_ENA_MASK 0x0010 /* OUT3R_ENA */
2531 #define ARIZONA_OUT3R_ENA_SHIFT 4 /* OUT3R_ENA */
2532 #define ARIZONA_OUT3R_ENA_WIDTH 1 /* OUT3R_ENA */
2533 #define ARIZONA_OUT2L_ENA 0x0008 /* OUT2L_ENA */
2534 #define ARIZONA_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */
2535 #define ARIZONA_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */
2536 #define ARIZONA_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */
2537 #define ARIZONA_OUT2R_ENA 0x0004 /* OUT2R_ENA */
2538 #define ARIZONA_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */
2539 #define ARIZONA_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */
2540 #define ARIZONA_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */
2541 #define ARIZONA_OUT1L_ENA 0x0002 /* OUT1L_ENA */
2542 #define ARIZONA_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */
2543 #define ARIZONA_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */
2544 #define ARIZONA_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */
2545 #define ARIZONA_OUT1R_ENA 0x0001 /* OUT1R_ENA */
2546 #define ARIZONA_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */
2547 #define ARIZONA_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */
2548 #define ARIZONA_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */
2551 * R1025 (0x401) - Output Status 1
2553 #define ARIZONA_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */
2554 #define ARIZONA_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */
2555 #define ARIZONA_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */
2556 #define ARIZONA_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */
2557 #define ARIZONA_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */
2558 #define ARIZONA_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */
2559 #define ARIZONA_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */
2560 #define ARIZONA_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */
2561 #define ARIZONA_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */
2562 #define ARIZONA_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */
2563 #define ARIZONA_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */
2564 #define ARIZONA_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */
2565 #define ARIZONA_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */
2566 #define ARIZONA_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */
2567 #define ARIZONA_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */
2568 #define ARIZONA_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */
2569 #define ARIZONA_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */
2570 #define ARIZONA_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */
2571 #define ARIZONA_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */
2572 #define ARIZONA_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */
2573 #define ARIZONA_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */
2574 #define ARIZONA_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */
2575 #define ARIZONA_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */
2576 #define ARIZONA_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */
2579 * R1032 (0x408) - Output Rate 1
2581 #define ARIZONA_OUT_RATE_MASK 0x7800 /* OUT_RATE - [14:11] */
2582 #define ARIZONA_OUT_RATE_SHIFT 11 /* OUT_RATE - [14:11] */
2583 #define ARIZONA_OUT_RATE_WIDTH 4 /* OUT_RATE - [14:11] */
2586 * R1033 (0x409) - Output Volume Ramp
2588 #define ARIZONA_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
2589 #define ARIZONA_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
2590 #define ARIZONA_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
2591 #define ARIZONA_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
2592 #define ARIZONA_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
2593 #define ARIZONA_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
2596 * R1040 (0x410) - Output Path Config 1L
2598 #define ARIZONA_OUT1_LP_MODE 0x8000 /* OUT1_LP_MODE */
2599 #define ARIZONA_OUT1_LP_MODE_MASK 0x8000 /* OUT1_LP_MODE */
2600 #define ARIZONA_OUT1_LP_MODE_SHIFT 15 /* OUT1_LP_MODE */
2601 #define ARIZONA_OUT1_LP_MODE_WIDTH 1 /* OUT1_LP_MODE */
2602 #define ARIZONA_OUT1_OSR 0x2000 /* OUT1_OSR */
2603 #define ARIZONA_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
2604 #define ARIZONA_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
2605 #define ARIZONA_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
2606 #define ARIZONA_OUT1_MONO 0x1000 /* OUT1_MONO */
2607 #define ARIZONA_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */
2608 #define ARIZONA_OUT1_MONO_SHIFT 12 /* OUT1_MONO */
2609 #define ARIZONA_OUT1_MONO_WIDTH 1 /* OUT1_MONO */
2610 #define ARIZONA_OUT1L_ANC_SRC_MASK 0x0C00 /* OUT1L_ANC_SRC - [11:10] */
2611 #define ARIZONA_OUT1L_ANC_SRC_SHIFT 10 /* OUT1L_ANC_SRC - [11:10] */
2612 #define ARIZONA_OUT1L_ANC_SRC_WIDTH 2 /* OUT1L_ANC_SRC - [11:10] */
2613 #define ARIZONA_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
2614 #define ARIZONA_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
2615 #define ARIZONA_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
2618 * R1041 (0x411) - DAC Digital Volume 1L
2620 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2621 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2622 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2623 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2624 #define ARIZONA_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
2625 #define ARIZONA_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
2626 #define ARIZONA_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
2627 #define ARIZONA_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
2628 #define ARIZONA_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
2629 #define ARIZONA_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
2630 #define ARIZONA_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
2633 * R1042 (0x412) - DAC Volume Limit 1L
2635 #define ARIZONA_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */
2636 #define ARIZONA_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */
2637 #define ARIZONA_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */
2640 * R1043 (0x413) - Noise Gate Select 1L
2642 #define ARIZONA_OUT1L_NGATE_SRC_MASK 0x0FFF /* OUT1L_NGATE_SRC - [11:0] */
2643 #define ARIZONA_OUT1L_NGATE_SRC_SHIFT 0 /* OUT1L_NGATE_SRC - [11:0] */
2644 #define ARIZONA_OUT1L_NGATE_SRC_WIDTH 12 /* OUT1L_NGATE_SRC - [11:0] */
2647 * R1044 (0x414) - Output Path Config 1R
2649 #define ARIZONA_OUT1R_ANC_SRC_MASK 0x0C00 /* OUT1R_ANC_SRC - [11:10] */
2650 #define ARIZONA_OUT1R_ANC_SRC_SHIFT 10 /* OUT1R_ANC_SRC - [11:10] */
2651 #define ARIZONA_OUT1R_ANC_SRC_WIDTH 2 /* OUT1R_ANC_SRC - [11:10] */
2652 #define ARIZONA_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
2653 #define ARIZONA_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
2654 #define ARIZONA_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
2657 * R1045 (0x415) - DAC Digital Volume 1R
2659 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2660 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2661 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2662 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2663 #define ARIZONA_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
2664 #define ARIZONA_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
2665 #define ARIZONA_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
2666 #define ARIZONA_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
2667 #define ARIZONA_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
2668 #define ARIZONA_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
2669 #define ARIZONA_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
2672 * R1046 (0x416) - DAC Volume Limit 1R
2674 #define ARIZONA_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */
2675 #define ARIZONA_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */
2676 #define ARIZONA_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */
2679 * R1047 (0x417) - Noise Gate Select 1R
2681 #define ARIZONA_OUT1R_NGATE_SRC_MASK 0x0FFF /* OUT1R_NGATE_SRC - [11:0] */
2682 #define ARIZONA_OUT1R_NGATE_SRC_SHIFT 0 /* OUT1R_NGATE_SRC - [11:0] */
2683 #define ARIZONA_OUT1R_NGATE_SRC_WIDTH 12 /* OUT1R_NGATE_SRC - [11:0] */
2686 * R1048 (0x418) - Output Path Config 2L
2688 #define ARIZONA_OUT2_LP_MODE 0x8000 /* OUT2_LP_MODE */
2689 #define ARIZONA_OUT2_LP_MODE_MASK 0x8000 /* OUT2_LP_MODE */
2690 #define ARIZONA_OUT2_LP_MODE_SHIFT 15 /* OUT2_LP_MODE */
2691 #define ARIZONA_OUT2_LP_MODE_WIDTH 1 /* OUT2_LP_MODE */
2692 #define ARIZONA_OUT2_OSR 0x2000 /* OUT2_OSR */
2693 #define ARIZONA_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
2694 #define ARIZONA_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
2695 #define ARIZONA_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
2696 #define ARIZONA_OUT2_MONO 0x1000 /* OUT2_MONO */
2697 #define ARIZONA_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */
2698 #define ARIZONA_OUT2_MONO_SHIFT 12 /* OUT2_MONO */
2699 #define ARIZONA_OUT2_MONO_WIDTH 1 /* OUT2_MONO */
2700 #define ARIZONA_OUT2L_ANC_SRC_MASK 0x0C00 /* OUT2L_ANC_SRC - [11:10] */
2701 #define ARIZONA_OUT2L_ANC_SRC_SHIFT 10 /* OUT2L_ANC_SRC - [11:10] */
2702 #define ARIZONA_OUT2L_ANC_SRC_WIDTH 2 /* OUT2L_ANC_SRC - [11:10] */
2703 #define ARIZONA_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */
2704 #define ARIZONA_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */
2705 #define ARIZONA_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */
2708 * R1049 (0x419) - DAC Digital Volume 2L
2710 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2711 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2712 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2713 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2714 #define ARIZONA_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
2715 #define ARIZONA_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
2716 #define ARIZONA_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
2717 #define ARIZONA_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
2718 #define ARIZONA_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
2719 #define ARIZONA_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
2720 #define ARIZONA_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
2723 * R1050 (0x41A) - DAC Volume Limit 2L
2725 #define ARIZONA_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */
2726 #define ARIZONA_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */
2727 #define ARIZONA_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */
2730 * R1051 (0x41B) - Noise Gate Select 2L
2732 #define ARIZONA_OUT2L_NGATE_SRC_MASK 0x0FFF /* OUT2L_NGATE_SRC - [11:0] */
2733 #define ARIZONA_OUT2L_NGATE_SRC_SHIFT 0 /* OUT2L_NGATE_SRC - [11:0] */
2734 #define ARIZONA_OUT2L_NGATE_SRC_WIDTH 12 /* OUT2L_NGATE_SRC - [11:0] */
2737 * R1052 (0x41C) - Output Path Config 2R
2739 #define ARIZONA_OUT2R_ANC_SRC_MASK 0x0C00 /* OUT2R_ANC_SRC - [11:10] */
2740 #define ARIZONA_OUT2R_ANC_SRC_SHIFT 10 /* OUT2R_ANC_SRC - [11:10] */
2741 #define ARIZONA_OUT2R_ANC_SRC_WIDTH 2 /* OUT2R_ANC_SRC - [11:10] */
2742 #define ARIZONA_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */
2743 #define ARIZONA_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */
2744 #define ARIZONA_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */
2747 * R1053 (0x41D) - DAC Digital Volume 2R
2749 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2750 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2751 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2752 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2753 #define ARIZONA_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
2754 #define ARIZONA_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
2755 #define ARIZONA_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
2756 #define ARIZONA_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
2757 #define ARIZONA_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
2758 #define ARIZONA_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
2759 #define ARIZONA_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
2762 * R1054 (0x41E) - DAC Volume Limit 2R
2764 #define ARIZONA_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */
2765 #define ARIZONA_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */
2766 #define ARIZONA_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */
2769 * R1055 (0x41F) - Noise Gate Select 2R
2771 #define ARIZONA_OUT2R_NGATE_SRC_MASK 0x0FFF /* OUT2R_NGATE_SRC - [11:0] */
2772 #define ARIZONA_OUT2R_NGATE_SRC_SHIFT 0 /* OUT2R_NGATE_SRC - [11:0] */
2773 #define ARIZONA_OUT2R_NGATE_SRC_WIDTH 12 /* OUT2R_NGATE_SRC - [11:0] */
2776 * R1056 (0x420) - Output Path Config 3L
2778 #define ARIZONA_OUT3_LP_MODE 0x8000 /* OUT3_LP_MODE */
2779 #define ARIZONA_OUT3_LP_MODE_MASK 0x8000 /* OUT3_LP_MODE */
2780 #define ARIZONA_OUT3_LP_MODE_SHIFT 15 /* OUT3_LP_MODE */
2781 #define ARIZONA_OUT3_LP_MODE_WIDTH 1 /* OUT3_LP_MODE */
2782 #define ARIZONA_OUT3_OSR 0x2000 /* OUT3_OSR */
2783 #define ARIZONA_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */
2784 #define ARIZONA_OUT3_OSR_SHIFT 13 /* OUT3_OSR */
2785 #define ARIZONA_OUT3_OSR_WIDTH 1 /* OUT3_OSR */
2786 #define ARIZONA_OUT3_MONO 0x1000 /* OUT3_MONO */
2787 #define ARIZONA_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */
2788 #define ARIZONA_OUT3_MONO_SHIFT 12 /* OUT3_MONO */
2789 #define ARIZONA_OUT3_MONO_WIDTH 1 /* OUT3_MONO */
2790 #define ARIZONA_OUT3L_ANC_SRC_MASK 0x0C00 /* OUT3L_ANC_SRC - [11:10] */
2791 #define ARIZONA_OUT3L_ANC_SRC_SHIFT 10 /* OUT3L_ANC_SRC - [11:10] */
2792 #define ARIZONA_OUT3L_ANC_SRC_WIDTH 2 /* OUT3L_ANC_SRC - [11:10] */
2793 #define ARIZONA_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */
2794 #define ARIZONA_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */
2795 #define ARIZONA_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */
2798 * R1057 (0x421) - DAC Digital Volume 3L
2800 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2801 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2802 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2803 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2804 #define ARIZONA_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */
2805 #define ARIZONA_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */
2806 #define ARIZONA_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */
2807 #define ARIZONA_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */
2808 #define ARIZONA_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */
2809 #define ARIZONA_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */
2810 #define ARIZONA_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */
2813 * R1058 (0x422) - DAC Volume Limit 3L
2815 #define ARIZONA_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */
2816 #define ARIZONA_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */
2817 #define ARIZONA_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */
2820 * R1059 (0x423) - Noise Gate Select 3L
2822 #define ARIZONA_OUT3_NGATE_SRC_MASK 0x0FFF /* OUT3_NGATE_SRC - [11:0] */
2823 #define ARIZONA_OUT3_NGATE_SRC_SHIFT 0 /* OUT3_NGATE_SRC - [11:0] */
2824 #define ARIZONA_OUT3_NGATE_SRC_WIDTH 12 /* OUT3_NGATE_SRC - [11:0] */
2827 * R1060 (0x424) - Output Path Config 3R
2829 #define ARIZONA_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */
2830 #define ARIZONA_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */
2831 #define ARIZONA_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */
2834 * R1061 (0x425) - DAC Digital Volume 3R
2836 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2837 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2838 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2839 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2840 #define ARIZONA_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */
2841 #define ARIZONA_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */
2842 #define ARIZONA_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */
2843 #define ARIZONA_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */
2844 #define ARIZONA_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */
2845 #define ARIZONA_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */
2846 #define ARIZONA_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */
2849 * R1062 (0x426) - DAC Volume Limit 3R
2851 #define ARIZONA_OUT3R_ANC_SRC_MASK 0x0C00 /* OUT3R_ANC_SRC - [11:10] */
2852 #define ARIZONA_OUT3R_ANC_SRC_SHIFT 10 /* OUT3R_ANC_SRC - [11:10] */
2853 #define ARIZONA_OUT3R_ANC_SRC_WIDTH 2 /* OUT3R_ANC_SRC - [11:10] */
2854 #define ARIZONA_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */
2855 #define ARIZONA_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */
2856 #define ARIZONA_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */
2859 * R1064 (0x428) - Output Path Config 4L
2861 #define ARIZONA_OUT4_OSR 0x2000 /* OUT4_OSR */
2862 #define ARIZONA_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */
2863 #define ARIZONA_OUT4_OSR_SHIFT 13 /* OUT4_OSR */
2864 #define ARIZONA_OUT4_OSR_WIDTH 1 /* OUT4_OSR */
2865 #define ARIZONA_OUT4L_ANC_SRC_MASK 0x0C00 /* OUT4L_ANC_SRC - [11:10] */
2866 #define ARIZONA_OUT4L_ANC_SRC_SHIFT 10 /* OUT4L_ANC_SRC - [11:10] */
2867 #define ARIZONA_OUT4L_ANC_SRC_WIDTH 2 /* OUT4L_ANC_SRC - [11:10] */
2870 * R1065 (0x429) - DAC Digital Volume 4L
2872 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2873 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2874 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2875 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2876 #define ARIZONA_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */
2877 #define ARIZONA_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */
2878 #define ARIZONA_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */
2879 #define ARIZONA_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */
2880 #define ARIZONA_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */
2881 #define ARIZONA_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */
2882 #define ARIZONA_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */
2885 * R1066 (0x42A) - Out Volume 4L
2887 #define ARIZONA_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */
2888 #define ARIZONA_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */
2889 #define ARIZONA_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */
2892 * R1067 (0x42B) - Noise Gate Select 4L
2894 #define ARIZONA_OUT4L_NGATE_SRC_MASK 0x0FFF /* OUT4L_NGATE_SRC - [11:0] */
2895 #define ARIZONA_OUT4L_NGATE_SRC_SHIFT 0 /* OUT4L_NGATE_SRC - [11:0] */
2896 #define ARIZONA_OUT4L_NGATE_SRC_WIDTH 12 /* OUT4L_NGATE_SRC - [11:0] */
2899 * R1068 (0x42C) - Output Path Config 4R
2901 #define ARIZONA_OUT4R_ANC_SRC_MASK 0x0C00 /* OUT4R_ANC_SRC - [11:10] */
2902 #define ARIZONA_OUT4R_ANC_SRC_SHIFT 10 /* OUT4R_ANC_SRC - [11:10] */
2903 #define ARIZONA_OUT4R_ANC_SRC_WIDTH 2 /* OUT4R_ANC_SRC - [11:10] */
2906 * R1069 (0x42D) - DAC Digital Volume 4R
2908 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2909 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2910 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2911 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2912 #define ARIZONA_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */
2913 #define ARIZONA_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */
2914 #define ARIZONA_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */
2915 #define ARIZONA_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */
2916 #define ARIZONA_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */
2917 #define ARIZONA_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */
2918 #define ARIZONA_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */
2921 * R1070 (0x42E) - Out Volume 4R
2923 #define ARIZONA_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */
2924 #define ARIZONA_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */
2925 #define ARIZONA_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */
2928 * R1071 (0x42F) - Noise Gate Select 4R
2930 #define ARIZONA_OUT4R_NGATE_SRC_MASK 0x0FFF /* OUT4R_NGATE_SRC - [11:0] */
2931 #define ARIZONA_OUT4R_NGATE_SRC_SHIFT 0 /* OUT4R_NGATE_SRC - [11:0] */
2932 #define ARIZONA_OUT4R_NGATE_SRC_WIDTH 12 /* OUT4R_NGATE_SRC - [11:0] */
2935 * R1072 (0x430) - Output Path Config 5L
2937 #define ARIZONA_OUT5_OSR 0x2000 /* OUT5_OSR */
2938 #define ARIZONA_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */
2939 #define ARIZONA_OUT5_OSR_SHIFT 13 /* OUT5_OSR */
2940 #define ARIZONA_OUT5_OSR_WIDTH 1 /* OUT5_OSR */
2941 #define ARIZONA_OUT5L_ANC_SRC_MASK 0x0C00 /* OUT5L_ANC_SRC - [11:10] */
2942 #define ARIZONA_OUT5L_ANC_SRC_SHIFT 10 /* OUT5L_ANC_SRC - [11:10] */
2943 #define ARIZONA_OUT5L_ANC_SRC_WIDTH 2 /* OUT5L_ANC_SRC - [11:10] */
2946 * R1073 (0x431) - DAC Digital Volume 5L
2948 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2949 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2950 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2951 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2952 #define ARIZONA_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */
2953 #define ARIZONA_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */
2954 #define ARIZONA_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */
2955 #define ARIZONA_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */
2956 #define ARIZONA_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */
2957 #define ARIZONA_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */
2958 #define ARIZONA_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */
2961 * R1074 (0x432) - DAC Volume Limit 5L
2963 #define ARIZONA_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */
2964 #define ARIZONA_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */
2965 #define ARIZONA_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */
2968 * R1075 (0x433) - Noise Gate Select 5L
2970 #define ARIZONA_OUT5L_NGATE_SRC_MASK 0x0FFF /* OUT5L_NGATE_SRC - [11:0] */
2971 #define ARIZONA_OUT5L_NGATE_SRC_SHIFT 0 /* OUT5L_NGATE_SRC - [11:0] */
2972 #define ARIZONA_OUT5L_NGATE_SRC_WIDTH 12 /* OUT5L_NGATE_SRC - [11:0] */
2975 * R1076 (0x434) - Output Path Config 5R
2977 #define ARIZONA_OUT5R_ANC_SRC_MASK 0x0C00 /* OUT5R_ANC_SRC - [11:10] */
2978 #define ARIZONA_OUT5R_ANC_SRC_SHIFT 10 /* OUT5R_ANC_SRC - [11:10] */
2979 #define ARIZONA_OUT5R_ANC_SRC_WIDTH 2 /* OUT5R_ANC_SRC - [11:10] */
2982 * R1077 (0x435) - DAC Digital Volume 5R
2984 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
2985 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
2986 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
2987 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
2988 #define ARIZONA_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */
2989 #define ARIZONA_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */
2990 #define ARIZONA_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */
2991 #define ARIZONA_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */
2992 #define ARIZONA_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */
2993 #define ARIZONA_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */
2994 #define ARIZONA_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */
2997 * R1078 (0x436) - DAC Volume Limit 5R
2999 #define ARIZONA_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */
3000 #define ARIZONA_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */
3001 #define ARIZONA_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */
3004 * R1079 (0x437) - Noise Gate Select 5R
3006 #define ARIZONA_OUT5R_NGATE_SRC_MASK 0x0FFF /* OUT5R_NGATE_SRC - [11:0] */
3007 #define ARIZONA_OUT5R_NGATE_SRC_SHIFT 0 /* OUT5R_NGATE_SRC - [11:0] */
3008 #define ARIZONA_OUT5R_NGATE_SRC_WIDTH 12 /* OUT5R_NGATE_SRC - [11:0] */
3011 * R1080 (0x438) - Output Path Config 6L
3013 #define ARIZONA_OUT6_OSR 0x2000 /* OUT6_OSR */
3014 #define ARIZONA_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */
3015 #define ARIZONA_OUT6_OSR_SHIFT 13 /* OUT6_OSR */
3016 #define ARIZONA_OUT6_OSR_WIDTH 1 /* OUT6_OSR */
3017 #define ARIZONA_OUT6L_ANC_SRC_MASK 0x0C00 /* OUT6L_ANC_SRC - [11:10] */
3018 #define ARIZONA_OUT6L_ANC_SRC_SHIFT 10 /* OUT6L_ANC_SRC - [11:10] */
3019 #define ARIZONA_OUT6L_ANC_SRC_WIDTH 2 /* OUT6L_ANC_SRC - [11:10] */
3022 * R1081 (0x439) - DAC Digital Volume 6L
3024 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
3025 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
3026 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
3027 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
3028 #define ARIZONA_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */
3029 #define ARIZONA_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */
3030 #define ARIZONA_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */
3031 #define ARIZONA_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */
3032 #define ARIZONA_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */
3033 #define ARIZONA_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */
3034 #define ARIZONA_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */
3037 * R1082 (0x43A) - DAC Volume Limit 6L
3039 #define ARIZONA_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */
3040 #define ARIZONA_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */
3041 #define ARIZONA_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */
3044 * R1083 (0x43B) - Noise Gate Select 6L
3046 #define ARIZONA_OUT6L_NGATE_SRC_MASK 0x0FFF /* OUT6L_NGATE_SRC - [11:0] */
3047 #define ARIZONA_OUT6L_NGATE_SRC_SHIFT 0 /* OUT6L_NGATE_SRC - [11:0] */
3048 #define ARIZONA_OUT6L_NGATE_SRC_WIDTH 12 /* OUT6L_NGATE_SRC - [11:0] */
3051 * R1084 (0x43C) - Output Path Config 6R
3053 #define ARIZONA_OUT6R_ANC_SRC_MASK 0x0C00 /* OUT6R_ANC_SRC - [11:10] */
3054 #define ARIZONA_OUT6R_ANC_SRC_SHIFT 10 /* OUT6R_ANC_SRC - [11:10] */
3055 #define ARIZONA_OUT6R_ANC_SRC_WIDTH 2 /* OUT6R_ANC_SRC - [11:10] */
3058 * R1085 (0x43D) - DAC Digital Volume 6R
3060 #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
3061 #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
3062 #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
3063 #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
3064 #define ARIZONA_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */
3065 #define ARIZONA_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */
3066 #define ARIZONA_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */
3067 #define ARIZONA_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */
3068 #define ARIZONA_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */
3069 #define ARIZONA_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */
3070 #define ARIZONA_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */
3073 * R1086 (0x43E) - DAC Volume Limit 6R
3075 #define ARIZONA_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */
3076 #define ARIZONA_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */
3077 #define ARIZONA_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */
3080 * R1087 (0x43F) - Noise Gate Select 6R
3082 #define ARIZONA_OUT6R_NGATE_SRC_MASK 0x0FFF /* OUT6R_NGATE_SRC - [11:0] */
3083 #define ARIZONA_OUT6R_NGATE_SRC_SHIFT 0 /* OUT6R_NGATE_SRC - [11:0] */
3084 #define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */
3087 * R1104 (0x450) - DAC AEC Control 1
3089 #define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */
3090 #define ARIZONA_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */
3091 #define ARIZONA_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */
3092 #define ARIZONA_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */
3093 #define ARIZONA_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */
3094 #define ARIZONA_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */
3095 #define ARIZONA_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */
3096 #define ARIZONA_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */
3097 #define ARIZONA_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */
3098 #define ARIZONA_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */
3099 #define ARIZONA_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
3102 * R1112 (0x458) - Noise Gate Control
3104 #define ARIZONA_NGATE_HOLD_MASK 0x0030 /* NGATE_HOLD - [5:4] */
3105 #define ARIZONA_NGATE_HOLD_SHIFT 4 /* NGATE_HOLD - [5:4] */
3106 #define ARIZONA_NGATE_HOLD_WIDTH 2 /* NGATE_HOLD - [5:4] */
3107 #define ARIZONA_NGATE_THR_MASK 0x000E /* NGATE_THR - [3:1] */
3108 #define ARIZONA_NGATE_THR_SHIFT 1 /* NGATE_THR - [3:1] */
3109 #define ARIZONA_NGATE_THR_WIDTH 3 /* NGATE_THR - [3:1] */
3110 #define ARIZONA_NGATE_ENA 0x0001 /* NGATE_ENA */
3111 #define ARIZONA_NGATE_ENA_MASK 0x0001 /* NGATE_ENA */
3112 #define ARIZONA_NGATE_ENA_SHIFT 0 /* NGATE_ENA */
3113 #define ARIZONA_NGATE_ENA_WIDTH 1 /* NGATE_ENA */
3116 * R1168 (0x490) - PDM SPK1 CTRL 1
3118 #define ARIZONA_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
3119 #define ARIZONA_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
3120 #define ARIZONA_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
3121 #define ARIZONA_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
3122 #define ARIZONA_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
3123 #define ARIZONA_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
3124 #define ARIZONA_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
3125 #define ARIZONA_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
3126 #define ARIZONA_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
3127 #define ARIZONA_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
3128 #define ARIZONA_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
3129 #define ARIZONA_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
3130 #define ARIZONA_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
3131 #define ARIZONA_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
3132 #define ARIZONA_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
3135 * R1169 (0x491) - PDM SPK1 CTRL 2
3137 #define ARIZONA_SPK1_FMT 0x0001 /* SPK1_FMT */
3138 #define ARIZONA_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
3139 #define ARIZONA_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
3140 #define ARIZONA_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
3143 * R1170 (0x492) - PDM SPK2 CTRL 1
3145 #define ARIZONA_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */
3146 #define ARIZONA_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */
3147 #define ARIZONA_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */
3148 #define ARIZONA_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
3149 #define ARIZONA_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */
3150 #define ARIZONA_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */
3151 #define ARIZONA_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */
3152 #define ARIZONA_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
3153 #define ARIZONA_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */
3154 #define ARIZONA_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */
3155 #define ARIZONA_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */
3156 #define ARIZONA_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */
3157 #define ARIZONA_SPK2_MUTE_SEQ_MASK 0x00FF /* SPK2_MUTE_SEQ - [7:0] */
3158 #define ARIZONA_SPK2_MUTE_SEQ_SHIFT 0 /* SPK2_MUTE_SEQ - [7:0] */
3159 #define ARIZONA_SPK2_MUTE_SEQ_WIDTH 8 /* SPK2_MUTE_SEQ - [7:0] */
3162 * R1171 (0x493) - PDM SPK2 CTRL 2
3164 #define ARIZONA_SPK2_FMT 0x0001 /* SPK2_FMT */
3165 #define ARIZONA_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */
3166 #define ARIZONA_SPK2_FMT_SHIFT 0 /* SPK2_FMT */
3167 #define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */
3170 * R1244 (0x4DC) - DAC comp 1
3172 #define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */
3173 #define ARIZONA_OUT_COMP_COEFF_SHIFT 0 /* OUT_COMP_COEFF - [15:0] */
3174 #define ARIZONA_OUT_COMP_COEFF_WIDTH 16 /* OUT_COMP_COEFF - [15:0] */
3177 * R1245 (0x4DD) - DAC comp 2
3179 #define ARIZONA_OUT_COMP_COEFF_1 0x0002 /* OUT_COMP_COEFF */
3180 #define ARIZONA_OUT_COMP_COEFF_1_MASK 0x0002 /* OUT_COMP_COEFF */
3181 #define ARIZONA_OUT_COMP_COEFF_1_SHIFT 1 /* OUT_COMP_COEFF */
3182 #define ARIZONA_OUT_COMP_COEFF_1_WIDTH 1 /* OUT_COMP_COEFF */
3183 #define ARIZONA_OUT_COMP_COEFF_SEL 0x0001 /* OUT_COMP_COEFF_SEL */
3184 #define ARIZONA_OUT_COMP_COEFF_SEL_MASK 0x0001 /* OUT_COMP_COEFF_SEL */
3185 #define ARIZONA_OUT_COMP_COEFF_SEL_SHIFT 0 /* OUT_COMP_COEFF_SEL */
3186 #define ARIZONA_OUT_COMP_COEFF_SEL_WIDTH 1 /* OUT_COMP_COEFF_SEL */
3189 * R1246 (0x4DE) - DAC comp 3
3191 #define ARIZONA_AEC_COMP_COEFF_MASK 0xFFFF /* AEC_COMP_COEFF - [15:0] */
3192 #define ARIZONA_AEC_COMP_COEFF_SHIFT 0 /* AEC_COMP_COEFF - [15:0] */
3193 #define ARIZONA_AEC_COMP_COEFF_WIDTH 16 /* AEC_COMP_COEFF - [15:0] */
3196 * R1247 (0x4DF) - DAC comp 4
3198 #define ARIZONA_AEC_COMP_COEFF_1 0x0002 /* AEC_COMP_COEFF */
3199 #define ARIZONA_AEC_COMP_COEFF_1_MASK 0x0002 /* AEC_COMP_COEFF */
3200 #define ARIZONA_AEC_COMP_COEFF_1_SHIFT 1 /* AEC_COMP_COEFF */
3201 #define ARIZONA_AEC_COMP_COEFF_1_WIDTH 1 /* AEC_COMP_COEFF */
3202 #define ARIZONA_AEC_COMP_COEFF_SEL 0x0001 /* AEC_COMP_COEFF_SEL */
3203 #define ARIZONA_AEC_COMP_COEFF_SEL_MASK 0x0001 /* AEC_COMP_COEFF_SEL */
3204 #define ARIZONA_AEC_COMP_COEFF_SEL_SHIFT 0 /* AEC_COMP_COEFF_SEL */
3205 #define ARIZONA_AEC_COMP_COEFF_SEL_WIDTH 1 /* AEC_COMP_COEFF_SEL */
3208 * R1280 (0x500) - AIF1 BCLK Ctrl
3210 #define ARIZONA_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */
3211 #define ARIZONA_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */
3212 #define ARIZONA_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */
3213 #define ARIZONA_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
3214 #define ARIZONA_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */
3215 #define ARIZONA_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */
3216 #define ARIZONA_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */
3217 #define ARIZONA_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
3218 #define ARIZONA_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */
3219 #define ARIZONA_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */
3220 #define ARIZONA_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */
3221 #define ARIZONA_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
3222 #define ARIZONA_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */
3223 #define ARIZONA_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */
3224 #define ARIZONA_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */
3227 * R1281 (0x501) - AIF1 Tx Pin Ctrl
3229 #define ARIZONA_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
3230 #define ARIZONA_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
3231 #define ARIZONA_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
3232 #define ARIZONA_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
3233 #define ARIZONA_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
3234 #define ARIZONA_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
3235 #define ARIZONA_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
3236 #define ARIZONA_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
3237 #define ARIZONA_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
3238 #define ARIZONA_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
3239 #define ARIZONA_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
3240 #define ARIZONA_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
3241 #define ARIZONA_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
3242 #define ARIZONA_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
3243 #define ARIZONA_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
3244 #define ARIZONA_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
3245 #define ARIZONA_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
3246 #define ARIZONA_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
3247 #define ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
3248 #define ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
3251 * R1282 (0x502) - AIF1 Rx Pin Ctrl
3253 #define ARIZONA_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
3254 #define ARIZONA_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
3255 #define ARIZONA_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
3256 #define ARIZONA_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
3257 #define ARIZONA_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
3258 #define ARIZONA_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
3259 #define ARIZONA_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
3260 #define ARIZONA_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
3261 #define ARIZONA_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
3262 #define ARIZONA_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
3263 #define ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
3264 #define ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
3267 * R1283 (0x503) - AIF1 Rate Ctrl
3269 #define ARIZONA_AIF1_RATE_MASK 0x7800 /* AIF1_RATE - [14:11] */
3270 #define ARIZONA_AIF1_RATE_SHIFT 11 /* AIF1_RATE - [14:11] */
3271 #define ARIZONA_AIF1_RATE_WIDTH 4 /* AIF1_RATE - [14:11] */
3272 #define ARIZONA_AIF1_TRI 0x0040 /* AIF1_TRI */
3273 #define ARIZONA_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
3274 #define ARIZONA_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
3275 #define ARIZONA_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
3278 * R1284 (0x504) - AIF1 Format
3280 #define ARIZONA_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
3281 #define ARIZONA_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
3282 #define ARIZONA_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
3285 * R1285 (0x505) - AIF1 Tx BCLK Rate
3287 #define ARIZONA_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */
3288 #define ARIZONA_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */
3289 #define ARIZONA_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */
3292 * R1286 (0x506) - AIF1 Rx BCLK Rate
3294 #define ARIZONA_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */
3295 #define ARIZONA_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */
3296 #define ARIZONA_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */
3299 * R1287 (0x507) - AIF1 Frame Ctrl 1
3301 #define ARIZONA_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
3302 #define ARIZONA_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
3303 #define ARIZONA_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
3304 #define ARIZONA_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
3305 #define ARIZONA_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
3306 #define ARIZONA_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
3309 * R1288 (0x508) - AIF1 Frame Ctrl 2
3311 #define ARIZONA_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
3312 #define ARIZONA_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
3313 #define ARIZONA_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
3314 #define ARIZONA_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
3315 #define ARIZONA_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
3316 #define ARIZONA_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
3319 * R1289 (0x509) - AIF1 Frame Ctrl 3
3321 #define ARIZONA_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
3322 #define ARIZONA_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
3323 #define ARIZONA_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
3326 * R1290 (0x50A) - AIF1 Frame Ctrl 4
3328 #define ARIZONA_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
3329 #define ARIZONA_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
3330 #define ARIZONA_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
3333 * R1291 (0x50B) - AIF1 Frame Ctrl 5
3335 #define ARIZONA_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
3336 #define ARIZONA_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
3337 #define ARIZONA_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
3340 * R1292 (0x50C) - AIF1 Frame Ctrl 6
3342 #define ARIZONA_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
3343 #define ARIZONA_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
3344 #define ARIZONA_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
3347 * R1293 (0x50D) - AIF1 Frame Ctrl 7
3349 #define ARIZONA_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
3350 #define ARIZONA_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
3351 #define ARIZONA_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
3354 * R1294 (0x50E) - AIF1 Frame Ctrl 8
3356 #define ARIZONA_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
3357 #define ARIZONA_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
3358 #define ARIZONA_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
3361 * R1295 (0x50F) - AIF1 Frame Ctrl 9
3363 #define ARIZONA_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */
3364 #define ARIZONA_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */
3365 #define ARIZONA_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */
3368 * R1296 (0x510) - AIF1 Frame Ctrl 10
3370 #define ARIZONA_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */
3371 #define ARIZONA_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */
3372 #define ARIZONA_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */
3375 * R1297 (0x511) - AIF1 Frame Ctrl 11
3377 #define ARIZONA_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
3378 #define ARIZONA_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
3379 #define ARIZONA_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
3382 * R1298 (0x512) - AIF1 Frame Ctrl 12
3384 #define ARIZONA_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
3385 #define ARIZONA_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
3386 #define ARIZONA_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
3389 * R1299 (0x513) - AIF1 Frame Ctrl 13
3391 #define ARIZONA_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
3392 #define ARIZONA_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
3393 #define ARIZONA_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
3396 * R1300 (0x514) - AIF1 Frame Ctrl 14
3398 #define ARIZONA_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
3399 #define ARIZONA_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
3400 #define ARIZONA_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
3403 * R1301 (0x515) - AIF1 Frame Ctrl 15
3405 #define ARIZONA_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
3406 #define ARIZONA_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
3407 #define ARIZONA_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
3410 * R1302 (0x516) - AIF1 Frame Ctrl 16
3412 #define ARIZONA_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
3413 #define ARIZONA_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
3414 #define ARIZONA_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
3417 * R1303 (0x517) - AIF1 Frame Ctrl 17
3419 #define ARIZONA_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */
3420 #define ARIZONA_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */
3421 #define ARIZONA_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */
3424 * R1304 (0x518) - AIF1 Frame Ctrl 18
3426 #define ARIZONA_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */
3427 #define ARIZONA_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */
3428 #define ARIZONA_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */
3431 * R1305 (0x519) - AIF1 Tx Enables
3433 #define ARIZONA_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */
3434 #define ARIZONA_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */
3435 #define ARIZONA_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */
3436 #define ARIZONA_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */
3437 #define ARIZONA_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */
3438 #define ARIZONA_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */
3439 #define ARIZONA_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */
3440 #define ARIZONA_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */
3441 #define ARIZONA_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
3442 #define ARIZONA_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
3443 #define ARIZONA_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
3444 #define ARIZONA_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
3445 #define ARIZONA_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
3446 #define ARIZONA_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
3447 #define ARIZONA_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
3448 #define ARIZONA_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
3449 #define ARIZONA_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
3450 #define ARIZONA_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
3451 #define ARIZONA_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
3452 #define ARIZONA_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
3453 #define ARIZONA_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
3454 #define ARIZONA_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
3455 #define ARIZONA_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
3456 #define ARIZONA_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
3457 #define ARIZONA_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
3458 #define ARIZONA_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
3459 #define ARIZONA_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
3460 #define ARIZONA_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
3461 #define ARIZONA_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
3462 #define ARIZONA_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
3463 #define ARIZONA_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
3464 #define ARIZONA_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
3467 * R1306 (0x51A) - AIF1 Rx Enables
3469 #define ARIZONA_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */
3470 #define ARIZONA_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */
3471 #define ARIZONA_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */
3472 #define ARIZONA_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */
3473 #define ARIZONA_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */
3474 #define ARIZONA_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */
3475 #define ARIZONA_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */
3476 #define ARIZONA_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */
3477 #define ARIZONA_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */
3478 #define ARIZONA_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */
3479 #define ARIZONA_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */
3480 #define ARIZONA_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
3481 #define ARIZONA_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */
3482 #define ARIZONA_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */
3483 #define ARIZONA_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */
3484 #define ARIZONA_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
3485 #define ARIZONA_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */
3486 #define ARIZONA_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */
3487 #define ARIZONA_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */
3488 #define ARIZONA_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
3489 #define ARIZONA_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */
3490 #define ARIZONA_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */
3491 #define ARIZONA_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */
3492 #define ARIZONA_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
3493 #define ARIZONA_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */
3494 #define ARIZONA_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */
3495 #define ARIZONA_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */
3496 #define ARIZONA_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
3497 #define ARIZONA_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */
3498 #define ARIZONA_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */
3499 #define ARIZONA_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */
3500 #define ARIZONA_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
3503 * R1307 (0x51B) - AIF1 Force Write
3505 #define ARIZONA_AIF1_FRC_WR 0x0001 /* AIF1_FRC_WR */
3506 #define ARIZONA_AIF1_FRC_WR_MASK 0x0001 /* AIF1_FRC_WR */
3507 #define ARIZONA_AIF1_FRC_WR_SHIFT 0 /* AIF1_FRC_WR */
3508 #define ARIZONA_AIF1_FRC_WR_WIDTH 1 /* AIF1_FRC_WR */
3511 * R1344 (0x540) - AIF2 BCLK Ctrl
3513 #define ARIZONA_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */
3514 #define ARIZONA_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */
3515 #define ARIZONA_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */
3516 #define ARIZONA_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
3517 #define ARIZONA_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */
3518 #define ARIZONA_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */
3519 #define ARIZONA_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */
3520 #define ARIZONA_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
3521 #define ARIZONA_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */
3522 #define ARIZONA_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */
3523 #define ARIZONA_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */
3524 #define ARIZONA_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
3525 #define ARIZONA_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */
3526 #define ARIZONA_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */
3527 #define ARIZONA_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */
3530 * R1345 (0x541) - AIF2 Tx Pin Ctrl
3532 #define ARIZONA_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */
3533 #define ARIZONA_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */
3534 #define ARIZONA_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */
3535 #define ARIZONA_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
3536 #define ARIZONA_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */
3537 #define ARIZONA_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */
3538 #define ARIZONA_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */
3539 #define ARIZONA_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */
3540 #define ARIZONA_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
3541 #define ARIZONA_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
3542 #define ARIZONA_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
3543 #define ARIZONA_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
3544 #define ARIZONA_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
3545 #define ARIZONA_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
3546 #define ARIZONA_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
3547 #define ARIZONA_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
3548 #define ARIZONA_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
3549 #define ARIZONA_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
3550 #define ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
3551 #define ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
3554 * R1346 (0x542) - AIF2 Rx Pin Ctrl
3556 #define ARIZONA_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
3557 #define ARIZONA_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
3558 #define ARIZONA_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
3559 #define ARIZONA_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
3560 #define ARIZONA_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
3561 #define ARIZONA_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
3562 #define ARIZONA_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
3563 #define ARIZONA_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
3564 #define ARIZONA_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
3565 #define ARIZONA_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
3566 #define ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
3567 #define ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
3570 * R1347 (0x543) - AIF2 Rate Ctrl
3572 #define ARIZONA_AIF2_RATE_MASK 0x7800 /* AIF2_RATE - [14:11] */
3573 #define ARIZONA_AIF2_RATE_SHIFT 11 /* AIF2_RATE - [14:11] */
3574 #define ARIZONA_AIF2_RATE_WIDTH 4 /* AIF2_RATE - [14:11] */
3575 #define ARIZONA_AIF2_TRI 0x0040 /* AIF2_TRI */
3576 #define ARIZONA_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */
3577 #define ARIZONA_AIF2_TRI_SHIFT 6 /* AIF2_TRI */
3578 #define ARIZONA_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
3581 * R1348 (0x544) - AIF2 Format
3583 #define ARIZONA_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */
3584 #define ARIZONA_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */
3585 #define ARIZONA_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */
3588 * R1349 (0x545) - AIF2 Tx BCLK Rate
3590 #define ARIZONA_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */
3591 #define ARIZONA_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */
3592 #define ARIZONA_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */
3595 * R1350 (0x546) - AIF2 Rx BCLK Rate
3597 #define ARIZONA_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */
3598 #define ARIZONA_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */
3599 #define ARIZONA_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */
3602 * R1351 (0x547) - AIF2 Frame Ctrl 1
3604 #define ARIZONA_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */
3605 #define ARIZONA_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */
3606 #define ARIZONA_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */
3607 #define ARIZONA_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
3608 #define ARIZONA_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
3609 #define ARIZONA_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
3612 * R1352 (0x548) - AIF2 Frame Ctrl 2
3614 #define ARIZONA_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */
3615 #define ARIZONA_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */
3616 #define ARIZONA_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */
3617 #define ARIZONA_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
3618 #define ARIZONA_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
3619 #define ARIZONA_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
3622 * R1353 (0x549) - AIF2 Frame Ctrl 3
3624 #define ARIZONA_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */
3625 #define ARIZONA_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */
3626 #define ARIZONA_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */
3629 * R1354 (0x54A) - AIF2 Frame Ctrl 4
3631 #define ARIZONA_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */
3632 #define ARIZONA_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */
3633 #define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */
3636 * R1361 (0x551) - AIF2 Frame Ctrl 11
3638 #define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */
3639 #define ARIZONA_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */
3640 #define ARIZONA_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */
3643 * R1362 (0x552) - AIF2 Frame Ctrl 12
3645 #define ARIZONA_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */
3646 #define ARIZONA_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */
3647 #define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */
3650 * R1369 (0x559) - AIF2 Tx Enables
3652 #define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */
3653 #define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */
3654 #define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */
3655 #define ARIZONA_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */
3656 #define ARIZONA_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */
3657 #define ARIZONA_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */
3658 #define ARIZONA_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */
3659 #define ARIZONA_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */
3662 * R1370 (0x55A) - AIF2 Rx Enables
3664 #define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */
3665 #define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */
3666 #define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */
3667 #define ARIZONA_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */
3668 #define ARIZONA_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */
3669 #define ARIZONA_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */
3670 #define ARIZONA_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */
3671 #define ARIZONA_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */
3674 * R1371 (0x55B) - AIF2 Force Write
3676 #define ARIZONA_AIF2_FRC_WR 0x0001 /* AIF2_FRC_WR */
3677 #define ARIZONA_AIF2_FRC_WR_MASK 0x0001 /* AIF2_FRC_WR */
3678 #define ARIZONA_AIF2_FRC_WR_SHIFT 0 /* AIF2_FRC_WR */
3679 #define ARIZONA_AIF2_FRC_WR_WIDTH 1 /* AIF2_FRC_WR */
3682 * R1408 (0x580) - AIF3 BCLK Ctrl
3684 #define ARIZONA_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */
3685 #define ARIZONA_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */
3686 #define ARIZONA_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */
3687 #define ARIZONA_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */
3688 #define ARIZONA_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */
3689 #define ARIZONA_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */
3690 #define ARIZONA_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */
3691 #define ARIZONA_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */
3692 #define ARIZONA_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */
3693 #define ARIZONA_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */
3694 #define ARIZONA_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */
3695 #define ARIZONA_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */
3696 #define ARIZONA_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */
3697 #define ARIZONA_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */
3698 #define ARIZONA_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */
3701 * R1409 (0x581) - AIF3 Tx Pin Ctrl
3703 #define ARIZONA_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */
3704 #define ARIZONA_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */
3705 #define ARIZONA_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */
3706 #define ARIZONA_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */
3707 #define ARIZONA_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */
3708 #define ARIZONA_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */
3709 #define ARIZONA_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */
3710 #define ARIZONA_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */
3711 #define ARIZONA_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */
3712 #define ARIZONA_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */
3713 #define ARIZONA_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */
3714 #define ARIZONA_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */
3715 #define ARIZONA_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */
3716 #define ARIZONA_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */
3717 #define ARIZONA_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */
3718 #define ARIZONA_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */
3719 #define ARIZONA_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */
3720 #define ARIZONA_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */
3721 #define ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */
3722 #define ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */
3725 * R1410 (0x582) - AIF3 Rx Pin Ctrl
3727 #define ARIZONA_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */
3728 #define ARIZONA_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */
3729 #define ARIZONA_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */
3730 #define ARIZONA_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */
3731 #define ARIZONA_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */
3732 #define ARIZONA_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */
3733 #define ARIZONA_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */
3734 #define ARIZONA_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */
3735 #define ARIZONA_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */
3736 #define ARIZONA_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */
3737 #define ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */
3738 #define ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */
3741 * R1411 (0x583) - AIF3 Rate Ctrl
3743 #define ARIZONA_AIF3_RATE_MASK 0x7800 /* AIF3_RATE - [14:11] */
3744 #define ARIZONA_AIF3_RATE_SHIFT 11 /* AIF3_RATE - [14:11] */
3745 #define ARIZONA_AIF3_RATE_WIDTH 4 /* AIF3_RATE - [14:11] */
3746 #define ARIZONA_AIF3_TRI 0x0040 /* AIF3_TRI */
3747 #define ARIZONA_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */
3748 #define ARIZONA_AIF3_TRI_SHIFT 6 /* AIF3_TRI */
3749 #define ARIZONA_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
3752 * R1412 (0x584) - AIF3 Format
3754 #define ARIZONA_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */
3755 #define ARIZONA_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */
3756 #define ARIZONA_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */
3759 * R1413 (0x585) - AIF3 Tx BCLK Rate
3761 #define ARIZONA_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */
3762 #define ARIZONA_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */
3763 #define ARIZONA_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */
3766 * R1414 (0x586) - AIF3 Rx BCLK Rate
3768 #define ARIZONA_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */
3769 #define ARIZONA_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */
3770 #define ARIZONA_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */
3773 * R1415 (0x587) - AIF3 Frame Ctrl 1
3775 #define ARIZONA_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */
3776 #define ARIZONA_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */
3777 #define ARIZONA_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */
3778 #define ARIZONA_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */
3779 #define ARIZONA_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */
3780 #define ARIZONA_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */
3783 * R1416 (0x588) - AIF3 Frame Ctrl 2
3785 #define ARIZONA_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */
3786 #define ARIZONA_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */
3787 #define ARIZONA_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */
3788 #define ARIZONA_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */
3789 #define ARIZONA_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */
3790 #define ARIZONA_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */
3793 * R1417 (0x589) - AIF3 Frame Ctrl 3
3795 #define ARIZONA_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */
3796 #define ARIZONA_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */
3797 #define ARIZONA_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */
3800 * R1418 (0x58A) - AIF3 Frame Ctrl 4
3802 #define ARIZONA_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */
3803 #define ARIZONA_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */
3804 #define ARIZONA_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */
3807 * R1425 (0x591) - AIF3 Frame Ctrl 11
3809 #define ARIZONA_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */
3810 #define ARIZONA_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */
3811 #define ARIZONA_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */
3814 * R1426 (0x592) - AIF3 Frame Ctrl 12
3816 #define ARIZONA_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */
3817 #define ARIZONA_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */
3818 #define ARIZONA_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */
3821 * R1433 (0x599) - AIF3 Tx Enables
3823 #define ARIZONA_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */
3824 #define ARIZONA_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */
3825 #define ARIZONA_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */
3826 #define ARIZONA_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */
3827 #define ARIZONA_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */
3828 #define ARIZONA_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */
3829 #define ARIZONA_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */
3830 #define ARIZONA_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */
3833 * R1434 (0x59A) - AIF3 Rx Enables
3835 #define ARIZONA_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */
3836 #define ARIZONA_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */
3837 #define ARIZONA_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */
3838 #define ARIZONA_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */
3839 #define ARIZONA_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */
3840 #define ARIZONA_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */
3841 #define ARIZONA_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */
3842 #define ARIZONA_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */
3845 * R1435 (0x59B) - AIF3 Force Write
3847 #define ARIZONA_AIF3_FRC_WR 0x0001 /* AIF3_FRC_WR */
3848 #define ARIZONA_AIF3_FRC_WR_MASK 0x0001 /* AIF3_FRC_WR */
3849 #define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */
3850 #define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */
3853 * R1507 (0x5E3) - SLIMbus Framer Ref Gear
3855 #define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */
3856 #define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */
3857 #define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */
3858 #define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */
3859 #define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */
3860 #define ARIZONA_FRAMER_REF_GEAR_SHIFT 0 /* FRAMER_REF_GEAR - [3:0] */
3861 #define ARIZONA_FRAMER_REF_GEAR_WIDTH 4 /* FRAMER_REF_GEAR - [3:0] */
3864 * R1509 (0x5E5) - SLIMbus Rates 1
3866 #define ARIZONA_SLIMRX2_RATE_MASK 0x7800 /* SLIMRX2_RATE - [14:11] */
3867 #define ARIZONA_SLIMRX2_RATE_SHIFT 11 /* SLIMRX2_RATE - [14:11] */
3868 #define ARIZONA_SLIMRX2_RATE_WIDTH 4 /* SLIMRX2_RATE - [14:11] */
3869 #define ARIZONA_SLIMRX1_RATE_MASK 0x0078 /* SLIMRX1_RATE - [6:3] */
3870 #define ARIZONA_SLIMRX1_RATE_SHIFT 3 /* SLIMRX1_RATE - [6:3] */
3871 #define ARIZONA_SLIMRX1_RATE_WIDTH 4 /* SLIMRX1_RATE - [6:3] */
3874 * R1510 (0x5E6) - SLIMbus Rates 2
3876 #define ARIZONA_SLIMRX4_RATE_MASK 0x7800 /* SLIMRX4_RATE - [14:11] */
3877 #define ARIZONA_SLIMRX4_RATE_SHIFT 11 /* SLIMRX4_RATE - [14:11] */
3878 #define ARIZONA_SLIMRX4_RATE_WIDTH 4 /* SLIMRX4_RATE - [14:11] */
3879 #define ARIZONA_SLIMRX3_RATE_MASK 0x0078 /* SLIMRX3_RATE - [6:3] */
3880 #define ARIZONA_SLIMRX3_RATE_SHIFT 3 /* SLIMRX3_RATE - [6:3] */
3881 #define ARIZONA_SLIMRX3_RATE_WIDTH 4 /* SLIMRX3_RATE - [6:3] */
3884 * R1511 (0x5E7) - SLIMbus Rates 3
3886 #define ARIZONA_SLIMRX6_RATE_MASK 0x7800 /* SLIMRX6_RATE - [14:11] */
3887 #define ARIZONA_SLIMRX6_RATE_SHIFT 11 /* SLIMRX6_RATE - [14:11] */
3888 #define ARIZONA_SLIMRX6_RATE_WIDTH 4 /* SLIMRX6_RATE - [14:11] */
3889 #define ARIZONA_SLIMRX5_RATE_MASK 0x0078 /* SLIMRX5_RATE - [6:3] */
3890 #define ARIZONA_SLIMRX5_RATE_SHIFT 3 /* SLIMRX5_RATE - [6:3] */
3891 #define ARIZONA_SLIMRX5_RATE_WIDTH 4 /* SLIMRX5_RATE - [6:3] */
3894 * R1512 (0x5E8) - SLIMbus Rates 4
3896 #define ARIZONA_SLIMRX8_RATE_MASK 0x7800 /* SLIMRX8_RATE - [14:11] */
3897 #define ARIZONA_SLIMRX8_RATE_SHIFT 11 /* SLIMRX8_RATE - [14:11] */
3898 #define ARIZONA_SLIMRX8_RATE_WIDTH 4 /* SLIMRX8_RATE - [14:11] */
3899 #define ARIZONA_SLIMRX7_RATE_MASK 0x0078 /* SLIMRX7_RATE - [6:3] */
3900 #define ARIZONA_SLIMRX7_RATE_SHIFT 3 /* SLIMRX7_RATE - [6:3] */
3901 #define ARIZONA_SLIMRX7_RATE_WIDTH 4 /* SLIMRX7_RATE - [6:3] */
3904 * R1513 (0x5E9) - SLIMbus Rates 5
3906 #define ARIZONA_SLIMTX2_RATE_MASK 0x7800 /* SLIMTX2_RATE - [14:11] */
3907 #define ARIZONA_SLIMTX2_RATE_SHIFT 11 /* SLIMTX2_RATE - [14:11] */
3908 #define ARIZONA_SLIMTX2_RATE_WIDTH 4 /* SLIMTX2_RATE - [14:11] */
3909 #define ARIZONA_SLIMTX1_RATE_MASK 0x0078 /* SLIMTX1_RATE - [6:3] */
3910 #define ARIZONA_SLIMTX1_RATE_SHIFT 3 /* SLIMTX1_RATE - [6:3] */
3911 #define ARIZONA_SLIMTX1_RATE_WIDTH 4 /* SLIMTX1_RATE - [6:3] */
3914 * R1514 (0x5EA) - SLIMbus Rates 6
3916 #define ARIZONA_SLIMTX4_RATE_MASK 0x7800 /* SLIMTX4_RATE - [14:11] */
3917 #define ARIZONA_SLIMTX4_RATE_SHIFT 11 /* SLIMTX4_RATE - [14:11] */
3918 #define ARIZONA_SLIMTX4_RATE_WIDTH 4 /* SLIMTX4_RATE - [14:11] */
3919 #define ARIZONA_SLIMTX3_RATE_MASK 0x0078 /* SLIMTX3_RATE - [6:3] */
3920 #define ARIZONA_SLIMTX3_RATE_SHIFT 3 /* SLIMTX3_RATE - [6:3] */
3921 #define ARIZONA_SLIMTX3_RATE_WIDTH 4 /* SLIMTX3_RATE - [6:3] */
3924 * R1515 (0x5EB) - SLIMbus Rates 7
3926 #define ARIZONA_SLIMTX6_RATE_MASK 0x7800 /* SLIMTX6_RATE - [14:11] */
3927 #define ARIZONA_SLIMTX6_RATE_SHIFT 11 /* SLIMTX6_RATE - [14:11] */
3928 #define ARIZONA_SLIMTX6_RATE_WIDTH 4 /* SLIMTX6_RATE - [14:11] */
3929 #define ARIZONA_SLIMTX5_RATE_MASK 0x0078 /* SLIMTX5_RATE - [6:3] */
3930 #define ARIZONA_SLIMTX5_RATE_SHIFT 3 /* SLIMTX5_RATE - [6:3] */
3931 #define ARIZONA_SLIMTX5_RATE_WIDTH 4 /* SLIMTX5_RATE - [6:3] */
3934 * R1516 (0x5EC) - SLIMbus Rates 8
3936 #define ARIZONA_SLIMTX8_RATE_MASK 0x7800 /* SLIMTX8_RATE - [14:11] */
3937 #define ARIZONA_SLIMTX8_RATE_SHIFT 11 /* SLIMTX8_RATE - [14:11] */
3938 #define ARIZONA_SLIMTX8_RATE_WIDTH 4 /* SLIMTX8_RATE - [14:11] */
3939 #define ARIZONA_SLIMTX7_RATE_MASK 0x0078 /* SLIMTX7_RATE - [6:3] */
3940 #define ARIZONA_SLIMTX7_RATE_SHIFT 3 /* SLIMTX7_RATE - [6:3] */
3941 #define ARIZONA_SLIMTX7_RATE_WIDTH 4 /* SLIMTX7_RATE - [6:3] */
3944 * R1525 (0x5F5) - SLIMbus RX Channel Enable
3946 #define ARIZONA_SLIMRX8_ENA 0x0080 /* SLIMRX8_ENA */
3947 #define ARIZONA_SLIMRX8_ENA_MASK 0x0080 /* SLIMRX8_ENA */
3948 #define ARIZONA_SLIMRX8_ENA_SHIFT 7 /* SLIMRX8_ENA */
3949 #define ARIZONA_SLIMRX8_ENA_WIDTH 1 /* SLIMRX8_ENA */
3950 #define ARIZONA_SLIMRX7_ENA 0x0040 /* SLIMRX7_ENA */
3951 #define ARIZONA_SLIMRX7_ENA_MASK 0x0040 /* SLIMRX7_ENA */
3952 #define ARIZONA_SLIMRX7_ENA_SHIFT 6 /* SLIMRX7_ENA */
3953 #define ARIZONA_SLIMRX7_ENA_WIDTH 1 /* SLIMRX7_ENA */
3954 #define ARIZONA_SLIMRX6_ENA 0x0020 /* SLIMRX6_ENA */
3955 #define ARIZONA_SLIMRX6_ENA_MASK 0x0020 /* SLIMRX6_ENA */
3956 #define ARIZONA_SLIMRX6_ENA_SHIFT 5 /* SLIMRX6_ENA */
3957 #define ARIZONA_SLIMRX6_ENA_WIDTH 1 /* SLIMRX6_ENA */
3958 #define ARIZONA_SLIMRX5_ENA 0x0010 /* SLIMRX5_ENA */
3959 #define ARIZONA_SLIMRX5_ENA_MASK 0x0010 /* SLIMRX5_ENA */
3960 #define ARIZONA_SLIMRX5_ENA_SHIFT 4 /* SLIMRX5_ENA */
3961 #define ARIZONA_SLIMRX5_ENA_WIDTH 1 /* SLIMRX5_ENA */
3962 #define ARIZONA_SLIMRX4_ENA 0x0008 /* SLIMRX4_ENA */
3963 #define ARIZONA_SLIMRX4_ENA_MASK 0x0008 /* SLIMRX4_ENA */
3964 #define ARIZONA_SLIMRX4_ENA_SHIFT 3 /* SLIMRX4_ENA */
3965 #define ARIZONA_SLIMRX4_ENA_WIDTH 1 /* SLIMRX4_ENA */
3966 #define ARIZONA_SLIMRX3_ENA 0x0004 /* SLIMRX3_ENA */
3967 #define ARIZONA_SLIMRX3_ENA_MASK 0x0004 /* SLIMRX3_ENA */
3968 #define ARIZONA_SLIMRX3_ENA_SHIFT 2 /* SLIMRX3_ENA */
3969 #define ARIZONA_SLIMRX3_ENA_WIDTH 1 /* SLIMRX3_ENA */
3970 #define ARIZONA_SLIMRX2_ENA 0x0002 /* SLIMRX2_ENA */
3971 #define ARIZONA_SLIMRX2_ENA_MASK 0x0002 /* SLIMRX2_ENA */
3972 #define ARIZONA_SLIMRX2_ENA_SHIFT 1 /* SLIMRX2_ENA */
3973 #define ARIZONA_SLIMRX2_ENA_WIDTH 1 /* SLIMRX2_ENA */
3974 #define ARIZONA_SLIMRX1_ENA 0x0001 /* SLIMRX1_ENA */
3975 #define ARIZONA_SLIMRX1_ENA_MASK 0x0001 /* SLIMRX1_ENA */
3976 #define ARIZONA_SLIMRX1_ENA_SHIFT 0 /* SLIMRX1_ENA */
3977 #define ARIZONA_SLIMRX1_ENA_WIDTH 1 /* SLIMRX1_ENA */
3980 * R1526 (0x5F6) - SLIMbus TX Channel Enable
3982 #define ARIZONA_SLIMTX8_ENA 0x0080 /* SLIMTX8_ENA */
3983 #define ARIZONA_SLIMTX8_ENA_MASK 0x0080 /* SLIMTX8_ENA */
3984 #define ARIZONA_SLIMTX8_ENA_SHIFT 7 /* SLIMTX8_ENA */
3985 #define ARIZONA_SLIMTX8_ENA_WIDTH 1 /* SLIMTX8_ENA */
3986 #define ARIZONA_SLIMTX7_ENA 0x0040 /* SLIMTX7_ENA */
3987 #define ARIZONA_SLIMTX7_ENA_MASK 0x0040 /* SLIMTX7_ENA */
3988 #define ARIZONA_SLIMTX7_ENA_SHIFT 6 /* SLIMTX7_ENA */
3989 #define ARIZONA_SLIMTX7_ENA_WIDTH 1 /* SLIMTX7_ENA */
3990 #define ARIZONA_SLIMTX6_ENA 0x0020 /* SLIMTX6_ENA */
3991 #define ARIZONA_SLIMTX6_ENA_MASK 0x0020 /* SLIMTX6_ENA */
3992 #define ARIZONA_SLIMTX6_ENA_SHIFT 5 /* SLIMTX6_ENA */
3993 #define ARIZONA_SLIMTX6_ENA_WIDTH 1 /* SLIMTX6_ENA */
3994 #define ARIZONA_SLIMTX5_ENA 0x0010 /* SLIMTX5_ENA */
3995 #define ARIZONA_SLIMTX5_ENA_MASK 0x0010 /* SLIMTX5_ENA */
3996 #define ARIZONA_SLIMTX5_ENA_SHIFT 4 /* SLIMTX5_ENA */
3997 #define ARIZONA_SLIMTX5_ENA_WIDTH 1 /* SLIMTX5_ENA */
3998 #define ARIZONA_SLIMTX4_ENA 0x0008 /* SLIMTX4_ENA */
3999 #define ARIZONA_SLIMTX4_ENA_MASK 0x0008 /* SLIMTX4_ENA */
4000 #define ARIZONA_SLIMTX4_ENA_SHIFT 3 /* SLIMTX4_ENA */
4001 #define ARIZONA_SLIMTX4_ENA_WIDTH 1 /* SLIMTX4_ENA */
4002 #define ARIZONA_SLIMTX3_ENA 0x0004 /* SLIMTX3_ENA */
4003 #define ARIZONA_SLIMTX3_ENA_MASK 0x0004 /* SLIMTX3_ENA */
4004 #define ARIZONA_SLIMTX3_ENA_SHIFT 2 /* SLIMTX3_ENA */
4005 #define ARIZONA_SLIMTX3_ENA_WIDTH 1 /* SLIMTX3_ENA */
4006 #define ARIZONA_SLIMTX2_ENA 0x0002 /* SLIMTX2_ENA */
4007 #define ARIZONA_SLIMTX2_ENA_MASK 0x0002 /* SLIMTX2_ENA */
4008 #define ARIZONA_SLIMTX2_ENA_SHIFT 1 /* SLIMTX2_ENA */
4009 #define ARIZONA_SLIMTX2_ENA_WIDTH 1 /* SLIMTX2_ENA */
4010 #define ARIZONA_SLIMTX1_ENA 0x0001 /* SLIMTX1_ENA */
4011 #define ARIZONA_SLIMTX1_ENA_MASK 0x0001 /* SLIMTX1_ENA */
4012 #define ARIZONA_SLIMTX1_ENA_SHIFT 0 /* SLIMTX1_ENA */
4013 #define ARIZONA_SLIMTX1_ENA_WIDTH 1 /* SLIMTX1_ENA */
4016 * R1527 (0x5F7) - SLIMbus RX Port Status
4018 #define ARIZONA_SLIMRX8_PORT_STS 0x0080 /* SLIMRX8_PORT_STS */
4019 #define ARIZONA_SLIMRX8_PORT_STS_MASK 0x0080 /* SLIMRX8_PORT_STS */
4020 #define ARIZONA_SLIMRX8_PORT_STS_SHIFT 7 /* SLIMRX8_PORT_STS */
4021 #define ARIZONA_SLIMRX8_PORT_STS_WIDTH 1 /* SLIMRX8_PORT_STS */
4022 #define ARIZONA_SLIMRX7_PORT_STS 0x0040 /* SLIMRX7_PORT_STS */
4023 #define ARIZONA_SLIMRX7_PORT_STS_MASK 0x0040 /* SLIMRX7_PORT_STS */
4024 #define ARIZONA_SLIMRX7_PORT_STS_SHIFT 6 /* SLIMRX7_PORT_STS */
4025 #define ARIZONA_SLIMRX7_PORT_STS_WIDTH 1 /* SLIMRX7_PORT_STS */
4026 #define ARIZONA_SLIMRX6_PORT_STS 0x0020 /* SLIMRX6_PORT_STS */
4027 #define ARIZONA_SLIMRX6_PORT_STS_MASK 0x0020 /* SLIMRX6_PORT_STS */
4028 #define ARIZONA_SLIMRX6_PORT_STS_SHIFT 5 /* SLIMRX6_PORT_STS */
4029 #define ARIZONA_SLIMRX6_PORT_STS_WIDTH 1 /* SLIMRX6_PORT_STS */
4030 #define ARIZONA_SLIMRX5_PORT_STS 0x0010 /* SLIMRX5_PORT_STS */
4031 #define ARIZONA_SLIMRX5_PORT_STS_MASK 0x0010 /* SLIMRX5_PORT_STS */
4032 #define ARIZONA_SLIMRX5_PORT_STS_SHIFT 4 /* SLIMRX5_PORT_STS */
4033 #define ARIZONA_SLIMRX5_PORT_STS_WIDTH 1 /* SLIMRX5_PORT_STS */
4034 #define ARIZONA_SLIMRX4_PORT_STS 0x0008 /* SLIMRX4_PORT_STS */
4035 #define ARIZONA_SLIMRX4_PORT_STS_MASK 0x0008 /* SLIMRX4_PORT_STS */
4036 #define ARIZONA_SLIMRX4_PORT_STS_SHIFT 3 /* SLIMRX4_PORT_STS */
4037 #define ARIZONA_SLIMRX4_PORT_STS_WIDTH 1 /* SLIMRX4_PORT_STS */
4038 #define ARIZONA_SLIMRX3_PORT_STS 0x0004 /* SLIMRX3_PORT_STS */
4039 #define ARIZONA_SLIMRX3_PORT_STS_MASK 0x0004 /* SLIMRX3_PORT_STS */
4040 #define ARIZONA_SLIMRX3_PORT_STS_SHIFT 2 /* SLIMRX3_PORT_STS */
4041 #define ARIZONA_SLIMRX3_PORT_STS_WIDTH 1 /* SLIMRX3_PORT_STS */
4042 #define ARIZONA_SLIMRX2_PORT_STS 0x0002 /* SLIMRX2_PORT_STS */
4043 #define ARIZONA_SLIMRX2_PORT_STS_MASK 0x0002 /* SLIMRX2_PORT_STS */
4044 #define ARIZONA_SLIMRX2_PORT_STS_SHIFT 1 /* SLIMRX2_PORT_STS */
4045 #define ARIZONA_SLIMRX2_PORT_STS_WIDTH 1 /* SLIMRX2_PORT_STS */
4046 #define ARIZONA_SLIMRX1_PORT_STS 0x0001 /* SLIMRX1_PORT_STS */
4047 #define ARIZONA_SLIMRX1_PORT_STS_MASK 0x0001 /* SLIMRX1_PORT_STS */
4048 #define ARIZONA_SLIMRX1_PORT_STS_SHIFT 0 /* SLIMRX1_PORT_STS */
4049 #define ARIZONA_SLIMRX1_PORT_STS_WIDTH 1 /* SLIMRX1_PORT_STS */
4052 * R1528 (0x5F8) - SLIMbus TX Port Status
4054 #define ARIZONA_SLIMTX8_PORT_STS 0x0080 /* SLIMTX8_PORT_STS */
4055 #define ARIZONA_SLIMTX8_PORT_STS_MASK 0x0080 /* SLIMTX8_PORT_STS */
4056 #define ARIZONA_SLIMTX8_PORT_STS_SHIFT 7 /* SLIMTX8_PORT_STS */
4057 #define ARIZONA_SLIMTX8_PORT_STS_WIDTH 1 /* SLIMTX8_PORT_STS */
4058 #define ARIZONA_SLIMTX7_PORT_STS 0x0040 /* SLIMTX7_PORT_STS */
4059 #define ARIZONA_SLIMTX7_PORT_STS_MASK 0x0040 /* SLIMTX7_PORT_STS */
4060 #define ARIZONA_SLIMTX7_PORT_STS_SHIFT 6 /* SLIMTX7_PORT_STS */
4061 #define ARIZONA_SLIMTX7_PORT_STS_WIDTH 1 /* SLIMTX7_PORT_STS */
4062 #define ARIZONA_SLIMTX6_PORT_STS 0x0020 /* SLIMTX6_PORT_STS */
4063 #define ARIZONA_SLIMTX6_PORT_STS_MASK 0x0020 /* SLIMTX6_PORT_STS */
4064 #define ARIZONA_SLIMTX6_PORT_STS_SHIFT 5 /* SLIMTX6_PORT_STS */
4065 #define ARIZONA_SLIMTX6_PORT_STS_WIDTH 1 /* SLIMTX6_PORT_STS */
4066 #define ARIZONA_SLIMTX5_PORT_STS 0x0010 /* SLIMTX5_PORT_STS */
4067 #define ARIZONA_SLIMTX5_PORT_STS_MASK 0x0010 /* SLIMTX5_PORT_STS */
4068 #define ARIZONA_SLIMTX5_PORT_STS_SHIFT 4 /* SLIMTX5_PORT_STS */
4069 #define ARIZONA_SLIMTX5_PORT_STS_WIDTH 1 /* SLIMTX5_PORT_STS */
4070 #define ARIZONA_SLIMTX4_PORT_STS 0x0008 /* SLIMTX4_PORT_STS */
4071 #define ARIZONA_SLIMTX4_PORT_STS_MASK 0x0008 /* SLIMTX4_PORT_STS */
4072 #define ARIZONA_SLIMTX4_PORT_STS_SHIFT 3 /* SLIMTX4_PORT_STS */
4073 #define ARIZONA_SLIMTX4_PORT_STS_WIDTH 1 /* SLIMTX4_PORT_STS */
4074 #define ARIZONA_SLIMTX3_PORT_STS 0x0004 /* SLIMTX3_PORT_STS */
4075 #define ARIZONA_SLIMTX3_PORT_STS_MASK 0x0004 /* SLIMTX3_PORT_STS */
4076 #define ARIZONA_SLIMTX3_PORT_STS_SHIFT 2 /* SLIMTX3_PORT_STS */
4077 #define ARIZONA_SLIMTX3_PORT_STS_WIDTH 1 /* SLIMTX3_PORT_STS */
4078 #define ARIZONA_SLIMTX2_PORT_STS 0x0002 /* SLIMTX2_PORT_STS */
4079 #define ARIZONA_SLIMTX2_PORT_STS_MASK 0x0002 /* SLIMTX2_PORT_STS */
4080 #define ARIZONA_SLIMTX2_PORT_STS_SHIFT 1 /* SLIMTX2_PORT_STS */
4081 #define ARIZONA_SLIMTX2_PORT_STS_WIDTH 1 /* SLIMTX2_PORT_STS */
4082 #define ARIZONA_SLIMTX1_PORT_STS 0x0001 /* SLIMTX1_PORT_STS */
4083 #define ARIZONA_SLIMTX1_PORT_STS_MASK 0x0001 /* SLIMTX1_PORT_STS */
4084 #define ARIZONA_SLIMTX1_PORT_STS_SHIFT 0 /* SLIMTX1_PORT_STS */
4085 #define ARIZONA_SLIMTX1_PORT_STS_WIDTH 1 /* SLIMTX1_PORT_STS */
4088 * R3087 (0xC0F) - IRQ CTRL 1
4090 #define ARIZONA_IRQ_POL 0x0400 /* IRQ_POL */
4091 #define ARIZONA_IRQ_POL_MASK 0x0400 /* IRQ_POL */
4092 #define ARIZONA_IRQ_POL_SHIFT 10 /* IRQ_POL */
4093 #define ARIZONA_IRQ_POL_WIDTH 1 /* IRQ_POL */
4094 #define ARIZONA_IRQ_OP_CFG 0x0200 /* IRQ_OP_CFG */
4095 #define ARIZONA_IRQ_OP_CFG_MASK 0x0200 /* IRQ_OP_CFG */
4096 #define ARIZONA_IRQ_OP_CFG_SHIFT 9 /* IRQ_OP_CFG */
4097 #define ARIZONA_IRQ_OP_CFG_WIDTH 1 /* IRQ_OP_CFG */
4100 * R3088 (0xC10) - GPIO Debounce Config
4102 #define ARIZONA_GP_DBTIME_MASK 0xF000 /* GP_DBTIME - [15:12] */
4103 #define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */
4104 #define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */
4107 * R3104 (0xC20) - Misc Pad Ctrl 1
4109 #define ARIZONA_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
4110 #define ARIZONA_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
4111 #define ARIZONA_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
4112 #define ARIZONA_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
4113 #define ARIZONA_MCLK2_PD 0x2000 /* MCLK2_PD */
4114 #define ARIZONA_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
4115 #define ARIZONA_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
4116 #define ARIZONA_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
4117 #define ARIZONA_RSTB_PU 0x0002 /* RSTB_PU */
4118 #define ARIZONA_RSTB_PU_MASK 0x0002 /* RSTB_PU */
4119 #define ARIZONA_RSTB_PU_SHIFT 1 /* RSTB_PU */
4120 #define ARIZONA_RSTB_PU_WIDTH 1 /* RSTB_PU */
4123 * R3105 (0xC21) - Misc Pad Ctrl 2
4125 #define ARIZONA_MCLK1_PD 0x1000 /* MCLK1_PD */
4126 #define ARIZONA_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
4127 #define ARIZONA_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
4128 #define ARIZONA_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
4129 #define ARIZONA_MICD_PD 0x0100 /* MICD_PD */
4130 #define ARIZONA_MICD_PD_MASK 0x0100 /* MICD_PD */
4131 #define ARIZONA_MICD_PD_SHIFT 8 /* MICD_PD */
4132 #define ARIZONA_MICD_PD_WIDTH 1 /* MICD_PD */
4133 #define ARIZONA_ADDR_PD 0x0001 /* ADDR_PD */
4134 #define ARIZONA_ADDR_PD_MASK 0x0001 /* ADDR_PD */
4135 #define ARIZONA_ADDR_PD_SHIFT 0 /* ADDR_PD */
4136 #define ARIZONA_ADDR_PD_WIDTH 1 /* ADDR_PD */
4139 * R3106 (0xC22) - Misc Pad Ctrl 3
4141 #define ARIZONA_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */
4142 #define ARIZONA_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */
4143 #define ARIZONA_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */
4144 #define ARIZONA_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */
4145 #define ARIZONA_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */
4146 #define ARIZONA_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */
4147 #define ARIZONA_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */
4148 #define ARIZONA_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
4149 #define ARIZONA_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */
4150 #define ARIZONA_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */
4151 #define ARIZONA_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */
4152 #define ARIZONA_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
4153 #define ARIZONA_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */
4154 #define ARIZONA_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */
4155 #define ARIZONA_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */
4156 #define ARIZONA_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
4159 * R3107 (0xC23) - Misc Pad Ctrl 4
4161 #define ARIZONA_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */
4162 #define ARIZONA_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */
4163 #define ARIZONA_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */
4164 #define ARIZONA_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */
4165 #define ARIZONA_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */
4166 #define ARIZONA_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */
4167 #define ARIZONA_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */
4168 #define ARIZONA_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */
4169 #define ARIZONA_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */
4170 #define ARIZONA_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */
4171 #define ARIZONA_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */
4172 #define ARIZONA_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */
4173 #define ARIZONA_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */
4174 #define ARIZONA_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */
4175 #define ARIZONA_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */
4176 #define ARIZONA_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */
4177 #define ARIZONA_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */
4178 #define ARIZONA_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */
4179 #define ARIZONA_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */
4180 #define ARIZONA_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */
4181 #define ARIZONA_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */
4182 #define ARIZONA_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */
4183 #define ARIZONA_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */
4184 #define ARIZONA_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */
4187 * R3108 (0xC24) - Misc Pad Ctrl 5
4189 #define ARIZONA_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */
4190 #define ARIZONA_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */
4191 #define ARIZONA_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */
4192 #define ARIZONA_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */
4193 #define ARIZONA_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */
4194 #define ARIZONA_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */
4195 #define ARIZONA_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */
4196 #define ARIZONA_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */
4197 #define ARIZONA_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */
4198 #define ARIZONA_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */
4199 #define ARIZONA_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */
4200 #define ARIZONA_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */
4201 #define ARIZONA_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */
4202 #define ARIZONA_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */
4203 #define ARIZONA_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */
4204 #define ARIZONA_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */
4205 #define ARIZONA_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */
4206 #define ARIZONA_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */
4207 #define ARIZONA_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */
4208 #define ARIZONA_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */
4209 #define ARIZONA_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */
4210 #define ARIZONA_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */
4211 #define ARIZONA_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */
4212 #define ARIZONA_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */
4215 * R3109 (0xC25) - Misc Pad Ctrl 6
4217 #define ARIZONA_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */
4218 #define ARIZONA_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */
4219 #define ARIZONA_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */
4220 #define ARIZONA_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */
4221 #define ARIZONA_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */
4222 #define ARIZONA_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */
4223 #define ARIZONA_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */
4224 #define ARIZONA_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */
4225 #define ARIZONA_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */
4226 #define ARIZONA_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */
4227 #define ARIZONA_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */
4228 #define ARIZONA_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */
4229 #define ARIZONA_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */
4230 #define ARIZONA_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */
4231 #define ARIZONA_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */
4232 #define ARIZONA_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */
4233 #define ARIZONA_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */
4234 #define ARIZONA_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */
4235 #define ARIZONA_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */
4236 #define ARIZONA_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */
4237 #define ARIZONA_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */
4238 #define ARIZONA_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */
4239 #define ARIZONA_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */
4240 #define ARIZONA_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */
4243 * R3328 (0xD00) - Interrupt Status 1
4245 #define ARIZONA_GP4_EINT1 0x0008 /* GP4_EINT1 */
4246 #define ARIZONA_GP4_EINT1_MASK 0x0008 /* GP4_EINT1 */
4247 #define ARIZONA_GP4_EINT1_SHIFT 3 /* GP4_EINT1 */
4248 #define ARIZONA_GP4_EINT1_WIDTH 1 /* GP4_EINT1 */
4249 #define ARIZONA_GP3_EINT1 0x0004 /* GP3_EINT1 */
4250 #define ARIZONA_GP3_EINT1_MASK 0x0004 /* GP3_EINT1 */
4251 #define ARIZONA_GP3_EINT1_SHIFT 2 /* GP3_EINT1 */
4252 #define ARIZONA_GP3_EINT1_WIDTH 1 /* GP3_EINT1 */
4253 #define ARIZONA_GP2_EINT1 0x0002 /* GP2_EINT1 */
4254 #define ARIZONA_GP2_EINT1_MASK 0x0002 /* GP2_EINT1 */
4255 #define ARIZONA_GP2_EINT1_SHIFT 1 /* GP2_EINT1 */
4256 #define ARIZONA_GP2_EINT1_WIDTH 1 /* GP2_EINT1 */
4257 #define ARIZONA_GP1_EINT1 0x0001 /* GP1_EINT1 */
4258 #define ARIZONA_GP1_EINT1_MASK 0x0001 /* GP1_EINT1 */
4259 #define ARIZONA_GP1_EINT1_SHIFT 0 /* GP1_EINT1 */
4260 #define ARIZONA_GP1_EINT1_WIDTH 1 /* GP1_EINT1 */
4263 * R3329 (0xD01) - Interrupt Status 2
4265 #define ARIZONA_DSP4_RAM_RDY_EINT1 0x0800 /* DSP4_RAM_RDY_EINT1 */
4266 #define ARIZONA_DSP4_RAM_RDY_EINT1_MASK 0x0800 /* DSP4_RAM_RDY_EINT1 */
4267 #define ARIZONA_DSP4_RAM_RDY_EINT1_SHIFT 11 /* DSP4_RAM_RDY_EINT1 */
4268 #define ARIZONA_DSP4_RAM_RDY_EINT1_WIDTH 1 /* DSP4_RAM_RDY_EINT1 */
4269 #define ARIZONA_DSP3_RAM_RDY_EINT1 0x0400 /* DSP3_RAM_RDY_EINT1 */
4270 #define ARIZONA_DSP3_RAM_RDY_EINT1_MASK 0x0400 /* DSP3_RAM_RDY_EINT1 */
4271 #define ARIZONA_DSP3_RAM_RDY_EINT1_SHIFT 10 /* DSP3_RAM_RDY_EINT1 */
4272 #define ARIZONA_DSP3_RAM_RDY_EINT1_WIDTH 1 /* DSP3_RAM_RDY_EINT1 */
4273 #define ARIZONA_DSP2_RAM_RDY_EINT1 0x0200 /* DSP2_RAM_RDY_EINT1 */
4274 #define ARIZONA_DSP2_RAM_RDY_EINT1_MASK 0x0200 /* DSP2_RAM_RDY_EINT1 */
4275 #define ARIZONA_DSP2_RAM_RDY_EINT1_SHIFT 9 /* DSP2_RAM_RDY_EINT1 */
4276 #define ARIZONA_DSP2_RAM_RDY_EINT1_WIDTH 1 /* DSP2_RAM_RDY_EINT1 */
4277 #define ARIZONA_DSP1_RAM_RDY_EINT1 0x0100 /* DSP1_RAM_RDY_EINT1 */
4278 #define ARIZONA_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* DSP1_RAM_RDY_EINT1 */
4279 #define ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT 8 /* DSP1_RAM_RDY_EINT1 */
4280 #define ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH 1 /* DSP1_RAM_RDY_EINT1 */
4281 #define ARIZONA_DSP_IRQ8_EINT1 0x0080 /* DSP_IRQ8_EINT1 */
4282 #define ARIZONA_DSP_IRQ8_EINT1_MASK 0x0080 /* DSP_IRQ8_EINT1 */
4283 #define ARIZONA_DSP_IRQ8_EINT1_SHIFT 7 /* DSP_IRQ8_EINT1 */
4284 #define ARIZONA_DSP_IRQ8_EINT1_WIDTH 1 /* DSP_IRQ8_EINT1 */
4285 #define ARIZONA_DSP_IRQ7_EINT1 0x0040 /* DSP_IRQ7_EINT1 */
4286 #define ARIZONA_DSP_IRQ7_EINT1_MASK 0x0040 /* DSP_IRQ7_EINT1 */
4287 #define ARIZONA_DSP_IRQ7_EINT1_SHIFT 6 /* DSP_IRQ7_EINT1 */
4288 #define ARIZONA_DSP_IRQ7_EINT1_WIDTH 1 /* DSP_IRQ7_EINT1 */
4289 #define ARIZONA_DSP_IRQ6_EINT1 0x0020 /* DSP_IRQ6_EINT1 */
4290 #define ARIZONA_DSP_IRQ6_EINT1_MASK 0x0020 /* DSP_IRQ6_EINT1 */
4291 #define ARIZONA_DSP_IRQ6_EINT1_SHIFT 5 /* DSP_IRQ6_EINT1 */
4292 #define ARIZONA_DSP_IRQ6_EINT1_WIDTH 1 /* DSP_IRQ6_EINT1 */
4293 #define ARIZONA_DSP_IRQ5_EINT1 0x0010 /* DSP_IRQ5_EINT1 */
4294 #define ARIZONA_DSP_IRQ5_EINT1_MASK 0x0010 /* DSP_IRQ5_EINT1 */
4295 #define ARIZONA_DSP_IRQ5_EINT1_SHIFT 4 /* DSP_IRQ5_EINT1 */
4296 #define ARIZONA_DSP_IRQ5_EINT1_WIDTH 1 /* DSP_IRQ5_EINT1 */
4297 #define ARIZONA_DSP_IRQ4_EINT1 0x0008 /* DSP_IRQ4_EINT1 */
4298 #define ARIZONA_DSP_IRQ4_EINT1_MASK 0x0008 /* DSP_IRQ4_EINT1 */
4299 #define ARIZONA_DSP_IRQ4_EINT1_SHIFT 3 /* DSP_IRQ4_EINT1 */
4300 #define ARIZONA_DSP_IRQ4_EINT1_WIDTH 1 /* DSP_IRQ4_EINT1 */
4301 #define ARIZONA_DSP_IRQ3_EINT1 0x0004 /* DSP_IRQ3_EINT1 */
4302 #define ARIZONA_DSP_IRQ3_EINT1_MASK 0x0004 /* DSP_IRQ3_EINT1 */
4303 #define ARIZONA_DSP_IRQ3_EINT1_SHIFT 2 /* DSP_IRQ3_EINT1 */
4304 #define ARIZONA_DSP_IRQ3_EINT1_WIDTH 1 /* DSP_IRQ3_EINT1 */
4305 #define ARIZONA_DSP_IRQ2_EINT1 0x0002 /* DSP_IRQ2_EINT1 */
4306 #define ARIZONA_DSP_IRQ2_EINT1_MASK 0x0002 /* DSP_IRQ2_EINT1 */
4307 #define ARIZONA_DSP_IRQ2_EINT1_SHIFT 1 /* DSP_IRQ2_EINT1 */
4308 #define ARIZONA_DSP_IRQ2_EINT1_WIDTH 1 /* DSP_IRQ2_EINT1 */
4309 #define ARIZONA_DSP_IRQ1_EINT1 0x0001 /* DSP_IRQ1_EINT1 */
4310 #define ARIZONA_DSP_IRQ1_EINT1_MASK 0x0001 /* DSP_IRQ1_EINT1 */
4311 #define ARIZONA_DSP_IRQ1_EINT1_SHIFT 0 /* DSP_IRQ1_EINT1 */
4312 #define ARIZONA_DSP_IRQ1_EINT1_WIDTH 1 /* DSP_IRQ1_EINT1 */
4315 * R3330 (0xD02) - Interrupt Status 3
4317 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
4318 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
4319 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT1 */
4320 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT1 */
4321 #define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */
4322 #define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */
4323 #define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */
4324 #define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */
4325 #define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */
4326 #define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */
4327 #define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */
4328 #define ARIZONA_HPDET_EINT1_WIDTH 1 /* HPDET_EINT1 */
4329 #define ARIZONA_MICDET_EINT1 0x1000 /* MICDET_EINT1 */
4330 #define ARIZONA_MICDET_EINT1_MASK 0x1000 /* MICDET_EINT1 */
4331 #define ARIZONA_MICDET_EINT1_SHIFT 12 /* MICDET_EINT1 */
4332 #define ARIZONA_MICDET_EINT1_WIDTH 1 /* MICDET_EINT1 */
4333 #define ARIZONA_WSEQ_DONE_EINT1 0x0800 /* WSEQ_DONE_EINT1 */
4334 #define ARIZONA_WSEQ_DONE_EINT1_MASK 0x0800 /* WSEQ_DONE_EINT1 */
4335 #define ARIZONA_WSEQ_DONE_EINT1_SHIFT 11 /* WSEQ_DONE_EINT1 */
4336 #define ARIZONA_WSEQ_DONE_EINT1_WIDTH 1 /* WSEQ_DONE_EINT1 */
4337 #define ARIZONA_DRC2_SIG_DET_EINT1 0x0400 /* DRC2_SIG_DET_EINT1 */
4338 #define ARIZONA_DRC2_SIG_DET_EINT1_MASK 0x0400 /* DRC2_SIG_DET_EINT1 */
4339 #define ARIZONA_DRC2_SIG_DET_EINT1_SHIFT 10 /* DRC2_SIG_DET_EINT1 */
4340 #define ARIZONA_DRC2_SIG_DET_EINT1_WIDTH 1 /* DRC2_SIG_DET_EINT1 */
4341 #define ARIZONA_DRC1_SIG_DET_EINT1 0x0200 /* DRC1_SIG_DET_EINT1 */
4342 #define ARIZONA_DRC1_SIG_DET_EINT1_MASK 0x0200 /* DRC1_SIG_DET_EINT1 */
4343 #define ARIZONA_DRC1_SIG_DET_EINT1_SHIFT 9 /* DRC1_SIG_DET_EINT1 */
4344 #define ARIZONA_DRC1_SIG_DET_EINT1_WIDTH 1 /* DRC1_SIG_DET_EINT1 */
4345 #define ARIZONA_ASRC2_LOCK_EINT1 0x0100 /* ASRC2_LOCK_EINT1 */
4346 #define ARIZONA_ASRC2_LOCK_EINT1_MASK 0x0100 /* ASRC2_LOCK_EINT1 */
4347 #define ARIZONA_ASRC2_LOCK_EINT1_SHIFT 8 /* ASRC2_LOCK_EINT1 */
4348 #define ARIZONA_ASRC2_LOCK_EINT1_WIDTH 1 /* ASRC2_LOCK_EINT1 */
4349 #define ARIZONA_ASRC1_LOCK_EINT1 0x0080 /* ASRC1_LOCK_EINT1 */
4350 #define ARIZONA_ASRC1_LOCK_EINT1_MASK 0x0080 /* ASRC1_LOCK_EINT1 */
4351 #define ARIZONA_ASRC1_LOCK_EINT1_SHIFT 7 /* ASRC1_LOCK_EINT1 */
4352 #define ARIZONA_ASRC1_LOCK_EINT1_WIDTH 1 /* ASRC1_LOCK_EINT1 */
4353 #define ARIZONA_UNDERCLOCKED_EINT1 0x0040 /* UNDERCLOCKED_EINT1 */
4354 #define ARIZONA_UNDERCLOCKED_EINT1_MASK 0x0040 /* UNDERCLOCKED_EINT1 */
4355 #define ARIZONA_UNDERCLOCKED_EINT1_SHIFT 6 /* UNDERCLOCKED_EINT1 */
4356 #define ARIZONA_UNDERCLOCKED_EINT1_WIDTH 1 /* UNDERCLOCKED_EINT1 */
4357 #define ARIZONA_OVERCLOCKED_EINT1 0x0020 /* OVERCLOCKED_EINT1 */
4358 #define ARIZONA_OVERCLOCKED_EINT1_MASK 0x0020 /* OVERCLOCKED_EINT1 */
4359 #define ARIZONA_OVERCLOCKED_EINT1_SHIFT 5 /* OVERCLOCKED_EINT1 */
4360 #define ARIZONA_OVERCLOCKED_EINT1_WIDTH 1 /* OVERCLOCKED_EINT1 */
4361 #define ARIZONA_FLL2_LOCK_EINT1 0x0008 /* FLL2_LOCK_EINT1 */
4362 #define ARIZONA_FLL2_LOCK_EINT1_MASK 0x0008 /* FLL2_LOCK_EINT1 */
4363 #define ARIZONA_FLL2_LOCK_EINT1_SHIFT 3 /* FLL2_LOCK_EINT1 */
4364 #define ARIZONA_FLL2_LOCK_EINT1_WIDTH 1 /* FLL2_LOCK_EINT1 */
4365 #define ARIZONA_FLL1_LOCK_EINT1 0x0004 /* FLL1_LOCK_EINT1 */
4366 #define ARIZONA_FLL1_LOCK_EINT1_MASK 0x0004 /* FLL1_LOCK_EINT1 */
4367 #define ARIZONA_FLL1_LOCK_EINT1_SHIFT 2 /* FLL1_LOCK_EINT1 */
4368 #define ARIZONA_FLL1_LOCK_EINT1_WIDTH 1 /* FLL1_LOCK_EINT1 */
4369 #define ARIZONA_CLKGEN_ERR_EINT1 0x0002 /* CLKGEN_ERR_EINT1 */
4370 #define ARIZONA_CLKGEN_ERR_EINT1_MASK 0x0002 /* CLKGEN_ERR_EINT1 */
4371 #define ARIZONA_CLKGEN_ERR_EINT1_SHIFT 1 /* CLKGEN_ERR_EINT1 */
4372 #define ARIZONA_CLKGEN_ERR_EINT1_WIDTH 1 /* CLKGEN_ERR_EINT1 */
4373 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
4374 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
4375 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT1 */
4376 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT1 */
4379 * R3331 (0xD03) - Interrupt Status 4
4381 #define ARIZONA_ASRC_CFG_ERR_EINT1 0x8000 /* ASRC_CFG_ERR_EINT1 */
4382 #define ARIZONA_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* ASRC_CFG_ERR_EINT1 */
4383 #define ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT 15 /* ASRC_CFG_ERR_EINT1 */
4384 #define ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */
4385 #define ARIZONA_AIF3_ERR_EINT1 0x4000 /* AIF3_ERR_EINT1 */
4386 #define ARIZONA_AIF3_ERR_EINT1_MASK 0x4000 /* AIF3_ERR_EINT1 */
4387 #define ARIZONA_AIF3_ERR_EINT1_SHIFT 14 /* AIF3_ERR_EINT1 */
4388 #define ARIZONA_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */
4389 #define ARIZONA_AIF2_ERR_EINT1 0x2000 /* AIF2_ERR_EINT1 */
4390 #define ARIZONA_AIF2_ERR_EINT1_MASK 0x2000 /* AIF2_ERR_EINT1 */
4391 #define ARIZONA_AIF2_ERR_EINT1_SHIFT 13 /* AIF2_ERR_EINT1 */
4392 #define ARIZONA_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */
4393 #define ARIZONA_AIF1_ERR_EINT1 0x1000 /* AIF1_ERR_EINT1 */
4394 #define ARIZONA_AIF1_ERR_EINT1_MASK 0x1000 /* AIF1_ERR_EINT1 */
4395 #define ARIZONA_AIF1_ERR_EINT1_SHIFT 12 /* AIF1_ERR_EINT1 */
4396 #define ARIZONA_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */
4397 #define ARIZONA_CTRLIF_ERR_EINT1 0x0800 /* CTRLIF_ERR_EINT1 */
4398 #define ARIZONA_CTRLIF_ERR_EINT1_MASK 0x0800 /* CTRLIF_ERR_EINT1 */
4399 #define ARIZONA_CTRLIF_ERR_EINT1_SHIFT 11 /* CTRLIF_ERR_EINT1 */
4400 #define ARIZONA_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */
4401 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
4402 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
4403 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT1 */
4404 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */
4405 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
4406 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
4407 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT1 */
4408 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */
4409 #define ARIZONA_SYSCLK_ENA_LOW_EINT1 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
4410 #define ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
4411 #define ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* SYSCLK_ENA_LOW_EINT1 */
4412 #define ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */
4413 #define ARIZONA_ISRC1_CFG_ERR_EINT1 0x0080 /* ISRC1_CFG_ERR_EINT1 */
4414 #define ARIZONA_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* ISRC1_CFG_ERR_EINT1 */
4415 #define ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* ISRC1_CFG_ERR_EINT1 */
4416 #define ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */
4417 #define ARIZONA_ISRC2_CFG_ERR_EINT1 0x0040 /* ISRC2_CFG_ERR_EINT1 */
4418 #define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */
4419 #define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */
4420 #define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */
4423 * R3332 (0xD04) - Interrupt Status 5
4425 #define ARIZONA_BOOT_DONE_EINT1 0x0100 /* BOOT_DONE_EINT1 */
4426 #define ARIZONA_BOOT_DONE_EINT1_MASK 0x0100 /* BOOT_DONE_EINT1 */
4427 #define ARIZONA_BOOT_DONE_EINT1_SHIFT 8 /* BOOT_DONE_EINT1 */
4428 #define ARIZONA_BOOT_DONE_EINT1_WIDTH 1 /* BOOT_DONE_EINT1 */
4429 #define ARIZONA_DCS_DAC_DONE_EINT1 0x0080 /* DCS_DAC_DONE_EINT1 */
4430 #define ARIZONA_DCS_DAC_DONE_EINT1_MASK 0x0080 /* DCS_DAC_DONE_EINT1 */
4431 #define ARIZONA_DCS_DAC_DONE_EINT1_SHIFT 7 /* DCS_DAC_DONE_EINT1 */
4432 #define ARIZONA_DCS_DAC_DONE_EINT1_WIDTH 1 /* DCS_DAC_DONE_EINT1 */
4433 #define ARIZONA_DCS_HP_DONE_EINT1 0x0040 /* DCS_HP_DONE_EINT1 */
4434 #define ARIZONA_DCS_HP_DONE_EINT1_MASK 0x0040 /* DCS_HP_DONE_EINT1 */
4435 #define ARIZONA_DCS_HP_DONE_EINT1_SHIFT 6 /* DCS_HP_DONE_EINT1 */
4436 #define ARIZONA_DCS_HP_DONE_EINT1_WIDTH 1 /* DCS_HP_DONE_EINT1 */
4437 #define ARIZONA_FLL2_CLOCK_OK_EINT1 0x0002 /* FLL2_CLOCK_OK_EINT1 */
4438 #define ARIZONA_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* FLL2_CLOCK_OK_EINT1 */
4439 #define ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* FLL2_CLOCK_OK_EINT1 */
4440 #define ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* FLL2_CLOCK_OK_EINT1 */
4441 #define ARIZONA_FLL1_CLOCK_OK_EINT1 0x0001 /* FLL1_CLOCK_OK_EINT1 */
4442 #define ARIZONA_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* FLL1_CLOCK_OK_EINT1 */
4443 #define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */
4444 #define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */
4447 * R3336 (0xD08) - Interrupt Status 1 Mask
4449 #define ARIZONA_IM_GP4_EINT1 0x0008 /* IM_GP4_EINT1 */
4450 #define ARIZONA_IM_GP4_EINT1_MASK 0x0008 /* IM_GP4_EINT1 */
4451 #define ARIZONA_IM_GP4_EINT1_SHIFT 3 /* IM_GP4_EINT1 */
4452 #define ARIZONA_IM_GP4_EINT1_WIDTH 1 /* IM_GP4_EINT1 */
4453 #define ARIZONA_IM_GP3_EINT1 0x0004 /* IM_GP3_EINT1 */
4454 #define ARIZONA_IM_GP3_EINT1_MASK 0x0004 /* IM_GP3_EINT1 */
4455 #define ARIZONA_IM_GP3_EINT1_SHIFT 2 /* IM_GP3_EINT1 */
4456 #define ARIZONA_IM_GP3_EINT1_WIDTH 1 /* IM_GP3_EINT1 */
4457 #define ARIZONA_IM_GP2_EINT1 0x0002 /* IM_GP2_EINT1 */
4458 #define ARIZONA_IM_GP2_EINT1_MASK 0x0002 /* IM_GP2_EINT1 */
4459 #define ARIZONA_IM_GP2_EINT1_SHIFT 1 /* IM_GP2_EINT1 */
4460 #define ARIZONA_IM_GP2_EINT1_WIDTH 1 /* IM_GP2_EINT1 */
4461 #define ARIZONA_IM_GP1_EINT1 0x0001 /* IM_GP1_EINT1 */
4462 #define ARIZONA_IM_GP1_EINT1_MASK 0x0001 /* IM_GP1_EINT1 */
4463 #define ARIZONA_IM_GP1_EINT1_SHIFT 0 /* IM_GP1_EINT1 */
4464 #define ARIZONA_IM_GP1_EINT1_WIDTH 1 /* IM_GP1_EINT1 */
4467 * R3337 (0xD09) - Interrupt Status 2 Mask
4469 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
4470 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
4471 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT1 */
4472 #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT1 */
4473 #define ARIZONA_IM_DSP_IRQ2_EINT1 0x0002 /* IM_DSP_IRQ2_EINT1 */
4474 #define ARIZONA_IM_DSP_IRQ2_EINT1_MASK 0x0002 /* IM_DSP_IRQ2_EINT1 */
4475 #define ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT 1 /* IM_DSP_IRQ2_EINT1 */
4476 #define ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH 1 /* IM_DSP_IRQ2_EINT1 */
4477 #define ARIZONA_IM_DSP_IRQ1_EINT1 0x0001 /* IM_DSP_IRQ1_EINT1 */
4478 #define ARIZONA_IM_DSP_IRQ1_EINT1_MASK 0x0001 /* IM_DSP_IRQ1_EINT1 */
4479 #define ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT 0 /* IM_DSP_IRQ1_EINT1 */
4480 #define ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH 1 /* IM_DSP_IRQ1_EINT1 */
4483 * R3338 (0xD0A) - Interrupt Status 3 Mask
4485 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4486 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4487 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4488 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
4489 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
4490 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
4491 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */
4492 #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */
4493 #define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */
4494 #define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */
4495 #define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */
4496 #define ARIZONA_IM_HPDET_EINT1_WIDTH 1 /* IM_HPDET_EINT1 */
4497 #define ARIZONA_IM_MICDET_EINT1 0x1000 /* IM_MICDET_EINT1 */
4498 #define ARIZONA_IM_MICDET_EINT1_MASK 0x1000 /* IM_MICDET_EINT1 */
4499 #define ARIZONA_IM_MICDET_EINT1_SHIFT 12 /* IM_MICDET_EINT1 */
4500 #define ARIZONA_IM_MICDET_EINT1_WIDTH 1 /* IM_MICDET_EINT1 */
4501 #define ARIZONA_IM_WSEQ_DONE_EINT1 0x0800 /* IM_WSEQ_DONE_EINT1 */
4502 #define ARIZONA_IM_WSEQ_DONE_EINT1_MASK 0x0800 /* IM_WSEQ_DONE_EINT1 */
4503 #define ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT 11 /* IM_WSEQ_DONE_EINT1 */
4504 #define ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH 1 /* IM_WSEQ_DONE_EINT1 */
4505 #define ARIZONA_IM_DRC2_SIG_DET_EINT1 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
4506 #define ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
4507 #define ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT 10 /* IM_DRC2_SIG_DET_EINT1 */
4508 #define ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH 1 /* IM_DRC2_SIG_DET_EINT1 */
4509 #define ARIZONA_IM_DRC1_SIG_DET_EINT1 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
4510 #define ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
4511 #define ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT 9 /* IM_DRC1_SIG_DET_EINT1 */
4512 #define ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH 1 /* IM_DRC1_SIG_DET_EINT1 */
4513 #define ARIZONA_IM_ASRC2_LOCK_EINT1 0x0100 /* IM_ASRC2_LOCK_EINT1 */
4514 #define ARIZONA_IM_ASRC2_LOCK_EINT1_MASK 0x0100 /* IM_ASRC2_LOCK_EINT1 */
4515 #define ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT 8 /* IM_ASRC2_LOCK_EINT1 */
4516 #define ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_LOCK_EINT1 */
4517 #define ARIZONA_IM_ASRC1_LOCK_EINT1 0x0080 /* IM_ASRC1_LOCK_EINT1 */
4518 #define ARIZONA_IM_ASRC1_LOCK_EINT1_MASK 0x0080 /* IM_ASRC1_LOCK_EINT1 */
4519 #define ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT 7 /* IM_ASRC1_LOCK_EINT1 */
4520 #define ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_LOCK_EINT1 */
4521 #define ARIZONA_IM_UNDERCLOCKED_EINT1 0x0040 /* IM_UNDERCLOCKED_EINT1 */
4522 #define ARIZONA_IM_UNDERCLOCKED_EINT1_MASK 0x0040 /* IM_UNDERCLOCKED_EINT1 */
4523 #define ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT 6 /* IM_UNDERCLOCKED_EINT1 */
4524 #define ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH 1 /* IM_UNDERCLOCKED_EINT1 */
4525 #define ARIZONA_IM_OVERCLOCKED_EINT1 0x0020 /* IM_OVERCLOCKED_EINT1 */
4526 #define ARIZONA_IM_OVERCLOCKED_EINT1_MASK 0x0020 /* IM_OVERCLOCKED_EINT1 */
4527 #define ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT 5 /* IM_OVERCLOCKED_EINT1 */
4528 #define ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH 1 /* IM_OVERCLOCKED_EINT1 */
4529 #define ARIZONA_IM_FLL2_LOCK_EINT1 0x0008 /* IM_FLL2_LOCK_EINT1 */
4530 #define ARIZONA_IM_FLL2_LOCK_EINT1_MASK 0x0008 /* IM_FLL2_LOCK_EINT1 */
4531 #define ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT 3 /* IM_FLL2_LOCK_EINT1 */
4532 #define ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH 1 /* IM_FLL2_LOCK_EINT1 */
4533 #define ARIZONA_IM_FLL1_LOCK_EINT1 0x0004 /* IM_FLL1_LOCK_EINT1 */
4534 #define ARIZONA_IM_FLL1_LOCK_EINT1_MASK 0x0004 /* IM_FLL1_LOCK_EINT1 */
4535 #define ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT 2 /* IM_FLL1_LOCK_EINT1 */
4536 #define ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH 1 /* IM_FLL1_LOCK_EINT1 */
4537 #define ARIZONA_IM_CLKGEN_ERR_EINT1 0x0002 /* IM_CLKGEN_ERR_EINT1 */
4538 #define ARIZONA_IM_CLKGEN_ERR_EINT1_MASK 0x0002 /* IM_CLKGEN_ERR_EINT1 */
4539 #define ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT 1 /* IM_CLKGEN_ERR_EINT1 */
4540 #define ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_EINT1 */
4541 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4542 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4543 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4544 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
4547 * R3339 (0xD0B) - Interrupt Status 4 Mask
4549 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
4550 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
4551 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */
4552 #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */
4553 #define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */
4554 #define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */
4555 #define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */
4556 #define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */
4557 #define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */
4558 #define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */
4559 #define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */
4560 #define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */
4561 #define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */
4562 #define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */
4563 #define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */
4564 #define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */
4565 #define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */
4566 #define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */
4567 #define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */
4568 #define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */
4569 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4570 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4571 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4572 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
4573 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4574 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4575 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4576 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
4577 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
4578 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
4579 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */
4580 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */
4581 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
4582 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
4583 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */
4584 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */
4585 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
4586 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
4587 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */
4588 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */
4591 * R3340 (0xD0C) - Interrupt Status 5 Mask
4593 #define ARIZONA_IM_BOOT_DONE_EINT1 0x0100 /* IM_BOOT_DONE_EINT1 */
4594 #define ARIZONA_IM_BOOT_DONE_EINT1_MASK 0x0100 /* IM_BOOT_DONE_EINT1 */
4595 #define ARIZONA_IM_BOOT_DONE_EINT1_SHIFT 8 /* IM_BOOT_DONE_EINT1 */
4596 #define ARIZONA_IM_BOOT_DONE_EINT1_WIDTH 1 /* IM_BOOT_DONE_EINT1 */
4597 #define ARIZONA_IM_DCS_DAC_DONE_EINT1 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
4598 #define ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
4599 #define ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT 7 /* IM_DCS_DAC_DONE_EINT1 */
4600 #define ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH 1 /* IM_DCS_DAC_DONE_EINT1 */
4601 #define ARIZONA_IM_DCS_HP_DONE_EINT1 0x0040 /* IM_DCS_HP_DONE_EINT1 */
4602 #define ARIZONA_IM_DCS_HP_DONE_EINT1_MASK 0x0040 /* IM_DCS_HP_DONE_EINT1 */
4603 #define ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT 6 /* IM_DCS_HP_DONE_EINT1 */
4604 #define ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH 1 /* IM_DCS_HP_DONE_EINT1 */
4605 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
4606 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
4607 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT1 */
4608 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT1 */
4609 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
4610 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
4611 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */
4612 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */
4615 * R3343 (0xD0F) - Interrupt Control
4617 #define ARIZONA_IM_IRQ1 0x0001 /* IM_IRQ1 */
4618 #define ARIZONA_IM_IRQ1_MASK 0x0001 /* IM_IRQ1 */
4619 #define ARIZONA_IM_IRQ1_SHIFT 0 /* IM_IRQ1 */
4620 #define ARIZONA_IM_IRQ1_WIDTH 1 /* IM_IRQ1 */
4623 * R3344 (0xD10) - IRQ2 Status 1
4625 #define ARIZONA_GP4_EINT2 0x0008 /* GP4_EINT2 */
4626 #define ARIZONA_GP4_EINT2_MASK 0x0008 /* GP4_EINT2 */
4627 #define ARIZONA_GP4_EINT2_SHIFT 3 /* GP4_EINT2 */
4628 #define ARIZONA_GP4_EINT2_WIDTH 1 /* GP4_EINT2 */
4629 #define ARIZONA_GP3_EINT2 0x0004 /* GP3_EINT2 */
4630 #define ARIZONA_GP3_EINT2_MASK 0x0004 /* GP3_EINT2 */
4631 #define ARIZONA_GP3_EINT2_SHIFT 2 /* GP3_EINT2 */
4632 #define ARIZONA_GP3_EINT2_WIDTH 1 /* GP3_EINT2 */
4633 #define ARIZONA_GP2_EINT2 0x0002 /* GP2_EINT2 */
4634 #define ARIZONA_GP2_EINT2_MASK 0x0002 /* GP2_EINT2 */
4635 #define ARIZONA_GP2_EINT2_SHIFT 1 /* GP2_EINT2 */
4636 #define ARIZONA_GP2_EINT2_WIDTH 1 /* GP2_EINT2 */
4637 #define ARIZONA_GP1_EINT2 0x0001 /* GP1_EINT2 */
4638 #define ARIZONA_GP1_EINT2_MASK 0x0001 /* GP1_EINT2 */
4639 #define ARIZONA_GP1_EINT2_SHIFT 0 /* GP1_EINT2 */
4640 #define ARIZONA_GP1_EINT2_WIDTH 1 /* GP1_EINT2 */
4643 * R3345 (0xD11) - IRQ2 Status 2
4645 #define ARIZONA_DSP1_RAM_RDY_EINT2 0x0100 /* DSP1_RAM_RDY_EINT2 */
4646 #define ARIZONA_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* DSP1_RAM_RDY_EINT2 */
4647 #define ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT 8 /* DSP1_RAM_RDY_EINT2 */
4648 #define ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH 1 /* DSP1_RAM_RDY_EINT2 */
4649 #define ARIZONA_DSP_IRQ2_EINT2 0x0002 /* DSP_IRQ2_EINT2 */
4650 #define ARIZONA_DSP_IRQ2_EINT2_MASK 0x0002 /* DSP_IRQ2_EINT2 */
4651 #define ARIZONA_DSP_IRQ2_EINT2_SHIFT 1 /* DSP_IRQ2_EINT2 */
4652 #define ARIZONA_DSP_IRQ2_EINT2_WIDTH 1 /* DSP_IRQ2_EINT2 */
4653 #define ARIZONA_DSP_IRQ1_EINT2 0x0001 /* DSP_IRQ1_EINT2 */
4654 #define ARIZONA_DSP_IRQ1_EINT2_MASK 0x0001 /* DSP_IRQ1_EINT2 */
4655 #define ARIZONA_DSP_IRQ1_EINT2_SHIFT 0 /* DSP_IRQ1_EINT2 */
4656 #define ARIZONA_DSP_IRQ1_EINT2_WIDTH 1 /* DSP_IRQ1_EINT2 */
4659 * R3346 (0xD12) - IRQ2 Status 3
4661 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
4662 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
4663 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT2 */
4664 #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT2 */
4665 #define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */
4666 #define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */
4667 #define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */
4668 #define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */
4669 #define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */
4670 #define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */
4671 #define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */
4672 #define ARIZONA_HPDET_EINT2_WIDTH 1 /* HPDET_EINT2 */
4673 #define ARIZONA_MICDET_EINT2 0x1000 /* MICDET_EINT2 */
4674 #define ARIZONA_MICDET_EINT2_MASK 0x1000 /* MICDET_EINT2 */
4675 #define ARIZONA_MICDET_EINT2_SHIFT 12 /* MICDET_EINT2 */
4676 #define ARIZONA_MICDET_EINT2_WIDTH 1 /* MICDET_EINT2 */
4677 #define ARIZONA_WSEQ_DONE_EINT2 0x0800 /* WSEQ_DONE_EINT2 */
4678 #define ARIZONA_WSEQ_DONE_EINT2_MASK 0x0800 /* WSEQ_DONE_EINT2 */
4679 #define ARIZONA_WSEQ_DONE_EINT2_SHIFT 11 /* WSEQ_DONE_EINT2 */
4680 #define ARIZONA_WSEQ_DONE_EINT2_WIDTH 1 /* WSEQ_DONE_EINT2 */
4681 #define ARIZONA_DRC2_SIG_DET_EINT2 0x0400 /* DRC2_SIG_DET_EINT2 */
4682 #define ARIZONA_DRC2_SIG_DET_EINT2_MASK 0x0400 /* DRC2_SIG_DET_EINT2 */
4683 #define ARIZONA_DRC2_SIG_DET_EINT2_SHIFT 10 /* DRC2_SIG_DET_EINT2 */
4684 #define ARIZONA_DRC2_SIG_DET_EINT2_WIDTH 1 /* DRC2_SIG_DET_EINT2 */
4685 #define ARIZONA_DRC1_SIG_DET_EINT2 0x0200 /* DRC1_SIG_DET_EINT2 */
4686 #define ARIZONA_DRC1_SIG_DET_EINT2_MASK 0x0200 /* DRC1_SIG_DET_EINT2 */
4687 #define ARIZONA_DRC1_SIG_DET_EINT2_SHIFT 9 /* DRC1_SIG_DET_EINT2 */
4688 #define ARIZONA_DRC1_SIG_DET_EINT2_WIDTH 1 /* DRC1_SIG_DET_EINT2 */
4689 #define ARIZONA_ASRC2_LOCK_EINT2 0x0100 /* ASRC2_LOCK_EINT2 */
4690 #define ARIZONA_ASRC2_LOCK_EINT2_MASK 0x0100 /* ASRC2_LOCK_EINT2 */
4691 #define ARIZONA_ASRC2_LOCK_EINT2_SHIFT 8 /* ASRC2_LOCK_EINT2 */
4692 #define ARIZONA_ASRC2_LOCK_EINT2_WIDTH 1 /* ASRC2_LOCK_EINT2 */
4693 #define ARIZONA_ASRC1_LOCK_EINT2 0x0080 /* ASRC1_LOCK_EINT2 */
4694 #define ARIZONA_ASRC1_LOCK_EINT2_MASK 0x0080 /* ASRC1_LOCK_EINT2 */
4695 #define ARIZONA_ASRC1_LOCK_EINT2_SHIFT 7 /* ASRC1_LOCK_EINT2 */
4696 #define ARIZONA_ASRC1_LOCK_EINT2_WIDTH 1 /* ASRC1_LOCK_EINT2 */
4697 #define ARIZONA_UNDERCLOCKED_EINT2 0x0040 /* UNDERCLOCKED_EINT2 */
4698 #define ARIZONA_UNDERCLOCKED_EINT2_MASK 0x0040 /* UNDERCLOCKED_EINT2 */
4699 #define ARIZONA_UNDERCLOCKED_EINT2_SHIFT 6 /* UNDERCLOCKED_EINT2 */
4700 #define ARIZONA_UNDERCLOCKED_EINT2_WIDTH 1 /* UNDERCLOCKED_EINT2 */
4701 #define ARIZONA_OVERCLOCKED_EINT2 0x0020 /* OVERCLOCKED_EINT2 */
4702 #define ARIZONA_OVERCLOCKED_EINT2_MASK 0x0020 /* OVERCLOCKED_EINT2 */
4703 #define ARIZONA_OVERCLOCKED_EINT2_SHIFT 5 /* OVERCLOCKED_EINT2 */
4704 #define ARIZONA_OVERCLOCKED_EINT2_WIDTH 1 /* OVERCLOCKED_EINT2 */
4705 #define ARIZONA_FLL2_LOCK_EINT2 0x0008 /* FLL2_LOCK_EINT2 */
4706 #define ARIZONA_FLL2_LOCK_EINT2_MASK 0x0008 /* FLL2_LOCK_EINT2 */
4707 #define ARIZONA_FLL2_LOCK_EINT2_SHIFT 3 /* FLL2_LOCK_EINT2 */
4708 #define ARIZONA_FLL2_LOCK_EINT2_WIDTH 1 /* FLL2_LOCK_EINT2 */
4709 #define ARIZONA_FLL1_LOCK_EINT2 0x0004 /* FLL1_LOCK_EINT2 */
4710 #define ARIZONA_FLL1_LOCK_EINT2_MASK 0x0004 /* FLL1_LOCK_EINT2 */
4711 #define ARIZONA_FLL1_LOCK_EINT2_SHIFT 2 /* FLL1_LOCK_EINT2 */
4712 #define ARIZONA_FLL1_LOCK_EINT2_WIDTH 1 /* FLL1_LOCK_EINT2 */
4713 #define ARIZONA_CLKGEN_ERR_EINT2 0x0002 /* CLKGEN_ERR_EINT2 */
4714 #define ARIZONA_CLKGEN_ERR_EINT2_MASK 0x0002 /* CLKGEN_ERR_EINT2 */
4715 #define ARIZONA_CLKGEN_ERR_EINT2_SHIFT 1 /* CLKGEN_ERR_EINT2 */
4716 #define ARIZONA_CLKGEN_ERR_EINT2_WIDTH 1 /* CLKGEN_ERR_EINT2 */
4717 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
4718 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
4719 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT2 */
4720 #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT2 */
4723 * R3347 (0xD13) - IRQ2 Status 4
4725 #define ARIZONA_ASRC_CFG_ERR_EINT2 0x8000 /* ASRC_CFG_ERR_EINT2 */
4726 #define ARIZONA_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* ASRC_CFG_ERR_EINT2 */
4727 #define ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT 15 /* ASRC_CFG_ERR_EINT2 */
4728 #define ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */
4729 #define ARIZONA_AIF3_ERR_EINT2 0x4000 /* AIF3_ERR_EINT2 */
4730 #define ARIZONA_AIF3_ERR_EINT2_MASK 0x4000 /* AIF3_ERR_EINT2 */
4731 #define ARIZONA_AIF3_ERR_EINT2_SHIFT 14 /* AIF3_ERR_EINT2 */
4732 #define ARIZONA_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */
4733 #define ARIZONA_AIF2_ERR_EINT2 0x2000 /* AIF2_ERR_EINT2 */
4734 #define ARIZONA_AIF2_ERR_EINT2_MASK 0x2000 /* AIF2_ERR_EINT2 */
4735 #define ARIZONA_AIF2_ERR_EINT2_SHIFT 13 /* AIF2_ERR_EINT2 */
4736 #define ARIZONA_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */
4737 #define ARIZONA_AIF1_ERR_EINT2 0x1000 /* AIF1_ERR_EINT2 */
4738 #define ARIZONA_AIF1_ERR_EINT2_MASK 0x1000 /* AIF1_ERR_EINT2 */
4739 #define ARIZONA_AIF1_ERR_EINT2_SHIFT 12 /* AIF1_ERR_EINT2 */
4740 #define ARIZONA_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */
4741 #define ARIZONA_CTRLIF_ERR_EINT2 0x0800 /* CTRLIF_ERR_EINT2 */
4742 #define ARIZONA_CTRLIF_ERR_EINT2_MASK 0x0800 /* CTRLIF_ERR_EINT2 */
4743 #define ARIZONA_CTRLIF_ERR_EINT2_SHIFT 11 /* CTRLIF_ERR_EINT2 */
4744 #define ARIZONA_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */
4745 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
4746 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
4747 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT2 */
4748 #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */
4749 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
4750 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
4751 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT2 */
4752 #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */
4753 #define ARIZONA_SYSCLK_ENA_LOW_EINT2 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
4754 #define ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
4755 #define ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* SYSCLK_ENA_LOW_EINT2 */
4756 #define ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */
4757 #define ARIZONA_ISRC1_CFG_ERR_EINT2 0x0080 /* ISRC1_CFG_ERR_EINT2 */
4758 #define ARIZONA_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* ISRC1_CFG_ERR_EINT2 */
4759 #define ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* ISRC1_CFG_ERR_EINT2 */
4760 #define ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */
4761 #define ARIZONA_ISRC2_CFG_ERR_EINT2 0x0040 /* ISRC2_CFG_ERR_EINT2 */
4762 #define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */
4763 #define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */
4764 #define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */
4767 * R3348 (0xD14) - IRQ2 Status 5
4769 #define ARIZONA_BOOT_DONE_EINT2 0x0100 /* BOOT_DONE_EINT2 */
4770 #define ARIZONA_BOOT_DONE_EINT2_MASK 0x0100 /* BOOT_DONE_EINT2 */
4771 #define ARIZONA_BOOT_DONE_EINT2_SHIFT 8 /* BOOT_DONE_EINT2 */
4772 #define ARIZONA_BOOT_DONE_EINT2_WIDTH 1 /* BOOT_DONE_EINT2 */
4773 #define ARIZONA_DCS_DAC_DONE_EINT2 0x0080 /* DCS_DAC_DONE_EINT2 */
4774 #define ARIZONA_DCS_DAC_DONE_EINT2_MASK 0x0080 /* DCS_DAC_DONE_EINT2 */
4775 #define ARIZONA_DCS_DAC_DONE_EINT2_SHIFT 7 /* DCS_DAC_DONE_EINT2 */
4776 #define ARIZONA_DCS_DAC_DONE_EINT2_WIDTH 1 /* DCS_DAC_DONE_EINT2 */
4777 #define ARIZONA_DCS_HP_DONE_EINT2 0x0040 /* DCS_HP_DONE_EINT2 */
4778 #define ARIZONA_DCS_HP_DONE_EINT2_MASK 0x0040 /* DCS_HP_DONE_EINT2 */
4779 #define ARIZONA_DCS_HP_DONE_EINT2_SHIFT 6 /* DCS_HP_DONE_EINT2 */
4780 #define ARIZONA_DCS_HP_DONE_EINT2_WIDTH 1 /* DCS_HP_DONE_EINT2 */
4781 #define ARIZONA_FLL2_CLOCK_OK_EINT2 0x0002 /* FLL2_CLOCK_OK_EINT2 */
4782 #define ARIZONA_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* FLL2_CLOCK_OK_EINT2 */
4783 #define ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* FLL2_CLOCK_OK_EINT2 */
4784 #define ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* FLL2_CLOCK_OK_EINT2 */
4785 #define ARIZONA_FLL1_CLOCK_OK_EINT2 0x0001 /* FLL1_CLOCK_OK_EINT2 */
4786 #define ARIZONA_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* FLL1_CLOCK_OK_EINT2 */
4787 #define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */
4788 #define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */
4791 * R3352 (0xD18) - IRQ2 Status 1 Mask
4793 #define ARIZONA_IM_GP4_EINT2 0x0008 /* IM_GP4_EINT2 */
4794 #define ARIZONA_IM_GP4_EINT2_MASK 0x0008 /* IM_GP4_EINT2 */
4795 #define ARIZONA_IM_GP4_EINT2_SHIFT 3 /* IM_GP4_EINT2 */
4796 #define ARIZONA_IM_GP4_EINT2_WIDTH 1 /* IM_GP4_EINT2 */
4797 #define ARIZONA_IM_GP3_EINT2 0x0004 /* IM_GP3_EINT2 */
4798 #define ARIZONA_IM_GP3_EINT2_MASK 0x0004 /* IM_GP3_EINT2 */
4799 #define ARIZONA_IM_GP3_EINT2_SHIFT 2 /* IM_GP3_EINT2 */
4800 #define ARIZONA_IM_GP3_EINT2_WIDTH 1 /* IM_GP3_EINT2 */
4801 #define ARIZONA_IM_GP2_EINT2 0x0002 /* IM_GP2_EINT2 */
4802 #define ARIZONA_IM_GP2_EINT2_MASK 0x0002 /* IM_GP2_EINT2 */
4803 #define ARIZONA_IM_GP2_EINT2_SHIFT 1 /* IM_GP2_EINT2 */
4804 #define ARIZONA_IM_GP2_EINT2_WIDTH 1 /* IM_GP2_EINT2 */
4805 #define ARIZONA_IM_GP1_EINT2 0x0001 /* IM_GP1_EINT2 */
4806 #define ARIZONA_IM_GP1_EINT2_MASK 0x0001 /* IM_GP1_EINT2 */
4807 #define ARIZONA_IM_GP1_EINT2_SHIFT 0 /* IM_GP1_EINT2 */
4808 #define ARIZONA_IM_GP1_EINT2_WIDTH 1 /* IM_GP1_EINT2 */
4811 * R3353 (0xD19) - IRQ2 Status 2 Mask
4813 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
4814 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
4815 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT2 */
4816 #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT2 */
4817 #define ARIZONA_IM_DSP_IRQ2_EINT2 0x0002 /* IM_DSP_IRQ2_EINT2 */
4818 #define ARIZONA_IM_DSP_IRQ2_EINT2_MASK 0x0002 /* IM_DSP_IRQ2_EINT2 */
4819 #define ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT 1 /* IM_DSP_IRQ2_EINT2 */
4820 #define ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH 1 /* IM_DSP_IRQ2_EINT2 */
4821 #define ARIZONA_IM_DSP_IRQ1_EINT2 0x0001 /* IM_DSP_IRQ1_EINT2 */
4822 #define ARIZONA_IM_DSP_IRQ1_EINT2_MASK 0x0001 /* IM_DSP_IRQ1_EINT2 */
4823 #define ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT 0 /* IM_DSP_IRQ1_EINT2 */
4824 #define ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH 1 /* IM_DSP_IRQ1_EINT2 */
4827 * R3354 (0xD1A) - IRQ2 Status 3 Mask
4829 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4830 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4831 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4832 #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
4833 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
4834 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
4835 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */
4836 #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */
4837 #define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */
4838 #define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */
4839 #define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */
4840 #define ARIZONA_IM_HPDET_EINT2_WIDTH 1 /* IM_HPDET_EINT2 */
4841 #define ARIZONA_IM_MICDET_EINT2 0x1000 /* IM_MICDET_EINT2 */
4842 #define ARIZONA_IM_MICDET_EINT2_MASK 0x1000 /* IM_MICDET_EINT2 */
4843 #define ARIZONA_IM_MICDET_EINT2_SHIFT 12 /* IM_MICDET_EINT2 */
4844 #define ARIZONA_IM_MICDET_EINT2_WIDTH 1 /* IM_MICDET_EINT2 */
4845 #define ARIZONA_IM_WSEQ_DONE_EINT2 0x0800 /* IM_WSEQ_DONE_EINT2 */
4846 #define ARIZONA_IM_WSEQ_DONE_EINT2_MASK 0x0800 /* IM_WSEQ_DONE_EINT2 */
4847 #define ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT 11 /* IM_WSEQ_DONE_EINT2 */
4848 #define ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH 1 /* IM_WSEQ_DONE_EINT2 */
4849 #define ARIZONA_IM_DRC2_SIG_DET_EINT2 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
4850 #define ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
4851 #define ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT 10 /* IM_DRC2_SIG_DET_EINT2 */
4852 #define ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH 1 /* IM_DRC2_SIG_DET_EINT2 */
4853 #define ARIZONA_IM_DRC1_SIG_DET_EINT2 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
4854 #define ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
4855 #define ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT 9 /* IM_DRC1_SIG_DET_EINT2 */
4856 #define ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH 1 /* IM_DRC1_SIG_DET_EINT2 */
4857 #define ARIZONA_IM_ASRC2_LOCK_EINT2 0x0100 /* IM_ASRC2_LOCK_EINT2 */
4858 #define ARIZONA_IM_ASRC2_LOCK_EINT2_MASK 0x0100 /* IM_ASRC2_LOCK_EINT2 */
4859 #define ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT 8 /* IM_ASRC2_LOCK_EINT2 */
4860 #define ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_LOCK_EINT2 */
4861 #define ARIZONA_IM_ASRC1_LOCK_EINT2 0x0080 /* IM_ASRC1_LOCK_EINT2 */
4862 #define ARIZONA_IM_ASRC1_LOCK_EINT2_MASK 0x0080 /* IM_ASRC1_LOCK_EINT2 */
4863 #define ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT 7 /* IM_ASRC1_LOCK_EINT2 */
4864 #define ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_LOCK_EINT2 */
4865 #define ARIZONA_IM_UNDERCLOCKED_EINT2 0x0040 /* IM_UNDERCLOCKED_EINT2 */
4866 #define ARIZONA_IM_UNDERCLOCKED_EINT2_MASK 0x0040 /* IM_UNDERCLOCKED_EINT2 */
4867 #define ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT 6 /* IM_UNDERCLOCKED_EINT2 */
4868 #define ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH 1 /* IM_UNDERCLOCKED_EINT2 */
4869 #define ARIZONA_IM_OVERCLOCKED_EINT2 0x0020 /* IM_OVERCLOCKED_EINT2 */
4870 #define ARIZONA_IM_OVERCLOCKED_EINT2_MASK 0x0020 /* IM_OVERCLOCKED_EINT2 */
4871 #define ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT 5 /* IM_OVERCLOCKED_EINT2 */
4872 #define ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH 1 /* IM_OVERCLOCKED_EINT2 */
4873 #define ARIZONA_IM_FLL2_LOCK_EINT2 0x0008 /* IM_FLL2_LOCK_EINT2 */
4874 #define ARIZONA_IM_FLL2_LOCK_EINT2_MASK 0x0008 /* IM_FLL2_LOCK_EINT2 */
4875 #define ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT 3 /* IM_FLL2_LOCK_EINT2 */
4876 #define ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH 1 /* IM_FLL2_LOCK_EINT2 */
4877 #define ARIZONA_IM_FLL1_LOCK_EINT2 0x0004 /* IM_FLL1_LOCK_EINT2 */
4878 #define ARIZONA_IM_FLL1_LOCK_EINT2_MASK 0x0004 /* IM_FLL1_LOCK_EINT2 */
4879 #define ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT 2 /* IM_FLL1_LOCK_EINT2 */
4880 #define ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH 1 /* IM_FLL1_LOCK_EINT2 */
4881 #define ARIZONA_IM_CLKGEN_ERR_EINT2 0x0002 /* IM_CLKGEN_ERR_EINT2 */
4882 #define ARIZONA_IM_CLKGEN_ERR_EINT2_MASK 0x0002 /* IM_CLKGEN_ERR_EINT2 */
4883 #define ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT 1 /* IM_CLKGEN_ERR_EINT2 */
4884 #define ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_EINT2 */
4885 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4886 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4887 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4888 #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
4891 * R3355 (0xD1B) - IRQ2 Status 4 Mask
4893 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
4894 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
4895 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */
4896 #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */
4897 #define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */
4898 #define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */
4899 #define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */
4900 #define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */
4901 #define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */
4902 #define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */
4903 #define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */
4904 #define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */
4905 #define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */
4906 #define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */
4907 #define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */
4908 #define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */
4909 #define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */
4910 #define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */
4911 #define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */
4912 #define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */
4913 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4914 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4915 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4916 #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
4917 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4918 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4919 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4920 #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
4921 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
4922 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
4923 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */
4924 #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */
4925 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
4926 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
4927 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */
4928 #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */
4929 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
4930 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
4931 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */
4932 #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */
4935 * R3356 (0xD1C) - IRQ2 Status 5 Mask
4938 #define ARIZONA_IM_BOOT_DONE_EINT2 0x0100 /* IM_BOOT_DONE_EINT2 */
4939 #define ARIZONA_IM_BOOT_DONE_EINT2_MASK 0x0100 /* IM_BOOT_DONE_EINT2 */
4940 #define ARIZONA_IM_BOOT_DONE_EINT2_SHIFT 8 /* IM_BOOT_DONE_EINT2 */
4941 #define ARIZONA_IM_BOOT_DONE_EINT2_WIDTH 1 /* IM_BOOT_DONE_EINT2 */
4942 #define ARIZONA_IM_DCS_DAC_DONE_EINT2 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
4943 #define ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
4944 #define ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT 7 /* IM_DCS_DAC_DONE_EINT2 */
4945 #define ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH 1 /* IM_DCS_DAC_DONE_EINT2 */
4946 #define ARIZONA_IM_DCS_HP_DONE_EINT2 0x0040 /* IM_DCS_HP_DONE_EINT2 */
4947 #define ARIZONA_IM_DCS_HP_DONE_EINT2_MASK 0x0040 /* IM_DCS_HP_DONE_EINT2 */
4948 #define ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT 6 /* IM_DCS_HP_DONE_EINT2 */
4949 #define ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH 1 /* IM_DCS_HP_DONE_EINT2 */
4950 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
4951 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
4952 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT2 */
4953 #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT2 */
4954 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
4955 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
4956 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */
4957 #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */
4960 * R3359 (0xD1F) - IRQ2 Control
4962 #define ARIZONA_IM_IRQ2 0x0001 /* IM_IRQ2 */
4963 #define ARIZONA_IM_IRQ2_MASK 0x0001 /* IM_IRQ2 */
4964 #define ARIZONA_IM_IRQ2_SHIFT 0 /* IM_IRQ2 */
4965 #define ARIZONA_IM_IRQ2_WIDTH 1 /* IM_IRQ2 */
4968 * R3360 (0xD20) - Interrupt Raw Status 2
4970 #define ARIZONA_DSP1_RAM_RDY_STS 0x0100 /* DSP1_RAM_RDY_STS */
4971 #define ARIZONA_DSP1_RAM_RDY_STS_MASK 0x0100 /* DSP1_RAM_RDY_STS */
4972 #define ARIZONA_DSP1_RAM_RDY_STS_SHIFT 8 /* DSP1_RAM_RDY_STS */
4973 #define ARIZONA_DSP1_RAM_RDY_STS_WIDTH 1 /* DSP1_RAM_RDY_STS */
4974 #define ARIZONA_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */
4975 #define ARIZONA_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */
4976 #define ARIZONA_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */
4977 #define ARIZONA_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */
4978 #define ARIZONA_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */
4979 #define ARIZONA_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */
4980 #define ARIZONA_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */
4981 #define ARIZONA_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */
4984 * R3361 (0xD21) - Interrupt Raw Status 3
4986 #define ARIZONA_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */
4987 #define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */
4988 #define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
4989 #define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */
4990 #define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
4991 #define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
4992 #define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
4993 #define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
4994 #define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */
4995 #define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */
4996 #define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */
4997 #define ARIZONA_HPDET_STS_WIDTH 1 /* HPDET_STS */
4998 #define ARIZONA_MICDET_STS 0x1000 /* MICDET_STS */
4999 #define ARIZONA_MICDET_STS_MASK 0x1000 /* MICDET_STS */
5000 #define ARIZONA_MICDET_STS_SHIFT 12 /* MICDET_STS */
5001 #define ARIZONA_MICDET_STS_WIDTH 1 /* MICDET_STS */
5002 #define ARIZONA_WSEQ_DONE_STS 0x0800 /* WSEQ_DONE_STS */
5003 #define ARIZONA_WSEQ_DONE_STS_MASK 0x0800 /* WSEQ_DONE_STS */
5004 #define ARIZONA_WSEQ_DONE_STS_SHIFT 11 /* WSEQ_DONE_STS */
5005 #define ARIZONA_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
5006 #define ARIZONA_DRC2_SIG_DET_STS 0x0400 /* DRC2_SIG_DET_STS */
5007 #define ARIZONA_DRC2_SIG_DET_STS_MASK 0x0400 /* DRC2_SIG_DET_STS */
5008 #define ARIZONA_DRC2_SIG_DET_STS_SHIFT 10 /* DRC2_SIG_DET_STS */
5009 #define ARIZONA_DRC2_SIG_DET_STS_WIDTH 1 /* DRC2_SIG_DET_STS */
5010 #define ARIZONA_DRC1_SIG_DET_STS 0x0200 /* DRC1_SIG_DET_STS */
5011 #define ARIZONA_DRC1_SIG_DET_STS_MASK 0x0200 /* DRC1_SIG_DET_STS */
5012 #define ARIZONA_DRC1_SIG_DET_STS_SHIFT 9 /* DRC1_SIG_DET_STS */
5013 #define ARIZONA_DRC1_SIG_DET_STS_WIDTH 1 /* DRC1_SIG_DET_STS */
5014 #define ARIZONA_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */
5015 #define ARIZONA_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */
5016 #define ARIZONA_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */
5017 #define ARIZONA_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */
5018 #define ARIZONA_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */
5019 #define ARIZONA_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */
5020 #define ARIZONA_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */
5021 #define ARIZONA_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */
5022 #define ARIZONA_UNDERCLOCKED_STS 0x0040 /* UNDERCLOCKED_STS */
5023 #define ARIZONA_UNDERCLOCKED_STS_MASK 0x0040 /* UNDERCLOCKED_STS */
5024 #define ARIZONA_UNDERCLOCKED_STS_SHIFT 6 /* UNDERCLOCKED_STS */
5025 #define ARIZONA_UNDERCLOCKED_STS_WIDTH 1 /* UNDERCLOCKED_STS */
5026 #define ARIZONA_OVERCLOCKED_STS 0x0020 /* OVERCLOCKED_STS */
5027 #define ARIZONA_OVERCLOCKED_STS_MASK 0x0020 /* OVERCLOCKED_STS */
5028 #define ARIZONA_OVERCLOCKED_STS_SHIFT 5 /* OVERCLOCKED_STS */
5029 #define ARIZONA_OVERCLOCKED_STS_WIDTH 1 /* OVERCLOCKED_STS */
5030 #define ARIZONA_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
5031 #define ARIZONA_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
5032 #define ARIZONA_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
5033 #define ARIZONA_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
5034 #define ARIZONA_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
5035 #define ARIZONA_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
5036 #define ARIZONA_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
5037 #define ARIZONA_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
5038 #define ARIZONA_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */
5039 #define ARIZONA_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */
5040 #define ARIZONA_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */
5041 #define ARIZONA_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */
5042 #define ARIZONA_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */
5043 #define ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */
5044 #define ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */
5045 #define ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */
5048 * R3362 (0xD22) - Interrupt Raw Status 4
5050 #define ARIZONA_ASRC_CFG_ERR_STS 0x8000 /* ASRC_CFG_ERR_STS */
5051 #define ARIZONA_ASRC_CFG_ERR_STS_MASK 0x8000 /* ASRC_CFG_ERR_STS */
5052 #define ARIZONA_ASRC_CFG_ERR_STS_SHIFT 15 /* ASRC_CFG_ERR_STS */
5053 #define ARIZONA_ASRC_CFG_ERR_STS_WIDTH 1 /* ASRC_CFG_ERR_STS */
5054 #define ARIZONA_AIF3_ERR_STS 0x4000 /* AIF3_ERR_STS */
5055 #define ARIZONA_AIF3_ERR_STS_MASK 0x4000 /* AIF3_ERR_STS */
5056 #define ARIZONA_AIF3_ERR_STS_SHIFT 14 /* AIF3_ERR_STS */
5057 #define ARIZONA_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */
5058 #define ARIZONA_AIF2_ERR_STS 0x2000 /* AIF2_ERR_STS */
5059 #define ARIZONA_AIF2_ERR_STS_MASK 0x2000 /* AIF2_ERR_STS */
5060 #define ARIZONA_AIF2_ERR_STS_SHIFT 13 /* AIF2_ERR_STS */
5061 #define ARIZONA_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */
5062 #define ARIZONA_AIF1_ERR_STS 0x1000 /* AIF1_ERR_STS */
5063 #define ARIZONA_AIF1_ERR_STS_MASK 0x1000 /* AIF1_ERR_STS */
5064 #define ARIZONA_AIF1_ERR_STS_SHIFT 12 /* AIF1_ERR_STS */
5065 #define ARIZONA_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */
5066 #define ARIZONA_CTRLIF_ERR_STS 0x0800 /* CTRLIF_ERR_STS */
5067 #define ARIZONA_CTRLIF_ERR_STS_MASK 0x0800 /* CTRLIF_ERR_STS */
5068 #define ARIZONA_CTRLIF_ERR_STS_SHIFT 11 /* CTRLIF_ERR_STS */
5069 #define ARIZONA_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */
5070 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
5071 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
5072 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT 10 /* MIXER_DROPPED_SAMPLE_STS */
5073 #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH 1 /* MIXER_DROPPED_SAMPLE_STS */
5074 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
5075 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
5076 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT 9 /* ASYNC_CLK_ENA_LOW_STS */
5077 #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH 1 /* ASYNC_CLK_ENA_LOW_STS */
5078 #define ARIZONA_SYSCLK_ENA_LOW_STS 0x0100 /* SYSCLK_ENA_LOW_STS */
5079 #define ARIZONA_SYSCLK_ENA_LOW_STS_MASK 0x0100 /* SYSCLK_ENA_LOW_STS */
5080 #define ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT 8 /* SYSCLK_ENA_LOW_STS */
5081 #define ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH 1 /* SYSCLK_ENA_LOW_STS */
5082 #define ARIZONA_ISRC1_CFG_ERR_STS 0x0080 /* ISRC1_CFG_ERR_STS */
5083 #define ARIZONA_ISRC1_CFG_ERR_STS_MASK 0x0080 /* ISRC1_CFG_ERR_STS */
5084 #define ARIZONA_ISRC1_CFG_ERR_STS_SHIFT 7 /* ISRC1_CFG_ERR_STS */
5085 #define ARIZONA_ISRC1_CFG_ERR_STS_WIDTH 1 /* ISRC1_CFG_ERR_STS */
5086 #define ARIZONA_ISRC2_CFG_ERR_STS 0x0040 /* ISRC2_CFG_ERR_STS */
5087 #define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */
5088 #define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */
5089 #define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */
5092 * R3363 (0xD23) - Interrupt Raw Status 5
5094 #define ARIZONA_BOOT_DONE_STS 0x0100 /* BOOT_DONE_STS */
5095 #define ARIZONA_BOOT_DONE_STS_MASK 0x0100 /* BOOT_DONE_STS */
5096 #define ARIZONA_BOOT_DONE_STS_SHIFT 8 /* BOOT_DONE_STS */
5097 #define ARIZONA_BOOT_DONE_STS_WIDTH 1 /* BOOT_DONE_STS */
5098 #define ARIZONA_DCS_DAC_DONE_STS 0x0080 /* DCS_DAC_DONE_STS */
5099 #define ARIZONA_DCS_DAC_DONE_STS_MASK 0x0080 /* DCS_DAC_DONE_STS */
5100 #define ARIZONA_DCS_DAC_DONE_STS_SHIFT 7 /* DCS_DAC_DONE_STS */
5101 #define ARIZONA_DCS_DAC_DONE_STS_WIDTH 1 /* DCS_DAC_DONE_STS */
5102 #define ARIZONA_DCS_HP_DONE_STS 0x0040 /* DCS_HP_DONE_STS */
5103 #define ARIZONA_DCS_HP_DONE_STS_MASK 0x0040 /* DCS_HP_DONE_STS */
5104 #define ARIZONA_DCS_HP_DONE_STS_SHIFT 6 /* DCS_HP_DONE_STS */
5105 #define ARIZONA_DCS_HP_DONE_STS_WIDTH 1 /* DCS_HP_DONE_STS */
5106 #define ARIZONA_FLL2_CLOCK_OK_STS 0x0002 /* FLL2_CLOCK_OK_STS */
5107 #define ARIZONA_FLL2_CLOCK_OK_STS_MASK 0x0002 /* FLL2_CLOCK_OK_STS */
5108 #define ARIZONA_FLL2_CLOCK_OK_STS_SHIFT 1 /* FLL2_CLOCK_OK_STS */
5109 #define ARIZONA_FLL2_CLOCK_OK_STS_WIDTH 1 /* FLL2_CLOCK_OK_STS */
5110 #define ARIZONA_FLL1_CLOCK_OK_STS 0x0001 /* FLL1_CLOCK_OK_STS */
5111 #define ARIZONA_FLL1_CLOCK_OK_STS_MASK 0x0001 /* FLL1_CLOCK_OK_STS */
5112 #define ARIZONA_FLL1_CLOCK_OK_STS_SHIFT 0 /* FLL1_CLOCK_OK_STS */
5113 #define ARIZONA_FLL1_CLOCK_OK_STS_WIDTH 1 /* FLL1_CLOCK_OK_STS */
5116 * R3364 (0xD24) - Interrupt Raw Status 6
5118 #define ARIZONA_PWM_OVERCLOCKED_STS 0x2000 /* PWM_OVERCLOCKED_STS */
5119 #define ARIZONA_PWM_OVERCLOCKED_STS_MASK 0x2000 /* PWM_OVERCLOCKED_STS */
5120 #define ARIZONA_PWM_OVERCLOCKED_STS_SHIFT 13 /* PWM_OVERCLOCKED_STS */
5121 #define ARIZONA_PWM_OVERCLOCKED_STS_WIDTH 1 /* PWM_OVERCLOCKED_STS */
5122 #define ARIZONA_FX_CORE_OVERCLOCKED_STS 0x1000 /* FX_CORE_OVERCLOCKED_STS */
5123 #define ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK 0x1000 /* FX_CORE_OVERCLOCKED_STS */
5124 #define ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT 12 /* FX_CORE_OVERCLOCKED_STS */
5125 #define ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH 1 /* FX_CORE_OVERCLOCKED_STS */
5126 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
5127 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
5128 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT 10 /* DAC_SYS_OVERCLOCKED_STS */
5129 #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH 1 /* DAC_SYS_OVERCLOCKED_STS */
5130 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
5131 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
5132 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT 9 /* DAC_WARP_OVERCLOCKED_STS */
5133 #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH 1 /* DAC_WARP_OVERCLOCKED_STS */
5134 #define ARIZONA_ADC_OVERCLOCKED_STS 0x0100 /* ADC_OVERCLOCKED_STS */
5135 #define ARIZONA_ADC_OVERCLOCKED_STS_MASK 0x0100 /* ADC_OVERCLOCKED_STS */
5136 #define ARIZONA_ADC_OVERCLOCKED_STS_SHIFT 8 /* ADC_OVERCLOCKED_STS */
5137 #define ARIZONA_ADC_OVERCLOCKED_STS_WIDTH 1 /* ADC_OVERCLOCKED_STS */
5138 #define ARIZONA_MIXER_OVERCLOCKED_STS 0x0080 /* MIXER_OVERCLOCKED_STS */
5139 #define ARIZONA_MIXER_OVERCLOCKED_STS_MASK 0x0080 /* MIXER_OVERCLOCKED_STS */
5140 #define ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT 7 /* MIXER_OVERCLOCKED_STS */
5141 #define ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH 1 /* MIXER_OVERCLOCKED_STS */
5142 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
5143 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
5144 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT 6 /* AIF3_ASYNC_OVERCLOCKED_STS */
5145 #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_ASYNC_OVERCLOCKED_STS */
5146 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
5147 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
5148 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT 5 /* AIF2_ASYNC_OVERCLOCKED_STS */
5149 #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_ASYNC_OVERCLOCKED_STS */
5150 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
5151 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
5152 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT 4 /* AIF1_ASYNC_OVERCLOCKED_STS */
5153 #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_ASYNC_OVERCLOCKED_STS */
5154 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
5155 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
5156 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT 3 /* AIF3_SYNC_OVERCLOCKED_STS */
5157 #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_SYNC_OVERCLOCKED_STS */
5158 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
5159 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
5160 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT 2 /* AIF2_SYNC_OVERCLOCKED_STS */
5161 #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_SYNC_OVERCLOCKED_STS */
5162 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
5163 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
5164 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT 1 /* AIF1_SYNC_OVERCLOCKED_STS */
5165 #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_SYNC_OVERCLOCKED_STS */
5166 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
5167 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
5168 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT 0 /* PAD_CTRL_OVERCLOCKED_STS */
5169 #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH 1 /* PAD_CTRL_OVERCLOCKED_STS */
5172 * R3365 (0xD25) - Interrupt Raw Status 7
5174 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
5175 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
5176 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT 15 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
5177 #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
5178 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
5179 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
5180 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
5181 #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
5182 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
5183 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
5184 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
5185 #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
5186 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
5187 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
5188 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT 12 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
5189 #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
5190 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
5191 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
5192 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
5193 #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
5194 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
5195 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
5196 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
5197 #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
5198 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
5199 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
5200 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT 9 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
5201 #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
5202 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
5203 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
5204 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */
5205 #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */
5206 #define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */
5207 #define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */
5208 #define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */
5209 #define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */
5210 #define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */
5211 #define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */
5212 #define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */
5213 #define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */
5216 * R3366 (0xD26) - Interrupt Raw Status 8
5218 #define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */
5219 #define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */
5220 #define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */
5221 #define ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */
5222 #define ARIZONA_AIF2_UNDERCLOCKED_STS 0x0200 /* AIF2_UNDERCLOCKED_STS */
5223 #define ARIZONA_AIF2_UNDERCLOCKED_STS_MASK 0x0200 /* AIF2_UNDERCLOCKED_STS */
5224 #define ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT 9 /* AIF2_UNDERCLOCKED_STS */
5225 #define ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */
5226 #define ARIZONA_AIF1_UNDERCLOCKED_STS 0x0100 /* AIF1_UNDERCLOCKED_STS */
5227 #define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */
5228 #define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */
5229 #define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */
5230 #define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */
5231 #define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */
5232 #define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */
5233 #define ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */
5234 #define ARIZONA_ISRC1_UNDERCLOCKED_STS 0x0020 /* ISRC1_UNDERCLOCKED_STS */
5235 #define ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK 0x0020 /* ISRC1_UNDERCLOCKED_STS */
5236 #define ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT 5 /* ISRC1_UNDERCLOCKED_STS */
5237 #define ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */
5238 #define ARIZONA_FX_UNDERCLOCKED_STS 0x0010 /* FX_UNDERCLOCKED_STS */
5239 #define ARIZONA_FX_UNDERCLOCKED_STS_MASK 0x0010 /* FX_UNDERCLOCKED_STS */
5240 #define ARIZONA_FX_UNDERCLOCKED_STS_SHIFT 4 /* FX_UNDERCLOCKED_STS */
5241 #define ARIZONA_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */
5242 #define ARIZONA_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */
5243 #define ARIZONA_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */
5244 #define ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */
5245 #define ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */
5246 #define ARIZONA_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */
5247 #define ARIZONA_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */
5248 #define ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */
5249 #define ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */
5250 #define ARIZONA_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */
5251 #define ARIZONA_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */
5252 #define ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */
5253 #define ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */
5254 #define ARIZONA_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */
5255 #define ARIZONA_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */
5256 #define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */
5257 #define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */
5260 * R3392 (0xD40) - IRQ Pin Status
5262 #define ARIZONA_IRQ2_STS 0x0002 /* IRQ2_STS */
5263 #define ARIZONA_IRQ2_STS_MASK 0x0002 /* IRQ2_STS */
5264 #define ARIZONA_IRQ2_STS_SHIFT 1 /* IRQ2_STS */
5265 #define ARIZONA_IRQ2_STS_WIDTH 1 /* IRQ2_STS */
5266 #define ARIZONA_IRQ1_STS 0x0001 /* IRQ1_STS */
5267 #define ARIZONA_IRQ1_STS_MASK 0x0001 /* IRQ1_STS */
5268 #define ARIZONA_IRQ1_STS_SHIFT 0 /* IRQ1_STS */
5269 #define ARIZONA_IRQ1_STS_WIDTH 1 /* IRQ1_STS */
5272 * R3393 (0xD41) - ADSP2 IRQ0
5274 #define ARIZONA_DSP_IRQ2 0x0002 /* DSP_IRQ2 */
5275 #define ARIZONA_DSP_IRQ2_MASK 0x0002 /* DSP_IRQ2 */
5276 #define ARIZONA_DSP_IRQ2_SHIFT 1 /* DSP_IRQ2 */
5277 #define ARIZONA_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */
5278 #define ARIZONA_DSP_IRQ1 0x0001 /* DSP_IRQ1 */
5279 #define ARIZONA_DSP_IRQ1_MASK 0x0001 /* DSP_IRQ1 */
5280 #define ARIZONA_DSP_IRQ1_SHIFT 0 /* DSP_IRQ1 */
5281 #define ARIZONA_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */
5284 * R3408 (0xD50) - AOD wkup and trig
5286 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
5287 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_MASK 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
5288 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_SHIFT 7 /* MICD_CLAMP_FALL_TRIG_STS */
5289 #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_WIDTH 1 /* MICD_CLAMP_FALL_TRIG_STS */
5290 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
5291 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_MASK 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
5292 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_SHIFT 6 /* MICD_CLAMP_RISE_TRIG_STS */
5293 #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_WIDTH 1 /* MICD_CLAMP_RISE_TRIG_STS */
5294 #define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */
5295 #define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */
5296 #define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */
5297 #define ARIZONA_GP5_FALL_TRIG_STS_WIDTH 1 /* GP5_FALL_TRIG_STS */
5298 #define ARIZONA_GP5_RISE_TRIG_STS 0x0010 /* GP5_RISE_TRIG_STS */
5299 #define ARIZONA_GP5_RISE_TRIG_STS_MASK 0x0010 /* GP5_RISE_TRIG_STS */
5300 #define ARIZONA_GP5_RISE_TRIG_STS_SHIFT 4 /* GP5_RISE_TRIG_STS */
5301 #define ARIZONA_GP5_RISE_TRIG_STS_WIDTH 1 /* GP5_RISE_TRIG_STS */
5302 #define ARIZONA_JD1_FALL_TRIG_STS 0x0008 /* JD1_FALL_TRIG_STS */
5303 #define ARIZONA_JD1_FALL_TRIG_STS_MASK 0x0008 /* JD1_FALL_TRIG_STS */
5304 #define ARIZONA_JD1_FALL_TRIG_STS_SHIFT 3 /* JD1_FALL_TRIG_STS */
5305 #define ARIZONA_JD1_FALL_TRIG_STS_WIDTH 1 /* JD1_FALL_TRIG_STS */
5306 #define ARIZONA_JD1_RISE_TRIG_STS 0x0004 /* JD1_RISE_TRIG_STS */
5307 #define ARIZONA_JD1_RISE_TRIG_STS_MASK 0x0004 /* JD1_RISE_TRIG_STS */
5308 #define ARIZONA_JD1_RISE_TRIG_STS_SHIFT 2 /* JD1_RISE_TRIG_STS */
5309 #define ARIZONA_JD1_RISE_TRIG_STS_WIDTH 1 /* JD1_RISE_TRIG_STS */
5310 #define ARIZONA_JD2_FALL_TRIG_STS 0x0002 /* JD2_FALL_TRIG_STS */
5311 #define ARIZONA_JD2_FALL_TRIG_STS_MASK 0x0002 /* JD2_FALL_TRIG_STS */
5312 #define ARIZONA_JD2_FALL_TRIG_STS_SHIFT 1 /* JD2_FALL_TRIG_STS */
5313 #define ARIZONA_JD2_FALL_TRIG_STS_WIDTH 1 /* JD2_FALL_TRIG_STS */
5314 #define ARIZONA_JD2_RISE_TRIG_STS 0x0001 /* JD2_RISE_TRIG_STS */
5315 #define ARIZONA_JD2_RISE_TRIG_STS_MASK 0x0001 /* JD2_RISE_TRIG_STS */
5316 #define ARIZONA_JD2_RISE_TRIG_STS_SHIFT 0 /* JD2_RISE_TRIG_STS */
5317 #define ARIZONA_JD2_RISE_TRIG_STS_WIDTH 1 /* JD2_RISE_TRIG_STS */
5320 * R3409 (0xD51) - AOD IRQ1
5322 #define ARIZONA_MICD_CLAMP_FALL_EINT1 0x0080 /* MICD_CLAMP_FALL_EINT1 */
5323 #define ARIZONA_MICD_CLAMP_FALL_EINT1_MASK 0x0080 /* MICD_CLAMP_FALL_EINT1 */
5324 #define ARIZONA_MICD_CLAMP_FALL_EINT1_SHIFT 7 /* MICD_CLAMP_FALL_EINT1 */
5325 #define ARIZONA_MICD_CLAMP_RISE_EINT1 0x0040 /* MICD_CLAMP_RISE_EINT1 */
5326 #define ARIZONA_MICD_CLAMP_RISE_EINT1_MASK 0x0040 /* MICD_CLAMP_RISE_EINT1 */
5327 #define ARIZONA_MICD_CLAMP_RISE_EINT1_SHIFT 6 /* MICD_CLAMP_RISE_EINT1 */
5328 #define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */
5329 #define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */
5330 #define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */
5331 #define ARIZONA_GP5_FALL_EINT1_WIDTH 1 /* GP5_FALL_EINT1 */
5332 #define ARIZONA_GP5_RISE_EINT1 0x0010 /* GP5_RISE_EINT1 */
5333 #define ARIZONA_GP5_RISE_EINT1_MASK 0x0010 /* GP5_RISE_EINT1 */
5334 #define ARIZONA_GP5_RISE_EINT1_SHIFT 4 /* GP5_RISE_EINT1 */
5335 #define ARIZONA_GP5_RISE_EINT1_WIDTH 1 /* GP5_RISE_EINT1 */
5336 #define ARIZONA_JD1_FALL_EINT1 0x0008 /* JD1_FALL_EINT1 */
5337 #define ARIZONA_JD1_FALL_EINT1_MASK 0x0008 /* JD1_FALL_EINT1 */
5338 #define ARIZONA_JD1_FALL_EINT1_SHIFT 3 /* JD1_FALL_EINT1 */
5339 #define ARIZONA_JD1_FALL_EINT1_WIDTH 1 /* JD1_FALL_EINT1 */
5340 #define ARIZONA_JD1_RISE_EINT1 0x0004 /* JD1_RISE_EINT1 */
5341 #define ARIZONA_JD1_RISE_EINT1_MASK 0x0004 /* JD1_RISE_EINT1 */
5342 #define ARIZONA_JD1_RISE_EINT1_SHIFT 2 /* JD1_RISE_EINT1 */
5343 #define ARIZONA_JD1_RISE_EINT1_WIDTH 1 /* JD1_RISE_EINT1 */
5344 #define ARIZONA_JD2_FALL_EINT1 0x0002 /* JD2_FALL_EINT1 */
5345 #define ARIZONA_JD2_FALL_EINT1_MASK 0x0002 /* JD2_FALL_EINT1 */
5346 #define ARIZONA_JD2_FALL_EINT1_SHIFT 1 /* JD2_FALL_EINT1 */
5347 #define ARIZONA_JD2_FALL_EINT1_WIDTH 1 /* JD2_FALL_EINT1 */
5348 #define ARIZONA_JD2_RISE_EINT1 0x0001 /* JD2_RISE_EINT1 */
5349 #define ARIZONA_JD2_RISE_EINT1_MASK 0x0001 /* JD2_RISE_EINT1 */
5350 #define ARIZONA_JD2_RISE_EINT1_SHIFT 0 /* JD2_RISE_EINT1 */
5351 #define ARIZONA_JD2_RISE_EINT1_WIDTH 1 /* JD2_RISE_EINT1 */
5354 * R3410 (0xD52) - AOD IRQ2
5356 #define ARIZONA_MICD_CLAMP_FALL_EINT2 0x0080 /* MICD_CLAMP_FALL_EINT2 */
5357 #define ARIZONA_MICD_CLAMP_FALL_EINT2_MASK 0x0080 /* MICD_CLAMP_FALL_EINT2 */
5358 #define ARIZONA_MICD_CLAMP_FALL_EINT2_SHIFT 7 /* MICD_CLAMP_FALL_EINT2 */
5359 #define ARIZONA_MICD_CLAMP_RISE_EINT2 0x0040 /* MICD_CLAMP_RISE_EINT2 */
5360 #define ARIZONA_MICD_CLAMP_RISE_EINT2_MASK 0x0040 /* MICD_CLAMP_RISE_EINT2 */
5361 #define ARIZONA_MICD_CLAMP_RISE_EINT2_SHIFT 6 /* MICD_CLAMP_RISE_EINT2 */
5362 #define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */
5363 #define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */
5364 #define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */
5365 #define ARIZONA_GP5_FALL_EINT2_WIDTH 1 /* GP5_FALL_EINT2 */
5366 #define ARIZONA_GP5_RISE_EINT2 0x0010 /* GP5_RISE_EINT2 */
5367 #define ARIZONA_GP5_RISE_EINT2_MASK 0x0010 /* GP5_RISE_EINT2 */
5368 #define ARIZONA_GP5_RISE_EINT2_SHIFT 4 /* GP5_RISE_EINT2 */
5369 #define ARIZONA_GP5_RISE_EINT2_WIDTH 1 /* GP5_RISE_EINT2 */
5370 #define ARIZONA_JD1_FALL_EINT2 0x0008 /* JD1_FALL_EINT2 */
5371 #define ARIZONA_JD1_FALL_EINT2_MASK 0x0008 /* JD1_FALL_EINT2 */
5372 #define ARIZONA_JD1_FALL_EINT2_SHIFT 3 /* JD1_FALL_EINT2 */
5373 #define ARIZONA_JD1_FALL_EINT2_WIDTH 1 /* JD1_FALL_EINT2 */
5374 #define ARIZONA_JD1_RISE_EINT2 0x0004 /* JD1_RISE_EINT2 */
5375 #define ARIZONA_JD1_RISE_EINT2_MASK 0x0004 /* JD1_RISE_EINT2 */
5376 #define ARIZONA_JD1_RISE_EINT2_SHIFT 2 /* JD1_RISE_EINT2 */
5377 #define ARIZONA_JD1_RISE_EINT2_WIDTH 1 /* JD1_RISE_EINT2 */
5378 #define ARIZONA_JD2_FALL_EINT2 0x0002 /* JD2_FALL_EINT2 */
5379 #define ARIZONA_JD2_FALL_EINT2_MASK 0x0002 /* JD2_FALL_EINT2 */
5380 #define ARIZONA_JD2_FALL_EINT2_SHIFT 1 /* JD2_FALL_EINT2 */
5381 #define ARIZONA_JD2_FALL_EINT2_WIDTH 1 /* JD2_FALL_EINT2 */
5382 #define ARIZONA_JD2_RISE_EINT2 0x0001 /* JD2_RISE_EINT2 */
5383 #define ARIZONA_JD2_RISE_EINT2_MASK 0x0001 /* JD2_RISE_EINT2 */
5384 #define ARIZONA_JD2_RISE_EINT2_SHIFT 0 /* JD2_RISE_EINT2 */
5385 #define ARIZONA_JD2_RISE_EINT2_WIDTH 1 /* JD2_RISE_EINT2 */
5388 * R3411 (0xD53) - AOD IRQ Mask IRQ1
5390 #define ARIZONA_IM_GP5_FALL_EINT1 0x0020 /* IM_GP5_FALL_EINT1 */
5391 #define ARIZONA_IM_GP5_FALL_EINT1_MASK 0x0020 /* IM_GP5_FALL_EINT1 */
5392 #define ARIZONA_IM_GP5_FALL_EINT1_SHIFT 5 /* IM_GP5_FALL_EINT1 */
5393 #define ARIZONA_IM_GP5_FALL_EINT1_WIDTH 1 /* IM_GP5_FALL_EINT1 */
5394 #define ARIZONA_IM_GP5_RISE_EINT1 0x0010 /* IM_GP5_RISE_EINT1 */
5395 #define ARIZONA_IM_GP5_RISE_EINT1_MASK 0x0010 /* IM_GP5_RISE_EINT1 */
5396 #define ARIZONA_IM_GP5_RISE_EINT1_SHIFT 4 /* IM_GP5_RISE_EINT1 */
5397 #define ARIZONA_IM_GP5_RISE_EINT1_WIDTH 1 /* IM_GP5_RISE_EINT1 */
5398 #define ARIZONA_IM_JD1_FALL_EINT1 0x0008 /* IM_JD1_FALL_EINT1 */
5399 #define ARIZONA_IM_JD1_FALL_EINT1_MASK 0x0008 /* IM_JD1_FALL_EINT1 */
5400 #define ARIZONA_IM_JD1_FALL_EINT1_SHIFT 3 /* IM_JD1_FALL_EINT1 */
5401 #define ARIZONA_IM_JD1_FALL_EINT1_WIDTH 1 /* IM_JD1_FALL_EINT1 */
5402 #define ARIZONA_IM_JD1_RISE_EINT1 0x0004 /* IM_JD1_RISE_EINT1 */
5403 #define ARIZONA_IM_JD1_RISE_EINT1_MASK 0x0004 /* IM_JD1_RISE_EINT1 */
5404 #define ARIZONA_IM_JD1_RISE_EINT1_SHIFT 2 /* IM_JD1_RISE_EINT1 */
5405 #define ARIZONA_IM_JD1_RISE_EINT1_WIDTH 1 /* IM_JD1_RISE_EINT1 */
5406 #define ARIZONA_IM_JD2_FALL_EINT1 0x0002 /* IM_JD2_FALL_EINT1 */
5407 #define ARIZONA_IM_JD2_FALL_EINT1_MASK 0x0002 /* IM_JD2_FALL_EINT1 */
5408 #define ARIZONA_IM_JD2_FALL_EINT1_SHIFT 1 /* IM_JD2_FALL_EINT1 */
5409 #define ARIZONA_IM_JD2_FALL_EINT1_WIDTH 1 /* IM_JD2_FALL_EINT1 */
5410 #define ARIZONA_IM_JD2_RISE_EINT1 0x0001 /* IM_JD2_RISE_EINT1 */
5411 #define ARIZONA_IM_JD2_RISE_EINT1_MASK 0x0001 /* IM_JD2_RISE_EINT1 */
5412 #define ARIZONA_IM_JD2_RISE_EINT1_SHIFT 0 /* IM_JD2_RISE_EINT1 */
5413 #define ARIZONA_IM_JD2_RISE_EINT1_WIDTH 1 /* IM_JD2_RISE_EINT1 */
5416 * R3412 (0xD54) - AOD IRQ Mask IRQ2
5418 #define ARIZONA_IM_GP5_FALL_EINT2 0x0020 /* IM_GP5_FALL_EINT2 */
5419 #define ARIZONA_IM_GP5_FALL_EINT2_MASK 0x0020 /* IM_GP5_FALL_EINT2 */
5420 #define ARIZONA_IM_GP5_FALL_EINT2_SHIFT 5 /* IM_GP5_FALL_EINT2 */
5421 #define ARIZONA_IM_GP5_FALL_EINT2_WIDTH 1 /* IM_GP5_FALL_EINT2 */
5422 #define ARIZONA_IM_GP5_RISE_EINT2 0x0010 /* IM_GP5_RISE_EINT2 */
5423 #define ARIZONA_IM_GP5_RISE_EINT2_MASK 0x0010 /* IM_GP5_RISE_EINT2 */
5424 #define ARIZONA_IM_GP5_RISE_EINT2_SHIFT 4 /* IM_GP5_RISE_EINT2 */
5425 #define ARIZONA_IM_GP5_RISE_EINT2_WIDTH 1 /* IM_GP5_RISE_EINT2 */
5426 #define ARIZONA_IM_JD1_FALL_EINT2 0x0008 /* IM_JD1_FALL_EINT2 */
5427 #define ARIZONA_IM_JD1_FALL_EINT2_MASK 0x0008 /* IM_JD1_FALL_EINT2 */
5428 #define ARIZONA_IM_JD1_FALL_EINT2_SHIFT 3 /* IM_JD1_FALL_EINT2 */
5429 #define ARIZONA_IM_JD1_FALL_EINT2_WIDTH 1 /* IM_JD1_FALL_EINT2 */
5430 #define ARIZONA_IM_JD1_RISE_EINT2 0x0004 /* IM_JD1_RISE_EINT2 */
5431 #define ARIZONA_IM_JD1_RISE_EINT2_MASK 0x0004 /* IM_JD1_RISE_EINT2 */
5432 #define ARIZONA_IM_JD1_RISE_EINT2_SHIFT 2 /* IM_JD1_RISE_EINT2 */
5433 #define ARIZONA_IM_JD1_RISE_EINT2_WIDTH 1 /* IM_JD1_RISE_EINT2 */
5434 #define ARIZONA_IM_JD2_FALL_EINT2 0x0002 /* IM_JD2_FALL_EINT2 */
5435 #define ARIZONA_IM_JD2_FALL_EINT2_MASK 0x0002 /* IM_JD2_FALL_EINT2 */
5436 #define ARIZONA_IM_JD2_FALL_EINT2_SHIFT 1 /* IM_JD2_FALL_EINT2 */
5437 #define ARIZONA_IM_JD2_FALL_EINT2_WIDTH 1 /* IM_JD2_FALL_EINT2 */
5438 #define ARIZONA_IM_JD2_RISE_EINT2 0x0001 /* IM_JD2_RISE_EINT2 */
5439 #define ARIZONA_IM_JD2_RISE_EINT2_MASK 0x0001 /* IM_JD2_RISE_EINT2 */
5440 #define ARIZONA_IM_JD2_RISE_EINT2_SHIFT 0 /* IM_JD2_RISE_EINT2 */
5441 #define ARIZONA_IM_JD2_RISE_EINT2_WIDTH 1 /* IM_JD2_RISE_EINT2 */
5444 * R3413 (0xD55) - AOD IRQ Raw Status
5446 #define ARIZONA_MICD_CLAMP_STS 0x0008 /* MICD_CLAMP_STS */
5447 #define ARIZONA_MICD_CLAMP_STS_MASK 0x0008 /* MICD_CLAMP_STS */
5448 #define ARIZONA_MICD_CLAMP_STS_SHIFT 3 /* MICD_CLAMP_STS */
5449 #define ARIZONA_MICD_CLAMP_STS_WIDTH 1 /* MICD_CLAMP_STS */
5450 #define ARIZONA_GP5_STS 0x0004 /* GP5_STS */
5451 #define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */
5452 #define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */
5453 #define ARIZONA_GP5_STS_WIDTH 1 /* GP5_STS */
5454 #define ARIZONA_JD2_STS 0x0002 /* JD2_STS */
5455 #define ARIZONA_JD2_STS_MASK 0x0002 /* JD2_STS */
5456 #define ARIZONA_JD2_STS_SHIFT 1 /* JD2_STS */
5457 #define ARIZONA_JD2_STS_WIDTH 1 /* JD2_STS */
5458 #define ARIZONA_JD1_STS 0x0001 /* JD1_STS */
5459 #define ARIZONA_JD1_STS_MASK 0x0001 /* JD1_STS */
5460 #define ARIZONA_JD1_STS_SHIFT 0 /* JD1_STS */
5461 #define ARIZONA_JD1_STS_WIDTH 1 /* JD1_STS */
5464 * R3414 (0xD56) - Jack detect debounce
5466 #define ARIZONA_MICD_CLAMP_DB 0x0008 /* MICD_CLAMP_DB */
5467 #define ARIZONA_MICD_CLAMP_DB_MASK 0x0008 /* MICD_CLAMP_DB */
5468 #define ARIZONA_MICD_CLAMP_DB_SHIFT 3 /* MICD_CLAMP_DB */
5469 #define ARIZONA_MICD_CLAMP_DB_WIDTH 1 /* MICD_CLAMP_DB */
5470 #define ARIZONA_JD2_DB 0x0002 /* JD2_DB */
5471 #define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */
5472 #define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */
5473 #define ARIZONA_JD2_DB_WIDTH 1 /* JD2_DB */
5474 #define ARIZONA_JD1_DB 0x0001 /* JD1_DB */
5475 #define ARIZONA_JD1_DB_MASK 0x0001 /* JD1_DB */
5476 #define ARIZONA_JD1_DB_SHIFT 0 /* JD1_DB */
5477 #define ARIZONA_JD1_DB_WIDTH 1 /* JD1_DB */
5480 * R3584 (0xE00) - FX_Ctrl1
5482 #define ARIZONA_FX_RATE_MASK 0x7800 /* FX_RATE - [14:11] */
5483 #define ARIZONA_FX_RATE_SHIFT 11 /* FX_RATE - [14:11] */
5484 #define ARIZONA_FX_RATE_WIDTH 4 /* FX_RATE - [14:11] */
5487 * R3585 (0xE01) - FX_Ctrl2
5489 #define ARIZONA_FX_STS_MASK 0xFFF0 /* FX_STS - [15:4] */
5490 #define ARIZONA_FX_STS_SHIFT 4 /* FX_STS - [15:4] */
5491 #define ARIZONA_FX_STS_WIDTH 12 /* FX_STS - [15:4] */
5494 * R3600 (0xE10) - EQ1_1
5496 #define ARIZONA_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */
5497 #define ARIZONA_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */
5498 #define ARIZONA_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */
5499 #define ARIZONA_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */
5500 #define ARIZONA_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */
5501 #define ARIZONA_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */
5502 #define ARIZONA_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */
5503 #define ARIZONA_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */
5504 #define ARIZONA_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */
5505 #define ARIZONA_EQ1_ENA 0x0001 /* EQ1_ENA */
5506 #define ARIZONA_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */
5507 #define ARIZONA_EQ1_ENA_SHIFT 0 /* EQ1_ENA */
5508 #define ARIZONA_EQ1_ENA_WIDTH 1 /* EQ1_ENA */
5511 * R3601 (0xE11) - EQ1_2
5513 #define ARIZONA_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */
5514 #define ARIZONA_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */
5515 #define ARIZONA_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */
5516 #define ARIZONA_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */
5517 #define ARIZONA_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */
5518 #define ARIZONA_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */
5519 #define ARIZONA_EQ1_B1_MODE 0x0001 /* EQ1_B1_MODE */
5520 #define ARIZONA_EQ1_B1_MODE_MASK 0x0001 /* EQ1_B1_MODE */
5521 #define ARIZONA_EQ1_B1_MODE_SHIFT 0 /* EQ1_B1_MODE */
5522 #define ARIZONA_EQ1_B1_MODE_WIDTH 1 /* EQ1_B1_MODE */
5525 * R3602 (0xE12) - EQ1_3
5527 #define ARIZONA_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */
5528 #define ARIZONA_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */
5529 #define ARIZONA_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */
5532 * R3603 (0xE13) - EQ1_4
5534 #define ARIZONA_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */
5535 #define ARIZONA_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */
5536 #define ARIZONA_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */
5539 * R3604 (0xE14) - EQ1_5
5541 #define ARIZONA_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */
5542 #define ARIZONA_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */
5543 #define ARIZONA_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */
5546 * R3605 (0xE15) - EQ1_6
5548 #define ARIZONA_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */
5549 #define ARIZONA_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */
5550 #define ARIZONA_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */
5553 * R3606 (0xE16) - EQ1_7
5555 #define ARIZONA_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */
5556 #define ARIZONA_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */
5557 #define ARIZONA_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */
5560 * R3607 (0xE17) - EQ1_8
5562 #define ARIZONA_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */
5563 #define ARIZONA_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */
5564 #define ARIZONA_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */
5567 * R3608 (0xE18) - EQ1_9
5569 #define ARIZONA_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */
5570 #define ARIZONA_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */
5571 #define ARIZONA_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */
5574 * R3609 (0xE19) - EQ1_10
5576 #define ARIZONA_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */
5577 #define ARIZONA_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */
5578 #define ARIZONA_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */
5581 * R3610 (0xE1A) - EQ1_11
5583 #define ARIZONA_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */
5584 #define ARIZONA_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */
5585 #define ARIZONA_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */
5588 * R3611 (0xE1B) - EQ1_12
5590 #define ARIZONA_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */
5591 #define ARIZONA_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */
5592 #define ARIZONA_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */
5595 * R3612 (0xE1C) - EQ1_13
5597 #define ARIZONA_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */
5598 #define ARIZONA_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */
5599 #define ARIZONA_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */
5602 * R3613 (0xE1D) - EQ1_14
5604 #define ARIZONA_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */
5605 #define ARIZONA_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */
5606 #define ARIZONA_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */
5609 * R3614 (0xE1E) - EQ1_15
5611 #define ARIZONA_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */
5612 #define ARIZONA_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */
5613 #define ARIZONA_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */
5616 * R3615 (0xE1F) - EQ1_16
5618 #define ARIZONA_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */
5619 #define ARIZONA_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */
5620 #define ARIZONA_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */
5623 * R3616 (0xE20) - EQ1_17
5625 #define ARIZONA_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */
5626 #define ARIZONA_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */
5627 #define ARIZONA_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */
5630 * R3617 (0xE21) - EQ1_18
5632 #define ARIZONA_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */
5633 #define ARIZONA_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */
5634 #define ARIZONA_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */
5637 * R3618 (0xE22) - EQ1_19
5639 #define ARIZONA_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */
5640 #define ARIZONA_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */
5641 #define ARIZONA_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */
5644 * R3619 (0xE23) - EQ1_20
5646 #define ARIZONA_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */
5647 #define ARIZONA_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */
5648 #define ARIZONA_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */
5651 * R3620 (0xE24) - EQ1_21
5653 #define ARIZONA_EQ1_B1_C_MASK 0xFFFF /* EQ1_B1_C - [15:0] */
5654 #define ARIZONA_EQ1_B1_C_SHIFT 0 /* EQ1_B1_C - [15:0] */
5655 #define ARIZONA_EQ1_B1_C_WIDTH 16 /* EQ1_B1_C - [15:0] */
5658 * R3622 (0xE26) - EQ2_1
5660 #define ARIZONA_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */
5661 #define ARIZONA_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */
5662 #define ARIZONA_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */
5663 #define ARIZONA_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */
5664 #define ARIZONA_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */
5665 #define ARIZONA_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */
5666 #define ARIZONA_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */
5667 #define ARIZONA_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */
5668 #define ARIZONA_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */
5669 #define ARIZONA_EQ2_ENA 0x0001 /* EQ2_ENA */
5670 #define ARIZONA_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */
5671 #define ARIZONA_EQ2_ENA_SHIFT 0 /* EQ2_ENA */
5672 #define ARIZONA_EQ2_ENA_WIDTH 1 /* EQ2_ENA */
5675 * R3623 (0xE27) - EQ2_2
5677 #define ARIZONA_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */
5678 #define ARIZONA_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */
5679 #define ARIZONA_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */
5680 #define ARIZONA_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */
5681 #define ARIZONA_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */
5682 #define ARIZONA_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */
5683 #define ARIZONA_EQ2_B1_MODE 0x0001 /* EQ2_B1_MODE */
5684 #define ARIZONA_EQ2_B1_MODE_MASK 0x0001 /* EQ2_B1_MODE */
5685 #define ARIZONA_EQ2_B1_MODE_SHIFT 0 /* EQ2_B1_MODE */
5686 #define ARIZONA_EQ2_B1_MODE_WIDTH 1 /* EQ2_B1_MODE */
5689 * R3624 (0xE28) - EQ2_3
5691 #define ARIZONA_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */
5692 #define ARIZONA_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */
5693 #define ARIZONA_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */
5696 * R3625 (0xE29) - EQ2_4
5698 #define ARIZONA_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */
5699 #define ARIZONA_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */
5700 #define ARIZONA_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */
5703 * R3626 (0xE2A) - EQ2_5
5705 #define ARIZONA_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */
5706 #define ARIZONA_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */
5707 #define ARIZONA_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */
5710 * R3627 (0xE2B) - EQ2_6
5712 #define ARIZONA_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */
5713 #define ARIZONA_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */
5714 #define ARIZONA_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */
5717 * R3628 (0xE2C) - EQ2_7
5719 #define ARIZONA_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */
5720 #define ARIZONA_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */
5721 #define ARIZONA_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */
5724 * R3629 (0xE2D) - EQ2_8
5726 #define ARIZONA_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */
5727 #define ARIZONA_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */
5728 #define ARIZONA_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */
5731 * R3630 (0xE2E) - EQ2_9
5733 #define ARIZONA_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */
5734 #define ARIZONA_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */
5735 #define ARIZONA_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */
5738 * R3631 (0xE2F) - EQ2_10
5740 #define ARIZONA_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */
5741 #define ARIZONA_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */
5742 #define ARIZONA_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */
5745 * R3632 (0xE30) - EQ2_11
5747 #define ARIZONA_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */
5748 #define ARIZONA_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */
5749 #define ARIZONA_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */
5752 * R3633 (0xE31) - EQ2_12
5754 #define ARIZONA_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */
5755 #define ARIZONA_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */
5756 #define ARIZONA_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */
5759 * R3634 (0xE32) - EQ2_13
5761 #define ARIZONA_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */
5762 #define ARIZONA_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */
5763 #define ARIZONA_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */
5766 * R3635 (0xE33) - EQ2_14
5768 #define ARIZONA_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */
5769 #define ARIZONA_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */
5770 #define ARIZONA_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */
5773 * R3636 (0xE34) - EQ2_15
5775 #define ARIZONA_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */
5776 #define ARIZONA_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */
5777 #define ARIZONA_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */
5780 * R3637 (0xE35) - EQ2_16
5782 #define ARIZONA_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */
5783 #define ARIZONA_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */
5784 #define ARIZONA_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */
5787 * R3638 (0xE36) - EQ2_17
5789 #define ARIZONA_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */
5790 #define ARIZONA_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */
5791 #define ARIZONA_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */
5794 * R3639 (0xE37) - EQ2_18
5796 #define ARIZONA_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */
5797 #define ARIZONA_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */
5798 #define ARIZONA_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */
5801 * R3640 (0xE38) - EQ2_19
5803 #define ARIZONA_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */
5804 #define ARIZONA_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */
5805 #define ARIZONA_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */
5808 * R3641 (0xE39) - EQ2_20
5810 #define ARIZONA_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */
5811 #define ARIZONA_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */
5812 #define ARIZONA_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */
5815 * R3642 (0xE3A) - EQ2_21
5817 #define ARIZONA_EQ2_B1_C_MASK 0xFFFF /* EQ2_B1_C - [15:0] */
5818 #define ARIZONA_EQ2_B1_C_SHIFT 0 /* EQ2_B1_C - [15:0] */
5819 #define ARIZONA_EQ2_B1_C_WIDTH 16 /* EQ2_B1_C - [15:0] */
5822 * R3644 (0xE3C) - EQ3_1
5824 #define ARIZONA_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */
5825 #define ARIZONA_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */
5826 #define ARIZONA_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */
5827 #define ARIZONA_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */
5828 #define ARIZONA_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */
5829 #define ARIZONA_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */
5830 #define ARIZONA_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */
5831 #define ARIZONA_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */
5832 #define ARIZONA_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */
5833 #define ARIZONA_EQ3_ENA 0x0001 /* EQ3_ENA */
5834 #define ARIZONA_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */
5835 #define ARIZONA_EQ3_ENA_SHIFT 0 /* EQ3_ENA */
5836 #define ARIZONA_EQ3_ENA_WIDTH 1 /* EQ3_ENA */
5839 * R3645 (0xE3D) - EQ3_2
5841 #define ARIZONA_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */
5842 #define ARIZONA_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */
5843 #define ARIZONA_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */
5844 #define ARIZONA_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */
5845 #define ARIZONA_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */
5846 #define ARIZONA_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */
5847 #define ARIZONA_EQ3_B1_MODE 0x0001 /* EQ3_B1_MODE */
5848 #define ARIZONA_EQ3_B1_MODE_MASK 0x0001 /* EQ3_B1_MODE */
5849 #define ARIZONA_EQ3_B1_MODE_SHIFT 0 /* EQ3_B1_MODE */
5850 #define ARIZONA_EQ3_B1_MODE_WIDTH 1 /* EQ3_B1_MODE */
5853 * R3646 (0xE3E) - EQ3_3
5855 #define ARIZONA_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */
5856 #define ARIZONA_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */
5857 #define ARIZONA_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */
5860 * R3647 (0xE3F) - EQ3_4
5862 #define ARIZONA_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */
5863 #define ARIZONA_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */
5864 #define ARIZONA_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */
5867 * R3648 (0xE40) - EQ3_5
5869 #define ARIZONA_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */
5870 #define ARIZONA_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */
5871 #define ARIZONA_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */
5874 * R3649 (0xE41) - EQ3_6
5876 #define ARIZONA_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */
5877 #define ARIZONA_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */
5878 #define ARIZONA_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */
5881 * R3650 (0xE42) - EQ3_7
5883 #define ARIZONA_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */
5884 #define ARIZONA_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */
5885 #define ARIZONA_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */
5888 * R3651 (0xE43) - EQ3_8
5890 #define ARIZONA_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */
5891 #define ARIZONA_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */
5892 #define ARIZONA_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */
5895 * R3652 (0xE44) - EQ3_9
5897 #define ARIZONA_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */
5898 #define ARIZONA_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */
5899 #define ARIZONA_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */
5902 * R3653 (0xE45) - EQ3_10
5904 #define ARIZONA_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */
5905 #define ARIZONA_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */
5906 #define ARIZONA_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */
5909 * R3654 (0xE46) - EQ3_11
5911 #define ARIZONA_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */
5912 #define ARIZONA_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */
5913 #define ARIZONA_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */
5916 * R3655 (0xE47) - EQ3_12
5918 #define ARIZONA_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */
5919 #define ARIZONA_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */
5920 #define ARIZONA_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */
5923 * R3656 (0xE48) - EQ3_13
5925 #define ARIZONA_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */
5926 #define ARIZONA_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */
5927 #define ARIZONA_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */
5930 * R3657 (0xE49) - EQ3_14
5932 #define ARIZONA_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */
5933 #define ARIZONA_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */
5934 #define ARIZONA_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */
5937 * R3658 (0xE4A) - EQ3_15
5939 #define ARIZONA_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */
5940 #define ARIZONA_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */
5941 #define ARIZONA_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */
5944 * R3659 (0xE4B) - EQ3_16
5946 #define ARIZONA_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */
5947 #define ARIZONA_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */
5948 #define ARIZONA_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */
5951 * R3660 (0xE4C) - EQ3_17
5953 #define ARIZONA_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */
5954 #define ARIZONA_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */
5955 #define ARIZONA_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */
5958 * R3661 (0xE4D) - EQ3_18
5960 #define ARIZONA_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */
5961 #define ARIZONA_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */
5962 #define ARIZONA_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */
5965 * R3662 (0xE4E) - EQ3_19
5967 #define ARIZONA_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */
5968 #define ARIZONA_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */
5969 #define ARIZONA_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */
5972 * R3663 (0xE4F) - EQ3_20
5974 #define ARIZONA_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */
5975 #define ARIZONA_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */
5976 #define ARIZONA_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */
5979 * R3664 (0xE50) - EQ3_21
5981 #define ARIZONA_EQ3_B1_C_MASK 0xFFFF /* EQ3_B1_C - [15:0] */
5982 #define ARIZONA_EQ3_B1_C_SHIFT 0 /* EQ3_B1_C - [15:0] */
5983 #define ARIZONA_EQ3_B1_C_WIDTH 16 /* EQ3_B1_C - [15:0] */
5986 * R3666 (0xE52) - EQ4_1
5988 #define ARIZONA_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */
5989 #define ARIZONA_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */
5990 #define ARIZONA_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */
5991 #define ARIZONA_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */
5992 #define ARIZONA_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */
5993 #define ARIZONA_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */
5994 #define ARIZONA_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */
5995 #define ARIZONA_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */
5996 #define ARIZONA_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */
5997 #define ARIZONA_EQ4_ENA 0x0001 /* EQ4_ENA */
5998 #define ARIZONA_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */
5999 #define ARIZONA_EQ4_ENA_SHIFT 0 /* EQ4_ENA */
6000 #define ARIZONA_EQ4_ENA_WIDTH 1 /* EQ4_ENA */
6003 * R3667 (0xE53) - EQ4_2
6005 #define ARIZONA_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */
6006 #define ARIZONA_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */
6007 #define ARIZONA_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */
6008 #define ARIZONA_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */
6009 #define ARIZONA_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */
6010 #define ARIZONA_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */
6011 #define ARIZONA_EQ4_B1_MODE 0x0001 /* EQ4_B1_MODE */
6012 #define ARIZONA_EQ4_B1_MODE_MASK 0x0001 /* EQ4_B1_MODE */
6013 #define ARIZONA_EQ4_B1_MODE_SHIFT 0 /* EQ4_B1_MODE */
6014 #define ARIZONA_EQ4_B1_MODE_WIDTH 1 /* EQ4_B1_MODE */
6017 * R3668 (0xE54) - EQ4_3
6019 #define ARIZONA_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */
6020 #define ARIZONA_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */
6021 #define ARIZONA_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */
6024 * R3669 (0xE55) - EQ4_4
6026 #define ARIZONA_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */
6027 #define ARIZONA_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */
6028 #define ARIZONA_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */
6031 * R3670 (0xE56) - EQ4_5
6033 #define ARIZONA_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */
6034 #define ARIZONA_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */
6035 #define ARIZONA_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */
6038 * R3671 (0xE57) - EQ4_6
6040 #define ARIZONA_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */
6041 #define ARIZONA_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */
6042 #define ARIZONA_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */
6045 * R3672 (0xE58) - EQ4_7
6047 #define ARIZONA_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */
6048 #define ARIZONA_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */
6049 #define ARIZONA_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */
6052 * R3673 (0xE59) - EQ4_8
6054 #define ARIZONA_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */
6055 #define ARIZONA_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */
6056 #define ARIZONA_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */
6059 * R3674 (0xE5A) - EQ4_9
6061 #define ARIZONA_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */
6062 #define ARIZONA_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */
6063 #define ARIZONA_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */
6066 * R3675 (0xE5B) - EQ4_10
6068 #define ARIZONA_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */
6069 #define ARIZONA_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */
6070 #define ARIZONA_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */
6073 * R3676 (0xE5C) - EQ4_11
6075 #define ARIZONA_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */
6076 #define ARIZONA_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */
6077 #define ARIZONA_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */
6080 * R3677 (0xE5D) - EQ4_12
6082 #define ARIZONA_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */
6083 #define ARIZONA_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */
6084 #define ARIZONA_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */
6087 * R3678 (0xE5E) - EQ4_13
6089 #define ARIZONA_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */
6090 #define ARIZONA_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */
6091 #define ARIZONA_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */
6094 * R3679 (0xE5F) - EQ4_14
6096 #define ARIZONA_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */
6097 #define ARIZONA_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */
6098 #define ARIZONA_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */
6101 * R3680 (0xE60) - EQ4_15
6103 #define ARIZONA_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */
6104 #define ARIZONA_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */
6105 #define ARIZONA_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */
6108 * R3681 (0xE61) - EQ4_16
6110 #define ARIZONA_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */
6111 #define ARIZONA_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */
6112 #define ARIZONA_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */
6115 * R3682 (0xE62) - EQ4_17
6117 #define ARIZONA_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */
6118 #define ARIZONA_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */
6119 #define ARIZONA_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */
6122 * R3683 (0xE63) - EQ4_18
6124 #define ARIZONA_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */
6125 #define ARIZONA_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */
6126 #define ARIZONA_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */
6129 * R3684 (0xE64) - EQ4_19
6131 #define ARIZONA_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */
6132 #define ARIZONA_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */
6133 #define ARIZONA_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */
6136 * R3685 (0xE65) - EQ4_20
6138 #define ARIZONA_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */
6139 #define ARIZONA_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */
6140 #define ARIZONA_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */
6143 * R3686 (0xE66) - EQ4_21
6145 #define ARIZONA_EQ4_B1_C_MASK 0xFFFF /* EQ4_B1_C - [15:0] */
6146 #define ARIZONA_EQ4_B1_C_SHIFT 0 /* EQ4_B1_C - [15:0] */
6147 #define ARIZONA_EQ4_B1_C_WIDTH 16 /* EQ4_B1_C - [15:0] */
6150 * R3712 (0xE80) - DRC1 ctrl1
6152 #define ARIZONA_DRC1_SIG_DET_RMS_MASK 0xF800 /* DRC1_SIG_DET_RMS - [15:11] */
6153 #define ARIZONA_DRC1_SIG_DET_RMS_SHIFT 11 /* DRC1_SIG_DET_RMS - [15:11] */
6154 #define ARIZONA_DRC1_SIG_DET_RMS_WIDTH 5 /* DRC1_SIG_DET_RMS - [15:11] */
6155 #define ARIZONA_DRC1_SIG_DET_PK_MASK 0x0600 /* DRC1_SIG_DET_PK - [10:9] */
6156 #define ARIZONA_DRC1_SIG_DET_PK_SHIFT 9 /* DRC1_SIG_DET_PK - [10:9] */
6157 #define ARIZONA_DRC1_SIG_DET_PK_WIDTH 2 /* DRC1_SIG_DET_PK - [10:9] */
6158 #define ARIZONA_DRC1_NG_ENA 0x0100 /* DRC1_NG_ENA */
6159 #define ARIZONA_DRC1_NG_ENA_MASK 0x0100 /* DRC1_NG_ENA */
6160 #define ARIZONA_DRC1_NG_ENA_SHIFT 8 /* DRC1_NG_ENA */
6161 #define ARIZONA_DRC1_NG_ENA_WIDTH 1 /* DRC1_NG_ENA */
6162 #define ARIZONA_DRC1_SIG_DET_MODE 0x0080 /* DRC1_SIG_DET_MODE */
6163 #define ARIZONA_DRC1_SIG_DET_MODE_MASK 0x0080 /* DRC1_SIG_DET_MODE */
6164 #define ARIZONA_DRC1_SIG_DET_MODE_SHIFT 7 /* DRC1_SIG_DET_MODE */
6165 #define ARIZONA_DRC1_SIG_DET_MODE_WIDTH 1 /* DRC1_SIG_DET_MODE */
6166 #define ARIZONA_DRC1_SIG_DET 0x0040 /* DRC1_SIG_DET */
6167 #define ARIZONA_DRC1_SIG_DET_MASK 0x0040 /* DRC1_SIG_DET */
6168 #define ARIZONA_DRC1_SIG_DET_SHIFT 6 /* DRC1_SIG_DET */
6169 #define ARIZONA_DRC1_SIG_DET_WIDTH 1 /* DRC1_SIG_DET */
6170 #define ARIZONA_DRC1_KNEE2_OP_ENA 0x0020 /* DRC1_KNEE2_OP_ENA */
6171 #define ARIZONA_DRC1_KNEE2_OP_ENA_MASK 0x0020 /* DRC1_KNEE2_OP_ENA */
6172 #define ARIZONA_DRC1_KNEE2_OP_ENA_SHIFT 5 /* DRC1_KNEE2_OP_ENA */
6173 #define ARIZONA_DRC1_KNEE2_OP_ENA_WIDTH 1 /* DRC1_KNEE2_OP_ENA */
6174 #define ARIZONA_DRC1_QR 0x0010 /* DRC1_QR */
6175 #define ARIZONA_DRC1_QR_MASK 0x0010 /* DRC1_QR */
6176 #define ARIZONA_DRC1_QR_SHIFT 4 /* DRC1_QR */
6177 #define ARIZONA_DRC1_QR_WIDTH 1 /* DRC1_QR */
6178 #define ARIZONA_DRC1_ANTICLIP 0x0008 /* DRC1_ANTICLIP */
6179 #define ARIZONA_DRC1_ANTICLIP_MASK 0x0008 /* DRC1_ANTICLIP */
6180 #define ARIZONA_DRC1_ANTICLIP_SHIFT 3 /* DRC1_ANTICLIP */
6181 #define ARIZONA_DRC1_ANTICLIP_WIDTH 1 /* DRC1_ANTICLIP */
6182 #define ARIZONA_DRC1L_ENA 0x0002 /* DRC1L_ENA */
6183 #define ARIZONA_DRC1L_ENA_MASK 0x0002 /* DRC1L_ENA */
6184 #define ARIZONA_DRC1L_ENA_SHIFT 1 /* DRC1L_ENA */
6185 #define ARIZONA_DRC1L_ENA_WIDTH 1 /* DRC1L_ENA */
6186 #define ARIZONA_DRC1R_ENA 0x0001 /* DRC1R_ENA */
6187 #define ARIZONA_DRC1R_ENA_MASK 0x0001 /* DRC1R_ENA */
6188 #define ARIZONA_DRC1R_ENA_SHIFT 0 /* DRC1R_ENA */
6189 #define ARIZONA_DRC1R_ENA_WIDTH 1 /* DRC1R_ENA */
6192 * R3713 (0xE81) - DRC1 ctrl2
6194 #define ARIZONA_DRC1_ATK_MASK 0x1E00 /* DRC1_ATK - [12:9] */
6195 #define ARIZONA_DRC1_ATK_SHIFT 9 /* DRC1_ATK - [12:9] */
6196 #define ARIZONA_DRC1_ATK_WIDTH 4 /* DRC1_ATK - [12:9] */
6197 #define ARIZONA_DRC1_DCY_MASK 0x01E0 /* DRC1_DCY - [8:5] */
6198 #define ARIZONA_DRC1_DCY_SHIFT 5 /* DRC1_DCY - [8:5] */
6199 #define ARIZONA_DRC1_DCY_WIDTH 4 /* DRC1_DCY - [8:5] */
6200 #define ARIZONA_DRC1_MINGAIN_MASK 0x001C /* DRC1_MINGAIN - [4:2] */
6201 #define ARIZONA_DRC1_MINGAIN_SHIFT 2 /* DRC1_MINGAIN - [4:2] */
6202 #define ARIZONA_DRC1_MINGAIN_WIDTH 3 /* DRC1_MINGAIN - [4:2] */
6203 #define ARIZONA_DRC1_MAXGAIN_MASK 0x0003 /* DRC1_MAXGAIN - [1:0] */
6204 #define ARIZONA_DRC1_MAXGAIN_SHIFT 0 /* DRC1_MAXGAIN - [1:0] */
6205 #define ARIZONA_DRC1_MAXGAIN_WIDTH 2 /* DRC1_MAXGAIN - [1:0] */
6208 * R3714 (0xE82) - DRC1 ctrl3
6210 #define ARIZONA_DRC1_NG_MINGAIN_MASK 0xF000 /* DRC1_NG_MINGAIN - [15:12] */
6211 #define ARIZONA_DRC1_NG_MINGAIN_SHIFT 12 /* DRC1_NG_MINGAIN - [15:12] */
6212 #define ARIZONA_DRC1_NG_MINGAIN_WIDTH 4 /* DRC1_NG_MINGAIN - [15:12] */
6213 #define ARIZONA_DRC1_NG_EXP_MASK 0x0C00 /* DRC1_NG_EXP - [11:10] */
6214 #define ARIZONA_DRC1_NG_EXP_SHIFT 10 /* DRC1_NG_EXP - [11:10] */
6215 #define ARIZONA_DRC1_NG_EXP_WIDTH 2 /* DRC1_NG_EXP - [11:10] */
6216 #define ARIZONA_DRC1_QR_THR_MASK 0x0300 /* DRC1_QR_THR - [9:8] */
6217 #define ARIZONA_DRC1_QR_THR_SHIFT 8 /* DRC1_QR_THR - [9:8] */
6218 #define ARIZONA_DRC1_QR_THR_WIDTH 2 /* DRC1_QR_THR - [9:8] */
6219 #define ARIZONA_DRC1_QR_DCY_MASK 0x00C0 /* DRC1_QR_DCY - [7:6] */
6220 #define ARIZONA_DRC1_QR_DCY_SHIFT 6 /* DRC1_QR_DCY - [7:6] */
6221 #define ARIZONA_DRC1_QR_DCY_WIDTH 2 /* DRC1_QR_DCY - [7:6] */
6222 #define ARIZONA_DRC1_HI_COMP_MASK 0x0038 /* DRC1_HI_COMP - [5:3] */
6223 #define ARIZONA_DRC1_HI_COMP_SHIFT 3 /* DRC1_HI_COMP - [5:3] */
6224 #define ARIZONA_DRC1_HI_COMP_WIDTH 3 /* DRC1_HI_COMP - [5:3] */
6225 #define ARIZONA_DRC1_LO_COMP_MASK 0x0007 /* DRC1_LO_COMP - [2:0] */
6226 #define ARIZONA_DRC1_LO_COMP_SHIFT 0 /* DRC1_LO_COMP - [2:0] */
6227 #define ARIZONA_DRC1_LO_COMP_WIDTH 3 /* DRC1_LO_COMP - [2:0] */
6230 * R3715 (0xE83) - DRC1 ctrl4
6232 #define ARIZONA_DRC1_KNEE_IP_MASK 0x07E0 /* DRC1_KNEE_IP - [10:5] */
6233 #define ARIZONA_DRC1_KNEE_IP_SHIFT 5 /* DRC1_KNEE_IP - [10:5] */
6234 #define ARIZONA_DRC1_KNEE_IP_WIDTH 6 /* DRC1_KNEE_IP - [10:5] */
6235 #define ARIZONA_DRC1_KNEE_OP_MASK 0x001F /* DRC1_KNEE_OP - [4:0] */
6236 #define ARIZONA_DRC1_KNEE_OP_SHIFT 0 /* DRC1_KNEE_OP - [4:0] */
6237 #define ARIZONA_DRC1_KNEE_OP_WIDTH 5 /* DRC1_KNEE_OP - [4:0] */
6240 * R3716 (0xE84) - DRC1 ctrl5
6242 #define ARIZONA_DRC1_KNEE2_IP_MASK 0x03E0 /* DRC1_KNEE2_IP - [9:5] */
6243 #define ARIZONA_DRC1_KNEE2_IP_SHIFT 5 /* DRC1_KNEE2_IP - [9:5] */
6244 #define ARIZONA_DRC1_KNEE2_IP_WIDTH 5 /* DRC1_KNEE2_IP - [9:5] */
6245 #define ARIZONA_DRC1_KNEE2_OP_MASK 0x001F /* DRC1_KNEE2_OP - [4:0] */
6246 #define ARIZONA_DRC1_KNEE2_OP_SHIFT 0 /* DRC1_KNEE2_OP - [4:0] */
6247 #define ARIZONA_DRC1_KNEE2_OP_WIDTH 5 /* DRC1_KNEE2_OP - [4:0] */
6250 * R3721 (0xE89) - DRC2 ctrl1
6252 #define ARIZONA_DRC2_SIG_DET_RMS_MASK 0xF800 /* DRC2_SIG_DET_RMS - [15:11] */
6253 #define ARIZONA_DRC2_SIG_DET_RMS_SHIFT 11 /* DRC2_SIG_DET_RMS - [15:11] */
6254 #define ARIZONA_DRC2_SIG_DET_RMS_WIDTH 5 /* DRC2_SIG_DET_RMS - [15:11] */
6255 #define ARIZONA_DRC2_SIG_DET_PK_MASK 0x0600 /* DRC2_SIG_DET_PK - [10:9] */
6256 #define ARIZONA_DRC2_SIG_DET_PK_SHIFT 9 /* DRC2_SIG_DET_PK - [10:9] */
6257 #define ARIZONA_DRC2_SIG_DET_PK_WIDTH 2 /* DRC2_SIG_DET_PK - [10:9] */
6258 #define ARIZONA_DRC2_NG_ENA 0x0100 /* DRC2_NG_ENA */
6259 #define ARIZONA_DRC2_NG_ENA_MASK 0x0100 /* DRC2_NG_ENA */
6260 #define ARIZONA_DRC2_NG_ENA_SHIFT 8 /* DRC2_NG_ENA */
6261 #define ARIZONA_DRC2_NG_ENA_WIDTH 1 /* DRC2_NG_ENA */
6262 #define ARIZONA_DRC2_SIG_DET_MODE 0x0080 /* DRC2_SIG_DET_MODE */
6263 #define ARIZONA_DRC2_SIG_DET_MODE_MASK 0x0080 /* DRC2_SIG_DET_MODE */
6264 #define ARIZONA_DRC2_SIG_DET_MODE_SHIFT 7 /* DRC2_SIG_DET_MODE */
6265 #define ARIZONA_DRC2_SIG_DET_MODE_WIDTH 1 /* DRC2_SIG_DET_MODE */
6266 #define ARIZONA_DRC2_SIG_DET 0x0040 /* DRC2_SIG_DET */
6267 #define ARIZONA_DRC2_SIG_DET_MASK 0x0040 /* DRC2_SIG_DET */
6268 #define ARIZONA_DRC2_SIG_DET_SHIFT 6 /* DRC2_SIG_DET */
6269 #define ARIZONA_DRC2_SIG_DET_WIDTH 1 /* DRC2_SIG_DET */
6270 #define ARIZONA_DRC2_KNEE2_OP_ENA 0x0020 /* DRC2_KNEE2_OP_ENA */
6271 #define ARIZONA_DRC2_KNEE2_OP_ENA_MASK 0x0020 /* DRC2_KNEE2_OP_ENA */
6272 #define ARIZONA_DRC2_KNEE2_OP_ENA_SHIFT 5 /* DRC2_KNEE2_OP_ENA */
6273 #define ARIZONA_DRC2_KNEE2_OP_ENA_WIDTH 1 /* DRC2_KNEE2_OP_ENA */
6274 #define ARIZONA_DRC2_QR 0x0010 /* DRC2_QR */
6275 #define ARIZONA_DRC2_QR_MASK 0x0010 /* DRC2_QR */
6276 #define ARIZONA_DRC2_QR_SHIFT 4 /* DRC2_QR */
6277 #define ARIZONA_DRC2_QR_WIDTH 1 /* DRC2_QR */
6278 #define ARIZONA_DRC2_ANTICLIP 0x0008 /* DRC2_ANTICLIP */
6279 #define ARIZONA_DRC2_ANTICLIP_MASK 0x0008 /* DRC2_ANTICLIP */
6280 #define ARIZONA_DRC2_ANTICLIP_SHIFT 3 /* DRC2_ANTICLIP */
6281 #define ARIZONA_DRC2_ANTICLIP_WIDTH 1 /* DRC2_ANTICLIP */
6282 #define ARIZONA_DRC2L_ENA 0x0002 /* DRC2L_ENA */
6283 #define ARIZONA_DRC2L_ENA_MASK 0x0002 /* DRC2L_ENA */
6284 #define ARIZONA_DRC2L_ENA_SHIFT 1 /* DRC2L_ENA */
6285 #define ARIZONA_DRC2L_ENA_WIDTH 1 /* DRC2L_ENA */
6286 #define ARIZONA_DRC2R_ENA 0x0001 /* DRC2R_ENA */
6287 #define ARIZONA_DRC2R_ENA_MASK 0x0001 /* DRC2R_ENA */
6288 #define ARIZONA_DRC2R_ENA_SHIFT 0 /* DRC2R_ENA */
6289 #define ARIZONA_DRC2R_ENA_WIDTH 1 /* DRC2R_ENA */
6292 * R3722 (0xE8A) - DRC2 ctrl2
6294 #define ARIZONA_DRC2_ATK_MASK 0x1E00 /* DRC2_ATK - [12:9] */
6295 #define ARIZONA_DRC2_ATK_SHIFT 9 /* DRC2_ATK - [12:9] */
6296 #define ARIZONA_DRC2_ATK_WIDTH 4 /* DRC2_ATK - [12:9] */
6297 #define ARIZONA_DRC2_DCY_MASK 0x01E0 /* DRC2_DCY - [8:5] */
6298 #define ARIZONA_DRC2_DCY_SHIFT 5 /* DRC2_DCY - [8:5] */
6299 #define ARIZONA_DRC2_DCY_WIDTH 4 /* DRC2_DCY - [8:5] */
6300 #define ARIZONA_DRC2_MINGAIN_MASK 0x001C /* DRC2_MINGAIN - [4:2] */
6301 #define ARIZONA_DRC2_MINGAIN_SHIFT 2 /* DRC2_MINGAIN - [4:2] */
6302 #define ARIZONA_DRC2_MINGAIN_WIDTH 3 /* DRC2_MINGAIN - [4:2] */
6303 #define ARIZONA_DRC2_MAXGAIN_MASK 0x0003 /* DRC2_MAXGAIN - [1:0] */
6304 #define ARIZONA_DRC2_MAXGAIN_SHIFT 0 /* DRC2_MAXGAIN - [1:0] */
6305 #define ARIZONA_DRC2_MAXGAIN_WIDTH 2 /* DRC2_MAXGAIN - [1:0] */
6308 * R3723 (0xE8B) - DRC2 ctrl3
6310 #define ARIZONA_DRC2_NG_MINGAIN_MASK 0xF000 /* DRC2_NG_MINGAIN - [15:12] */
6311 #define ARIZONA_DRC2_NG_MINGAIN_SHIFT 12 /* DRC2_NG_MINGAIN - [15:12] */
6312 #define ARIZONA_DRC2_NG_MINGAIN_WIDTH 4 /* DRC2_NG_MINGAIN - [15:12] */
6313 #define ARIZONA_DRC2_NG_EXP_MASK 0x0C00 /* DRC2_NG_EXP - [11:10] */
6314 #define ARIZONA_DRC2_NG_EXP_SHIFT 10 /* DRC2_NG_EXP - [11:10] */
6315 #define ARIZONA_DRC2_NG_EXP_WIDTH 2 /* DRC2_NG_EXP - [11:10] */
6316 #define ARIZONA_DRC2_QR_THR_MASK 0x0300 /* DRC2_QR_THR - [9:8] */
6317 #define ARIZONA_DRC2_QR_THR_SHIFT 8 /* DRC2_QR_THR - [9:8] */
6318 #define ARIZONA_DRC2_QR_THR_WIDTH 2 /* DRC2_QR_THR - [9:8] */
6319 #define ARIZONA_DRC2_QR_DCY_MASK 0x00C0 /* DRC2_QR_DCY - [7:6] */
6320 #define ARIZONA_DRC2_QR_DCY_SHIFT 6 /* DRC2_QR_DCY - [7:6] */
6321 #define ARIZONA_DRC2_QR_DCY_WIDTH 2 /* DRC2_QR_DCY - [7:6] */
6322 #define ARIZONA_DRC2_HI_COMP_MASK 0x0038 /* DRC2_HI_COMP - [5:3] */
6323 #define ARIZONA_DRC2_HI_COMP_SHIFT 3 /* DRC2_HI_COMP - [5:3] */
6324 #define ARIZONA_DRC2_HI_COMP_WIDTH 3 /* DRC2_HI_COMP - [5:3] */
6325 #define ARIZONA_DRC2_LO_COMP_MASK 0x0007 /* DRC2_LO_COMP - [2:0] */
6326 #define ARIZONA_DRC2_LO_COMP_SHIFT 0 /* DRC2_LO_COMP - [2:0] */
6327 #define ARIZONA_DRC2_LO_COMP_WIDTH 3 /* DRC2_LO_COMP - [2:0] */
6330 * R3724 (0xE8C) - DRC2 ctrl4
6332 #define ARIZONA_DRC2_KNEE_IP_MASK 0x07E0 /* DRC2_KNEE_IP - [10:5] */
6333 #define ARIZONA_DRC2_KNEE_IP_SHIFT 5 /* DRC2_KNEE_IP - [10:5] */
6334 #define ARIZONA_DRC2_KNEE_IP_WIDTH 6 /* DRC2_KNEE_IP - [10:5] */
6335 #define ARIZONA_DRC2_KNEE_OP_MASK 0x001F /* DRC2_KNEE_OP - [4:0] */
6336 #define ARIZONA_DRC2_KNEE_OP_SHIFT 0 /* DRC2_KNEE_OP - [4:0] */
6337 #define ARIZONA_DRC2_KNEE_OP_WIDTH 5 /* DRC2_KNEE_OP - [4:0] */
6340 * R3725 (0xE8D) - DRC2 ctrl5
6342 #define ARIZONA_DRC2_KNEE2_IP_MASK 0x03E0 /* DRC2_KNEE2_IP - [9:5] */
6343 #define ARIZONA_DRC2_KNEE2_IP_SHIFT 5 /* DRC2_KNEE2_IP - [9:5] */
6344 #define ARIZONA_DRC2_KNEE2_IP_WIDTH 5 /* DRC2_KNEE2_IP - [9:5] */
6345 #define ARIZONA_DRC2_KNEE2_OP_MASK 0x001F /* DRC2_KNEE2_OP - [4:0] */
6346 #define ARIZONA_DRC2_KNEE2_OP_SHIFT 0 /* DRC2_KNEE2_OP - [4:0] */
6347 #define ARIZONA_DRC2_KNEE2_OP_WIDTH 5 /* DRC2_KNEE2_OP - [4:0] */
6350 * R3776 (0xEC0) - HPLPF1_1
6352 #define ARIZONA_LHPF1_MODE 0x0002 /* LHPF1_MODE */
6353 #define ARIZONA_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
6354 #define ARIZONA_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
6355 #define ARIZONA_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
6356 #define ARIZONA_LHPF1_ENA 0x0001 /* LHPF1_ENA */
6357 #define ARIZONA_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
6358 #define ARIZONA_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
6359 #define ARIZONA_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
6362 * R3777 (0xEC1) - HPLPF1_2
6364 #define ARIZONA_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
6365 #define ARIZONA_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
6366 #define ARIZONA_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
6369 * R3780 (0xEC4) - HPLPF2_1
6371 #define ARIZONA_LHPF2_MODE 0x0002 /* LHPF2_MODE */
6372 #define ARIZONA_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
6373 #define ARIZONA_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
6374 #define ARIZONA_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
6375 #define ARIZONA_LHPF2_ENA 0x0001 /* LHPF2_ENA */
6376 #define ARIZONA_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
6377 #define ARIZONA_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
6378 #define ARIZONA_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
6381 * R3781 (0xEC5) - HPLPF2_2
6383 #define ARIZONA_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
6384 #define ARIZONA_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
6385 #define ARIZONA_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
6388 * R3784 (0xEC8) - HPLPF3_1
6390 #define ARIZONA_LHPF3_MODE 0x0002 /* LHPF3_MODE */
6391 #define ARIZONA_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */
6392 #define ARIZONA_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */
6393 #define ARIZONA_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */
6394 #define ARIZONA_LHPF3_ENA 0x0001 /* LHPF3_ENA */
6395 #define ARIZONA_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */
6396 #define ARIZONA_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */
6397 #define ARIZONA_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */
6400 * R3785 (0xEC9) - HPLPF3_2
6402 #define ARIZONA_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */
6403 #define ARIZONA_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */
6404 #define ARIZONA_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */
6407 * R3788 (0xECC) - HPLPF4_1
6409 #define ARIZONA_LHPF4_MODE 0x0002 /* LHPF4_MODE */
6410 #define ARIZONA_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */
6411 #define ARIZONA_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */
6412 #define ARIZONA_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */
6413 #define ARIZONA_LHPF4_ENA 0x0001 /* LHPF4_ENA */
6414 #define ARIZONA_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */
6415 #define ARIZONA_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */
6416 #define ARIZONA_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */
6419 * R3789 (0xECD) - HPLPF4_2
6421 #define ARIZONA_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */
6422 #define ARIZONA_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
6423 #define ARIZONA_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
6426 * R3808 (0xEE0) - ASRC_ENABLE
6428 #define ARIZONA_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */
6429 #define ARIZONA_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */
6430 #define ARIZONA_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */
6431 #define ARIZONA_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */
6432 #define ARIZONA_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */
6433 #define ARIZONA_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */
6434 #define ARIZONA_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */
6435 #define ARIZONA_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */
6436 #define ARIZONA_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */
6437 #define ARIZONA_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */
6438 #define ARIZONA_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */
6439 #define ARIZONA_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */
6440 #define ARIZONA_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */
6441 #define ARIZONA_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */
6442 #define ARIZONA_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */
6443 #define ARIZONA_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */
6446 * R3810 (0xEE2) - ASRC_RATE1
6448 #define ARIZONA_ASRC_RATE1_MASK 0x7800 /* ASRC_RATE1 - [14:11] */
6449 #define ARIZONA_ASRC_RATE1_SHIFT 11 /* ASRC_RATE1 - [14:11] */
6450 #define ARIZONA_ASRC_RATE1_WIDTH 4 /* ASRC_RATE1 - [14:11] */
6453 * R3811 (0xEE3) - ASRC_RATE2
6455 #define ARIZONA_ASRC_RATE2_MASK 0x7800 /* ASRC_RATE2 - [14:11] */
6456 #define ARIZONA_ASRC_RATE2_SHIFT 11 /* ASRC_RATE2 - [14:11] */
6457 #define ARIZONA_ASRC_RATE2_WIDTH 4 /* ASRC_RATE2 - [14:11] */
6460 * R3824 (0xEF0) - ISRC 1 CTRL 1
6462 #define ARIZONA_ISRC1_FSH_MASK 0x7800 /* ISRC1_FSH - [14:11] */
6463 #define ARIZONA_ISRC1_FSH_SHIFT 11 /* ISRC1_FSH - [14:11] */
6464 #define ARIZONA_ISRC1_FSH_WIDTH 4 /* ISRC1_FSH - [14:11] */
6465 #define ARIZONA_ISRC1_CLK_SEL_MASK 0x0700 /* ISRC1_CLK_SEL - [10:8] */
6466 #define ARIZONA_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [10:8] */
6467 #define ARIZONA_ISRC1_CLK_SEL_WIDTH 3 /* ISRC1_CLK_SEL - [10:8] */
6470 * R3825 (0xEF1) - ISRC 1 CTRL 2
6472 #define ARIZONA_ISRC1_FSL_MASK 0x7800 /* ISRC1_FSL - [14:11] */
6473 #define ARIZONA_ISRC1_FSL_SHIFT 11 /* ISRC1_FSL - [14:11] */
6474 #define ARIZONA_ISRC1_FSL_WIDTH 4 /* ISRC1_FSL - [14:11] */
6477 * R3826 (0xEF2) - ISRC 1 CTRL 3
6479 #define ARIZONA_ISRC1_INT0_ENA 0x8000 /* ISRC1_INT0_ENA */
6480 #define ARIZONA_ISRC1_INT0_ENA_MASK 0x8000 /* ISRC1_INT0_ENA */
6481 #define ARIZONA_ISRC1_INT0_ENA_SHIFT 15 /* ISRC1_INT0_ENA */
6482 #define ARIZONA_ISRC1_INT0_ENA_WIDTH 1 /* ISRC1_INT0_ENA */
6483 #define ARIZONA_ISRC1_INT1_ENA 0x4000 /* ISRC1_INT1_ENA */
6484 #define ARIZONA_ISRC1_INT1_ENA_MASK 0x4000 /* ISRC1_INT1_ENA */
6485 #define ARIZONA_ISRC1_INT1_ENA_SHIFT 14 /* ISRC1_INT1_ENA */
6486 #define ARIZONA_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */
6487 #define ARIZONA_ISRC1_INT2_ENA 0x2000 /* ISRC1_INT2_ENA */
6488 #define ARIZONA_ISRC1_INT2_ENA_MASK 0x2000 /* ISRC1_INT2_ENA */
6489 #define ARIZONA_ISRC1_INT2_ENA_SHIFT 13 /* ISRC1_INT2_ENA */
6490 #define ARIZONA_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */
6491 #define ARIZONA_ISRC1_INT3_ENA 0x1000 /* ISRC1_INT3_ENA */
6492 #define ARIZONA_ISRC1_INT3_ENA_MASK 0x1000 /* ISRC1_INT3_ENA */
6493 #define ARIZONA_ISRC1_INT3_ENA_SHIFT 12 /* ISRC1_INT3_ENA */
6494 #define ARIZONA_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */
6495 #define ARIZONA_ISRC1_DEC0_ENA 0x0200 /* ISRC1_DEC0_ENA */
6496 #define ARIZONA_ISRC1_DEC0_ENA_MASK 0x0200 /* ISRC1_DEC0_ENA */
6497 #define ARIZONA_ISRC1_DEC0_ENA_SHIFT 9 /* ISRC1_DEC0_ENA */
6498 #define ARIZONA_ISRC1_DEC0_ENA_WIDTH 1 /* ISRC1_DEC0_ENA */
6499 #define ARIZONA_ISRC1_DEC1_ENA 0x0100 /* ISRC1_DEC1_ENA */
6500 #define ARIZONA_ISRC1_DEC1_ENA_MASK 0x0100 /* ISRC1_DEC1_ENA */
6501 #define ARIZONA_ISRC1_DEC1_ENA_SHIFT 8 /* ISRC1_DEC1_ENA */
6502 #define ARIZONA_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */
6503 #define ARIZONA_ISRC1_DEC2_ENA 0x0080 /* ISRC1_DEC2_ENA */
6504 #define ARIZONA_ISRC1_DEC2_ENA_MASK 0x0080 /* ISRC1_DEC2_ENA */
6505 #define ARIZONA_ISRC1_DEC2_ENA_SHIFT 7 /* ISRC1_DEC2_ENA */
6506 #define ARIZONA_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */
6507 #define ARIZONA_ISRC1_DEC3_ENA 0x0040 /* ISRC1_DEC3_ENA */
6508 #define ARIZONA_ISRC1_DEC3_ENA_MASK 0x0040 /* ISRC1_DEC3_ENA */
6509 #define ARIZONA_ISRC1_DEC3_ENA_SHIFT 6 /* ISRC1_DEC3_ENA */
6510 #define ARIZONA_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */
6511 #define ARIZONA_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */
6512 #define ARIZONA_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */
6513 #define ARIZONA_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */
6514 #define ARIZONA_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */
6517 * R3827 (0xEF3) - ISRC 2 CTRL 1
6519 #define ARIZONA_ISRC2_FSH_MASK 0x7800 /* ISRC2_FSH - [14:11] */
6520 #define ARIZONA_ISRC2_FSH_SHIFT 11 /* ISRC2_FSH - [14:11] */
6521 #define ARIZONA_ISRC2_FSH_WIDTH 4 /* ISRC2_FSH - [14:11] */
6522 #define ARIZONA_ISRC2_CLK_SEL_MASK 0x0700 /* ISRC2_CLK_SEL - [10:8] */
6523 #define ARIZONA_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [10:8] */
6524 #define ARIZONA_ISRC2_CLK_SEL_WIDTH 3 /* ISRC2_CLK_SEL - [10:8] */
6527 * R3828 (0xEF4) - ISRC 2 CTRL 2
6529 #define ARIZONA_ISRC2_FSL_MASK 0x7800 /* ISRC2_FSL - [14:11] */
6530 #define ARIZONA_ISRC2_FSL_SHIFT 11 /* ISRC2_FSL - [14:11] */
6531 #define ARIZONA_ISRC2_FSL_WIDTH 4 /* ISRC2_FSL - [14:11] */
6534 * R3829 (0xEF5) - ISRC 2 CTRL 3
6536 #define ARIZONA_ISRC2_INT0_ENA 0x8000 /* ISRC2_INT0_ENA */
6537 #define ARIZONA_ISRC2_INT0_ENA_MASK 0x8000 /* ISRC2_INT0_ENA */
6538 #define ARIZONA_ISRC2_INT0_ENA_SHIFT 15 /* ISRC2_INT0_ENA */
6539 #define ARIZONA_ISRC2_INT0_ENA_WIDTH 1 /* ISRC2_INT0_ENA */
6540 #define ARIZONA_ISRC2_INT1_ENA 0x4000 /* ISRC2_INT1_ENA */
6541 #define ARIZONA_ISRC2_INT1_ENA_MASK 0x4000 /* ISRC2_INT1_ENA */
6542 #define ARIZONA_ISRC2_INT1_ENA_SHIFT 14 /* ISRC2_INT1_ENA */
6543 #define ARIZONA_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */
6544 #define ARIZONA_ISRC2_INT2_ENA 0x2000 /* ISRC2_INT2_ENA */
6545 #define ARIZONA_ISRC2_INT2_ENA_MASK 0x2000 /* ISRC2_INT2_ENA */
6546 #define ARIZONA_ISRC2_INT2_ENA_SHIFT 13 /* ISRC2_INT2_ENA */
6547 #define ARIZONA_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */
6548 #define ARIZONA_ISRC2_INT3_ENA 0x1000 /* ISRC2_INT3_ENA */
6549 #define ARIZONA_ISRC2_INT3_ENA_MASK 0x1000 /* ISRC2_INT3_ENA */
6550 #define ARIZONA_ISRC2_INT3_ENA_SHIFT 12 /* ISRC2_INT3_ENA */
6551 #define ARIZONA_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */
6552 #define ARIZONA_ISRC2_DEC0_ENA 0x0200 /* ISRC2_DEC0_ENA */
6553 #define ARIZONA_ISRC2_DEC0_ENA_MASK 0x0200 /* ISRC2_DEC0_ENA */
6554 #define ARIZONA_ISRC2_DEC0_ENA_SHIFT 9 /* ISRC2_DEC0_ENA */
6555 #define ARIZONA_ISRC2_DEC0_ENA_WIDTH 1 /* ISRC2_DEC0_ENA */
6556 #define ARIZONA_ISRC2_DEC1_ENA 0x0100 /* ISRC2_DEC1_ENA */
6557 #define ARIZONA_ISRC2_DEC1_ENA_MASK 0x0100 /* ISRC2_DEC1_ENA */
6558 #define ARIZONA_ISRC2_DEC1_ENA_SHIFT 8 /* ISRC2_DEC1_ENA */
6559 #define ARIZONA_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */
6560 #define ARIZONA_ISRC2_DEC2_ENA 0x0080 /* ISRC2_DEC2_ENA */
6561 #define ARIZONA_ISRC2_DEC2_ENA_MASK 0x0080 /* ISRC2_DEC2_ENA */
6562 #define ARIZONA_ISRC2_DEC2_ENA_SHIFT 7 /* ISRC2_DEC2_ENA */
6563 #define ARIZONA_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */
6564 #define ARIZONA_ISRC2_DEC3_ENA 0x0040 /* ISRC2_DEC3_ENA */
6565 #define ARIZONA_ISRC2_DEC3_ENA_MASK 0x0040 /* ISRC2_DEC3_ENA */
6566 #define ARIZONA_ISRC2_DEC3_ENA_SHIFT 6 /* ISRC2_DEC3_ENA */
6567 #define ARIZONA_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */
6568 #define ARIZONA_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */
6569 #define ARIZONA_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */
6570 #define ARIZONA_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */
6571 #define ARIZONA_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */
6574 * R3830 (0xEF6) - ISRC 3 CTRL 1
6576 #define ARIZONA_ISRC3_FSH_MASK 0x7800 /* ISRC3_FSH - [14:11] */
6577 #define ARIZONA_ISRC3_FSH_SHIFT 11 /* ISRC3_FSH - [14:11] */
6578 #define ARIZONA_ISRC3_FSH_WIDTH 4 /* ISRC3_FSH - [14:11] */
6579 #define ARIZONA_ISRC3_CLK_SEL_MASK 0x0700 /* ISRC3_CLK_SEL - [10:8] */
6580 #define ARIZONA_ISRC3_CLK_SEL_SHIFT 8 /* ISRC3_CLK_SEL - [10:8] */
6581 #define ARIZONA_ISRC3_CLK_SEL_WIDTH 3 /* ISRC3_CLK_SEL - [10:8] */
6584 * R3831 (0xEF7) - ISRC 3 CTRL 2
6586 #define ARIZONA_ISRC3_FSL_MASK 0x7800 /* ISRC3_FSL - [14:11] */
6587 #define ARIZONA_ISRC3_FSL_SHIFT 11 /* ISRC3_FSL - [14:11] */
6588 #define ARIZONA_ISRC3_FSL_WIDTH 4 /* ISRC3_FSL - [14:11] */
6591 * R3832 (0xEF8) - ISRC 3 CTRL 3
6593 #define ARIZONA_ISRC3_INT0_ENA 0x8000 /* ISRC3_INT0_ENA */
6594 #define ARIZONA_ISRC3_INT0_ENA_MASK 0x8000 /* ISRC3_INT0_ENA */
6595 #define ARIZONA_ISRC3_INT0_ENA_SHIFT 15 /* ISRC3_INT0_ENA */
6596 #define ARIZONA_ISRC3_INT0_ENA_WIDTH 1 /* ISRC3_INT0_ENA */
6597 #define ARIZONA_ISRC3_INT1_ENA 0x4000 /* ISRC3_INT1_ENA */
6598 #define ARIZONA_ISRC3_INT1_ENA_MASK 0x4000 /* ISRC3_INT1_ENA */
6599 #define ARIZONA_ISRC3_INT1_ENA_SHIFT 14 /* ISRC3_INT1_ENA */
6600 #define ARIZONA_ISRC3_INT1_ENA_WIDTH 1 /* ISRC3_INT1_ENA */
6601 #define ARIZONA_ISRC3_INT2_ENA 0x2000 /* ISRC3_INT2_ENA */
6602 #define ARIZONA_ISRC3_INT2_ENA_MASK 0x2000 /* ISRC3_INT2_ENA */
6603 #define ARIZONA_ISRC3_INT2_ENA_SHIFT 13 /* ISRC3_INT2_ENA */
6604 #define ARIZONA_ISRC3_INT2_ENA_WIDTH 1 /* ISRC3_INT2_ENA */
6605 #define ARIZONA_ISRC3_INT3_ENA 0x1000 /* ISRC3_INT3_ENA */
6606 #define ARIZONA_ISRC3_INT3_ENA_MASK 0x1000 /* ISRC3_INT3_ENA */
6607 #define ARIZONA_ISRC3_INT3_ENA_SHIFT 12 /* ISRC3_INT3_ENA */
6608 #define ARIZONA_ISRC3_INT3_ENA_WIDTH 1 /* ISRC3_INT3_ENA */
6609 #define ARIZONA_ISRC3_DEC0_ENA 0x0200 /* ISRC3_DEC0_ENA */
6610 #define ARIZONA_ISRC3_DEC0_ENA_MASK 0x0200 /* ISRC3_DEC0_ENA */
6611 #define ARIZONA_ISRC3_DEC0_ENA_SHIFT 9 /* ISRC3_DEC0_ENA */
6612 #define ARIZONA_ISRC3_DEC0_ENA_WIDTH 1 /* ISRC3_DEC0_ENA */
6613 #define ARIZONA_ISRC3_DEC1_ENA 0x0100 /* ISRC3_DEC1_ENA */
6614 #define ARIZONA_ISRC3_DEC1_ENA_MASK 0x0100 /* ISRC3_DEC1_ENA */
6615 #define ARIZONA_ISRC3_DEC1_ENA_SHIFT 8 /* ISRC3_DEC1_ENA */
6616 #define ARIZONA_ISRC3_DEC1_ENA_WIDTH 1 /* ISRC3_DEC1_ENA */
6617 #define ARIZONA_ISRC3_DEC2_ENA 0x0080 /* ISRC3_DEC2_ENA */
6618 #define ARIZONA_ISRC3_DEC2_ENA_MASK 0x0080 /* ISRC3_DEC2_ENA */
6619 #define ARIZONA_ISRC3_DEC2_ENA_SHIFT 7 /* ISRC3_DEC2_ENA */
6620 #define ARIZONA_ISRC3_DEC2_ENA_WIDTH 1 /* ISRC3_DEC2_ENA */
6621 #define ARIZONA_ISRC3_DEC3_ENA 0x0040 /* ISRC3_DEC3_ENA */
6622 #define ARIZONA_ISRC3_DEC3_ENA_MASK 0x0040 /* ISRC3_DEC3_ENA */
6623 #define ARIZONA_ISRC3_DEC3_ENA_SHIFT 6 /* ISRC3_DEC3_ENA */
6624 #define ARIZONA_ISRC3_DEC3_ENA_WIDTH 1 /* ISRC3_DEC3_ENA */
6625 #define ARIZONA_ISRC3_NOTCH_ENA 0x0001 /* ISRC3_NOTCH_ENA */
6626 #define ARIZONA_ISRC3_NOTCH_ENA_MASK 0x0001 /* ISRC3_NOTCH_ENA */
6627 #define ARIZONA_ISRC3_NOTCH_ENA_SHIFT 0 /* ISRC3_NOTCH_ENA */
6628 #define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */
6631 * R4352 (0x1100) - DSP1 Control 1
6633 #define ARIZONA_DSP1_RATE_MASK 0x7800 /* DSP1_RATE - [14:11] */
6634 #define ARIZONA_DSP1_RATE_SHIFT 11 /* DSP1_RATE - [14:11] */
6635 #define ARIZONA_DSP1_RATE_WIDTH 4 /* DSP1_RATE - [14:11] */
6636 #define ARIZONA_DSP1_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
6637 #define ARIZONA_DSP1_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
6638 #define ARIZONA_DSP1_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
6639 #define ARIZONA_DSP1_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
6640 #define ARIZONA_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
6641 #define ARIZONA_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
6642 #define ARIZONA_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
6643 #define ARIZONA_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
6644 #define ARIZONA_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
6645 #define ARIZONA_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
6646 #define ARIZONA_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
6647 #define ARIZONA_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
6648 #define ARIZONA_DSP1_START 0x0001 /* DSP1_START */
6649 #define ARIZONA_DSP1_START_MASK 0x0001 /* DSP1_START */
6650 #define ARIZONA_DSP1_START_SHIFT 0 /* DSP1_START */
6651 #define ARIZONA_DSP1_START_WIDTH 1 /* DSP1_START */
6654 * R4353 (0x1101) - DSP1 Clocking 1
6656 #define ARIZONA_DSP1_CLK_SEL_MASK 0x0007 /* DSP1_CLK_SEL - [2:0] */
6657 #define ARIZONA_DSP1_CLK_SEL_SHIFT 0 /* DSP1_CLK_SEL - [2:0] */
6658 #define ARIZONA_DSP1_CLK_SEL_WIDTH 3 /* DSP1_CLK_SEL - [2:0] */
6661 * R4356 (0x1104) - DSP1 Status 1
6663 #define ARIZONA_DSP1_RAM_RDY 0x0001 /* DSP1_RAM_RDY */
6664 #define ARIZONA_DSP1_RAM_RDY_MASK 0x0001 /* DSP1_RAM_RDY */
6665 #define ARIZONA_DSP1_RAM_RDY_SHIFT 0 /* DSP1_RAM_RDY */
6666 #define ARIZONA_DSP1_RAM_RDY_WIDTH 1 /* DSP1_RAM_RDY */
6669 * R4357 (0x1105) - DSP1 Status 2
6671 #define ARIZONA_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */
6672 #define ARIZONA_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */
6673 #define ARIZONA_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */
6674 #define ARIZONA_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */
6675 #define ARIZONA_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */
6676 #define ARIZONA_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */
6677 #define ARIZONA_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */
6678 #define ARIZONA_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */
6679 #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
6680 #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
6681 #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */