2 * include/linux/irqchip/arm-gic.h
4 * Copyright (C) 2002 ARM Limited, All Rights Reserved.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef __LINUX_IRQCHIP_ARM_GIC_H
11 #define __LINUX_IRQCHIP_ARM_GIC_H
13 #define GIC_CPU_CTRL 0x00
14 #define GIC_CPU_PRIMASK 0x04
15 #define GIC_CPU_BINPOINT 0x08
16 #define GIC_CPU_INTACK 0x0c
17 #define GIC_CPU_EOI 0x10
18 #define GIC_CPU_RUNNINGPRI 0x14
19 #define GIC_CPU_HIGHPRI 0x18
20 #define GIC_CPU_ALIAS_BINPOINT 0x1c
21 #define GIC_CPU_ACTIVEPRIO 0xd0
22 #define GIC_CPU_IDENT 0xfc
24 #define GIC_DIST_CTRL 0x000
25 #define GIC_DIST_CTR 0x004
26 #define GIC_DIST_IGROUP 0x080
27 #define GIC_DIST_ENABLE_SET 0x100
28 #define GIC_DIST_ENABLE_CLEAR 0x180
29 #define GIC_DIST_PENDING_SET 0x200
30 #define GIC_DIST_PENDING_CLEAR 0x280
31 #define GIC_DIST_ACTIVE_SET 0x300
32 #define GIC_DIST_ACTIVE_CLEAR 0x380
33 #define GIC_DIST_PRI 0x400
34 #define GIC_DIST_TARGET 0x800
35 #define GIC_DIST_CONFIG 0xc00
36 #define GIC_DIST_SOFTINT 0xf00
37 #define GIC_DIST_SGI_PENDING_CLEAR 0xf10
38 #define GIC_DIST_SGI_PENDING_SET 0xf20
43 #define GICH_MISR 0x10
44 #define GICH_EISR0 0x20
45 #define GICH_EISR1 0x24
46 #define GICH_ELRSR0 0x30
47 #define GICH_ELRSR1 0x34
49 #define GICH_LR0 0x100
51 #define GICH_HCR_EN (1 << 0)
52 #define GICH_HCR_UIE (1 << 1)
54 #define GICH_LR_VIRTUALID (0x3ff << 0)
55 #define GICH_LR_PHYSID_CPUID_SHIFT (10)
56 #define GICH_LR_PHYSID_CPUID (7 << GICH_LR_PHYSID_CPUID_SHIFT)
57 #define GICH_LR_STATE (3 << 28)
58 #define GICH_LR_PENDING_BIT (1 << 28)
59 #define GICH_LR_ACTIVE_BIT (1 << 29)
60 #define GICH_LR_EOI (1 << 19)
62 #define GICH_VMCR_CTRL_SHIFT 0
63 #define GICH_VMCR_CTRL_MASK (0x21f << GICH_VMCR_CTRL_SHIFT)
64 #define GICH_VMCR_PRIMASK_SHIFT 27
65 #define GICH_VMCR_PRIMASK_MASK (0x1f << GICH_VMCR_PRIMASK_SHIFT)
66 #define GICH_VMCR_BINPOINT_SHIFT 21
67 #define GICH_VMCR_BINPOINT_MASK (0x7 << GICH_VMCR_BINPOINT_SHIFT)
68 #define GICH_VMCR_ALIAS_BINPOINT_SHIFT 18
69 #define GICH_VMCR_ALIAS_BINPOINT_MASK (0x7 << GICH_VMCR_ALIAS_BINPOINT_SHIFT)
71 #define GICH_MISR_EOI (1 << 0)
72 #define GICH_MISR_U (1 << 1)
78 extern struct irq_chip gic_arch_extn;
80 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
81 u32 offset, struct device_node *);
82 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
83 void gic_cpu_if_down(void);
85 static inline void gic_init(unsigned int nr, int start,
86 void __iomem *dist , void __iomem *cpu)
88 gic_init_bases(nr, start, dist, cpu, 0, NULL);
91 void gic_send_sgi(unsigned int cpu_id, unsigned int irq);
92 int gic_get_cpu_id(unsigned int cpu);
93 void gic_migrate_target(unsigned int new_cpu_id);
94 unsigned long gic_get_sgir_physaddr(void);
96 extern const struct irq_domain_ops *gic_routable_irq_domain_ops;
97 static inline void __init register_routable_domain_ops
98 (const struct irq_domain_ops *ops)
100 gic_routable_irq_domain_ops = ops;
102 #endif /* __ASSEMBLY */