include/linux/irqchip/arm-gic-v3.h

   1 /*
   2  * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved.
   3  * Author: Marc Zyngier <marc.zyngier@arm.com>
   4  *
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18 #ifndef __LINUX_IRQCHIP_ARM_GIC_V3_H
  19 #define __LINUX_IRQCHIP_ARM_GIC_V3_H
  20
  21 /*
  22  * Distributor registers. We assume we're running non-secure, with ARE
  23  * being set. Secure-only and non-ARE registers are not described.
  24  */
  25 #define GICD_CTLR                       0x0000
  26 #define GICD_TYPER                      0x0004
  27 #define GICD_IIDR                       0x0008
  28 #define GICD_STATUSR                    0x0010
  29 #define GICD_SETSPI_NSR                 0x0040
  30 #define GICD_CLRSPI_NSR                 0x0048
  31 #define GICD_SETSPI_SR                  0x0050
  32 #define GICD_CLRSPI_SR                  0x0058
  33 #define GICD_SEIR                       0x0068
  34 #define GICD_ISENABLER                  0x0100
  35 #define GICD_ICENABLER                  0x0180
  36 #define GICD_ISPENDR                    0x0200
  37 #define GICD_ICPENDR                    0x0280
  38 #define GICD_ISACTIVER                  0x0300
  39 #define GICD_ICACTIVER                  0x0380
  40 #define GICD_IPRIORITYR                 0x0400
  41 #define GICD_ICFGR                      0x0C00
  42 #define GICD_IROUTER                    0x6000
  43 #define GICD_PIDR2                      0xFFE8
  44
  45 #define GICD_CTLR_RWP                   (1U << 31)
  46 #define GICD_CTLR_ARE_NS                (1U << 4)
  47 #define GICD_CTLR_ENABLE_G1A            (1U << 1)
  48 #define GICD_CTLR_ENABLE_G1             (1U << 0)
  49
  50 #define GICD_IROUTER_SPI_MODE_ONE       (0U << 31)
  51 #define GICD_IROUTER_SPI_MODE_ANY       (1U << 31)
  52
  53 #define GIC_PIDR2_ARCH_MASK             0xf0
  54 #define GIC_PIDR2_ARCH_GICv3            0x30
  55 #define GIC_PIDR2_ARCH_GICv4            0x40
  56
  57 /*
  58  * Re-Distributor registers, offsets from RD_base
  59  */
  60 #define GICR_CTLR                       GICD_CTLR
  61 #define GICR_IIDR                       0x0004
  62 #define GICR_TYPER                      0x0008
  63 #define GICR_STATUSR                    GICD_STATUSR
  64 #define GICR_WAKER                      0x0014
  65 #define GICR_SETLPIR                    0x0040
  66 #define GICR_CLRLPIR                    0x0048
  67 #define GICR_SEIR                       GICD_SEIR
  68 #define GICR_PROPBASER                  0x0070
  69 #define GICR_PENDBASER                  0x0078
  70 #define GICR_INVLPIR                    0x00A0
  71 #define GICR_INVALLR                    0x00B0
  72 #define GICR_SYNCR                      0x00C0
  73 #define GICR_MOVLPIR                    0x0100
  74 #define GICR_MOVALLR                    0x0110
  75 #define GICR_PIDR2                      GICD_PIDR2
  76
  77 #define GICR_WAKER_ProcessorSleep       (1U << 1)
  78 #define GICR_WAKER_ChildrenAsleep       (1U << 2)
  79
  80 /*
  81  * Re-Distributor registers, offsets from SGI_base
  82  */
  83 #define GICR_ISENABLER0                 GICD_ISENABLER
  84 #define GICR_ICENABLER0                 GICD_ICENABLER
  85 #define GICR_ISPENDR0                   GICD_ISPENDR
  86 #define GICR_ICPENDR0                   GICD_ICPENDR
  87 #define GICR_ISACTIVER0                 GICD_ISACTIVER
  88 #define GICR_ICACTIVER0                 GICD_ICACTIVER
  89 #define GICR_IPRIORITYR0                GICD_IPRIORITYR
  90 #define GICR_ICFGR0                     GICD_ICFGR
  91
  92 #define GICR_TYPER_VLPIS                (1U << 1)
  93 #define GICR_TYPER_LAST                 (1U << 4)
  94
  95 /*
  96  * CPU interface registers
  97  */
  98 #define ICC_CTLR_EL1_EOImode_drop_dir   (0U << 1)
  99 #define ICC_CTLR_EL1_EOImode_drop       (1U << 1)
 100 #define ICC_SRE_EL1_SRE                 (1U << 0)
 101
 102 /*
 103  * Hypervisor interface registers (SRE only)
 104  */
 105 #define ICH_LR_VIRTUAL_ID_MASK          ((1UL << 32) - 1)
 106
 107 #define ICH_LR_EOI                      (1UL << 41)
 108 #define ICH_LR_GROUP                    (1UL << 60)
 109 #define ICH_LR_STATE                    (3UL << 62)
 110 #define ICH_LR_PENDING_BIT              (1UL << 62)
 111 #define ICH_LR_ACTIVE_BIT               (1UL << 63)
 112
 113 #define ICH_MISR_EOI                    (1 << 0)
 114 #define ICH_MISR_U                      (1 << 1)
 115
 116 #define ICH_HCR_EN                      (1 << 0)
 117 #define ICH_HCR_UIE                     (1 << 1)
 118
 119 #define ICH_VMCR_CTLR_SHIFT             0
 120 #define ICH_VMCR_CTLR_MASK              (0x21f << ICH_VMCR_CTLR_SHIFT)
 121 #define ICH_VMCR_BPR1_SHIFT             18
 122 #define ICH_VMCR_BPR1_MASK              (7 << ICH_VMCR_BPR1_SHIFT)
 123 #define ICH_VMCR_BPR0_SHIFT             21
 124 #define ICH_VMCR_BPR0_MASK              (7 << ICH_VMCR_BPR0_SHIFT)
 125 #define ICH_VMCR_PMR_SHIFT              24
 126 #define ICH_VMCR_PMR_MASK               (0xffUL << ICH_VMCR_PMR_SHIFT)
 127
 128 #define ICC_EOIR1_EL1                   S3_0_C12_C12_1
 129 #define ICC_IAR1_EL1                    S3_0_C12_C12_0
 130 #define ICC_SGI1R_EL1                   S3_0_C12_C11_5
 131 #define ICC_PMR_EL1                     S3_0_C4_C6_0
 132 #define ICC_CTLR_EL1                    S3_0_C12_C12_4
 133 #define ICC_SRE_EL1                     S3_0_C12_C12_5
 134 #define ICC_GRPEN1_EL1                  S3_0_C12_C12_7
 135
 136 #define ICC_IAR1_EL1_SPURIOUS           0x3ff
 137
 138 #define ICC_SRE_EL2                     S3_4_C12_C9_5
 139
 140 #define ICC_SRE_EL2_SRE                 (1 << 0)
 141 #define ICC_SRE_EL2_ENABLE              (1 << 3)
 142
 143 /*
 144  * System register definitions
 145  */
 146 #define ICH_VSEIR_EL2                   S3_4_C12_C9_4
 147 #define ICH_HCR_EL2                     S3_4_C12_C11_0
 148 #define ICH_VTR_EL2                     S3_4_C12_C11_1
 149 #define ICH_MISR_EL2                    S3_4_C12_C11_2
 150 #define ICH_EISR_EL2                    S3_4_C12_C11_3
 151 #define ICH_ELSR_EL2                    S3_4_C12_C11_5
 152 #define ICH_VMCR_EL2                    S3_4_C12_C11_7
 153
 154 #define __LR0_EL2(x)                    S3_4_C12_C12_ ## x
 155 #define __LR8_EL2(x)                    S3_4_C12_C13_ ## x
 156
 157 #define ICH_LR0_EL2                     __LR0_EL2(0)
 158 #define ICH_LR1_EL2                     __LR0_EL2(1)
 159 #define ICH_LR2_EL2                     __LR0_EL2(2)
 160 #define ICH_LR3_EL2                     __LR0_EL2(3)
 161 #define ICH_LR4_EL2                     __LR0_EL2(4)
 162 #define ICH_LR5_EL2                     __LR0_EL2(5)
 163 #define ICH_LR6_EL2                     __LR0_EL2(6)
 164 #define ICH_LR7_EL2                     __LR0_EL2(7)
 165 #define ICH_LR8_EL2                     __LR8_EL2(0)
 166 #define ICH_LR9_EL2                     __LR8_EL2(1)
 167 #define ICH_LR10_EL2                    __LR8_EL2(2)
 168 #define ICH_LR11_EL2                    __LR8_EL2(3)
 169 #define ICH_LR12_EL2                    __LR8_EL2(4)
 170 #define ICH_LR13_EL2                    __LR8_EL2(5)
 171 #define ICH_LR14_EL2                    __LR8_EL2(6)
 172 #define ICH_LR15_EL2                    __LR8_EL2(7)
 173
 174 #define __AP0Rx_EL2(x)                  S3_4_C12_C8_ ## x
 175 #define ICH_AP0R0_EL2                   __AP0Rx_EL2(0)
 176 #define ICH_AP0R1_EL2                   __AP0Rx_EL2(1)
 177 #define ICH_AP0R2_EL2                   __AP0Rx_EL2(2)
 178 #define ICH_AP0R3_EL2                   __AP0Rx_EL2(3)
 179
 180 #define __AP1Rx_EL2(x)                  S3_4_C12_C9_ ## x
 181 #define ICH_AP1R0_EL2                   __AP1Rx_EL2(0)
 182 #define ICH_AP1R1_EL2                   __AP1Rx_EL2(1)
 183 #define ICH_AP1R2_EL2                   __AP1Rx_EL2(2)
 184 #define ICH_AP1R3_EL2                   __AP1Rx_EL2(3)
 185
 186 #ifndef __ASSEMBLY__
 187
 188 #include <linux/stringify.h>
 189
 190 static inline void gic_write_eoir(u64 irq)
 191 {
 192         asm volatile("msr " __stringify(ICC_EOIR1_EL1) ", %0" : : "r" (irq));
 193         isb();
 194 }
 195
 196 #endif
 197
 198 #endif