2 * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the Free
6 * Software Foundation; either version 2 of the License, or (at your option)
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc., 59
16 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
18 * The full GNU General Public License is included in this distribution in the
19 * file called COPYING.
21 #ifndef LINUX_DMAENGINE_H
22 #define LINUX_DMAENGINE_H
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/uio.h>
27 #include <linux/bug.h>
28 #include <linux/scatterlist.h>
29 #include <linux/bitmap.h>
30 #include <linux/types.h>
34 * typedef dma_cookie_t - an opaque DMA cookie
36 * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
38 typedef s32 dma_cookie_t;
39 #define DMA_MIN_COOKIE 1
41 static inline int dma_submit_error(dma_cookie_t cookie)
43 return cookie < 0 ? cookie : 0;
47 * enum dma_status - DMA transaction status
48 * @DMA_COMPLETE: transaction completed
49 * @DMA_IN_PROGRESS: transaction not yet processed
50 * @DMA_PAUSED: transaction is paused
51 * @DMA_ERROR: transaction failed
61 * enum dma_transaction_type - DMA transaction types/indexes
63 * Note: The DMA_ASYNC_TX capability is not to be set by drivers. It is
64 * automatically set as dma devices are registered.
66 enum dma_transaction_type {
79 /* last transaction type for creation of the capabilities mask */
84 * enum dma_transfer_direction - dma transfer mode and direction indicator
85 * @DMA_MEM_TO_MEM: Async/Memcpy mode
86 * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
87 * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
88 * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
90 enum dma_transfer_direction {
99 * Interleaved Transfer Request
100 * ----------------------------
101 * A chunk is collection of contiguous bytes to be transfered.
102 * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
103 * ICGs may or maynot change between chunks.
104 * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
105 * that when repeated an integral number of times, specifies the transfer.
106 * A transfer template is specification of a Frame, the number of times
107 * it is to be repeated and other per-transfer attributes.
109 * Practically, a client driver would have ready a template for each
110 * type of transfer it is going to need during its lifetime and
111 * set only 'src_start' and 'dst_start' before submitting the requests.
114 * | Frame-1 | Frame-2 | ~ | Frame-'numf' |
115 * |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
122 * struct data_chunk - Element of scatter-gather list that makes a frame.
123 * @size: Number of bytes to read from source.
124 * size_dst := fn(op, size_src), so doesn't mean much for destination.
125 * @icg: Number of bytes to jump after last src/dst address of this
126 * chunk and before first src/dst address for next chunk.
127 * Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
128 * Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
136 * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
138 * @src_start: Bus address of source for the first chunk.
139 * @dst_start: Bus address of destination for the first chunk.
140 * @dir: Specifies the type of Source and Destination.
141 * @src_inc: If the source address increments after reading from it.
142 * @dst_inc: If the destination address increments after writing to it.
143 * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
144 * Otherwise, source is read contiguously (icg ignored).
145 * Ignored if src_inc is false.
146 * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
147 * Otherwise, destination is filled contiguously (icg ignored).
148 * Ignored if dst_inc is false.
149 * @numf: Number of frames in this template.
150 * @frame_size: Number of chunks in a frame i.e, size of sgl[].
151 * @sgl: Array of {chunk,icg} pairs that make up a frame.
153 struct dma_interleaved_template {
154 dma_addr_t src_start;
155 dma_addr_t dst_start;
156 enum dma_transfer_direction dir;
163 struct data_chunk sgl[0];
167 * enum dma_ctrl_flags - DMA flags to augment operation preparation,
168 * control completion, and communicate status.
169 * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
171 * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
172 * acknowledges receipt, i.e. has has a chance to establish any dependency
174 * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
175 * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
176 * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
177 * sources that were the result of a previous operation, in the case of a PQ
178 * operation it continues the calculation with new sources
179 * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
180 * on the result of this operation
182 enum dma_ctrl_flags {
183 DMA_PREP_INTERRUPT = (1 << 0),
184 DMA_CTRL_ACK = (1 << 1),
185 DMA_PREP_PQ_DISABLE_P = (1 << 2),
186 DMA_PREP_PQ_DISABLE_Q = (1 << 3),
187 DMA_PREP_CONTINUE = (1 << 4),
188 DMA_PREP_FENCE = (1 << 5),
192 * enum sum_check_bits - bit position of pq_check_flags
194 enum sum_check_bits {
200 * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
201 * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
202 * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
204 enum sum_check_flags {
205 SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
206 SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
211 * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
212 * See linux/cpumask.h
214 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
217 * struct dma_chan_percpu - the per-CPU part of struct dma_chan
218 * @memcpy_count: transaction counter
219 * @bytes_transferred: byte counter
222 struct dma_chan_percpu {
224 unsigned long memcpy_count;
225 unsigned long bytes_transferred;
229 * struct dma_chan - devices supply DMA channels, clients use them
230 * @device: ptr to the dma device who supplies this channel, always !%NULL
231 * @cookie: last cookie value returned to client
232 * @completed_cookie: last completed cookie for this channel
233 * @chan_id: channel ID for sysfs
234 * @dev: class device for sysfs
235 * @device_node: used to add this to the device chan list
236 * @local: per-cpu pointer to a struct dma_chan_percpu
237 * @client_count: how many clients are using this channel
238 * @table_count: number of appearances in the mem-to-mem allocation table
239 * @private: private data for certain client-channel associations
242 struct dma_device *device;
244 dma_cookie_t completed_cookie;
248 struct dma_chan_dev *dev;
250 struct list_head device_node;
251 struct dma_chan_percpu __percpu *local;
258 * struct dma_chan_dev - relate sysfs device node to backing channel device
259 * @chan: driver channel device
260 * @device: sysfs device
261 * @dev_id: parent dma_device dev_id
262 * @idr_ref: reference count to gate release of dma_device dev_id
264 struct dma_chan_dev {
265 struct dma_chan *chan;
266 struct device device;
272 * enum dma_slave_buswidth - defines bus width of the DMA slave
273 * device, source or target buses
275 enum dma_slave_buswidth {
276 DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
277 DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
278 DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
279 DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
280 DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
281 DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
285 * struct dma_slave_config - dma slave channel runtime config
286 * @direction: whether the data shall go in or out on this slave
287 * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
288 * legal values. DEPRECATED, drivers should use the direction argument
289 * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
290 * the dir field in the dma_interleaved_template structure.
291 * @src_addr: this is the physical address where DMA slave data
292 * should be read (RX), if the source is memory this argument is
294 * @dst_addr: this is the physical address where DMA slave data
295 * should be written (TX), if the source is memory this argument
297 * @src_addr_width: this is the width in bytes of the source (RX)
298 * register where DMA data shall be read. If the source
299 * is memory this may be ignored depending on architecture.
300 * Legal values: 1, 2, 4, 8.
301 * @dst_addr_width: same as src_addr_width but for destination
302 * target (TX) mutatis mutandis.
303 * @src_maxburst: the maximum number of words (note: words, as in
304 * units of the src_addr_width member, not bytes) that can be sent
305 * in one burst to the device. Typically something like half the
306 * FIFO depth on I/O peripherals so you don't overflow it. This
307 * may or may not be applicable on memory sources.
308 * @dst_maxburst: same as src_maxburst but for destination target
310 * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
311 * with 'true' if peripheral should be flow controller. Direction will be
312 * selected at Runtime.
313 * @slave_id: Slave requester id. Only valid for slave channels. The dma
314 * slave peripheral will have unique id as dma requester which need to be
315 * pass as slave config.
317 * This struct is passed in as configuration data to a DMA engine
318 * in order to set up a certain channel for DMA transport at runtime.
319 * The DMA device/engine has to provide support for an additional
320 * callback in the dma_device structure, device_config and this struct
321 * will then be passed in as an argument to the function.
323 * The rationale for adding configuration information to this struct is as
324 * follows: if it is likely that more than one DMA slave controllers in
325 * the world will support the configuration option, then make it generic.
326 * If not: if it is fixed so that it be sent in static from the platform
327 * data, then prefer to do that.
329 struct dma_slave_config {
330 enum dma_transfer_direction direction;
333 enum dma_slave_buswidth src_addr_width;
334 enum dma_slave_buswidth dst_addr_width;
338 unsigned int slave_id;
342 * enum dma_residue_granularity - Granularity of the reported transfer residue
343 * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
344 * DMA channel is only able to tell whether a descriptor has been completed or
345 * not, which means residue reporting is not supported by this channel. The
346 * residue field of the dma_tx_state field will always be 0.
347 * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
348 * completed segment of the transfer (For cyclic transfers this is after each
349 * period). This is typically implemented by having the hardware generate an
350 * interrupt after each transferred segment and then the drivers updates the
351 * outstanding residue by the size of the segment. Another possibility is if
352 * the hardware supports scatter-gather and the segment descriptor has a field
353 * which gets set after the segment has been completed. The driver then counts
354 * the number of segments without the flag set to compute the residue.
355 * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
356 * burst. This is typically only supported if the hardware has a progress
357 * register of some sort (E.g. a register with the current read/write address
358 * or a register with the amount of bursts/beats/bytes that have been
359 * transferred or still need to be transferred).
361 enum dma_residue_granularity {
362 DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
363 DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
364 DMA_RESIDUE_GRANULARITY_BURST = 2,
367 /* struct dma_slave_caps - expose capabilities of a slave channel only
369 * @src_addr_widths: bit mask of src addr widths the channel supports
370 * @dst_addr_widths: bit mask of dstn addr widths the channel supports
371 * @directions: bit mask of slave direction the channel supported
372 * since the enum dma_transfer_direction is not defined as bits for each
373 * type of direction, the dma controller should fill (1 << <TYPE>) and same
374 * should be checked by controller as well
375 * @cmd_pause: true, if pause and thereby resume is supported
376 * @cmd_terminate: true, if terminate cmd is supported
377 * @residue_granularity: granularity of the reported transfer residue
379 struct dma_slave_caps {
385 enum dma_residue_granularity residue_granularity;
388 static inline const char *dma_chan_name(struct dma_chan *chan)
390 return dev_name(&chan->dev->device);
393 void dma_chan_cleanup(struct kref *kref);
396 * typedef dma_filter_fn - callback filter for dma_request_channel
397 * @chan: channel to be reviewed
398 * @filter_param: opaque parameter passed through dma_request_channel
400 * When this optional parameter is specified in a call to dma_request_channel a
401 * suitable channel is passed to this routine for further dispositioning before
402 * being returned. Where 'suitable' indicates a non-busy channel that
403 * satisfies the given capability mask. It returns 'true' to indicate that the
404 * channel is suitable.
406 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
408 typedef void (*dma_async_tx_callback)(void *dma_async_param);
410 struct dmaengine_unmap_data {
422 * struct dma_async_tx_descriptor - async transaction descriptor
423 * ---dma generic offload fields---
424 * @cookie: tracking cookie for this transaction, set to -EBUSY if
425 * this tx is sitting on a dependency list
426 * @flags: flags to augment operation preparation, control completion, and
428 * @phys: physical address of the descriptor
429 * @chan: target channel for this operation
430 * @tx_submit: accept the descriptor, assign ordered cookie and mark the
431 * descriptor pending. To be pushed on .issue_pending() call
432 * @callback: routine to call after this operation is complete
433 * @callback_param: general parameter to pass to the callback routine
434 * ---async_tx api specific fields---
435 * @next: at completion submit this descriptor
436 * @parent: pointer to the next level up in the dependency chain
437 * @lock: protect the parent and next pointers
439 struct dma_async_tx_descriptor {
441 enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
443 struct dma_chan *chan;
444 dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
445 dma_async_tx_callback callback;
446 void *callback_param;
447 struct dmaengine_unmap_data *unmap;
448 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
449 struct dma_async_tx_descriptor *next;
450 struct dma_async_tx_descriptor *parent;
455 #ifdef CONFIG_DMA_ENGINE
456 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
457 struct dmaengine_unmap_data *unmap)
459 kref_get(&unmap->kref);
463 struct dmaengine_unmap_data *
464 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
465 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
467 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
468 struct dmaengine_unmap_data *unmap)
471 static inline struct dmaengine_unmap_data *
472 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
476 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
481 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
484 dmaengine_unmap_put(tx->unmap);
489 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
490 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
493 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
496 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
500 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
503 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
506 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
510 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
516 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
518 spin_lock_bh(&txd->lock);
520 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
522 spin_unlock_bh(&txd->lock);
524 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
529 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
533 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
537 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
541 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
548 * struct dma_tx_state - filled in to report the status of
550 * @last: last completed DMA cookie
551 * @used: last issued DMA cookie (i.e. the one in progress)
552 * @residue: the remaining number of bytes left to transmit
553 * on the selected transfer for states DMA_IN_PROGRESS and
554 * DMA_PAUSED if this is implemented in the driver, else 0
556 struct dma_tx_state {
563 * struct dma_device - info on the entity supplying DMA services
564 * @chancnt: how many DMA channels are supported
565 * @privatecnt: how many DMA channels are requested by dma_request_channel
566 * @channels: the list of struct dma_chan
567 * @global_node: list_head for global dma_device_list
568 * @cap_mask: one or more dma_capability flags
569 * @max_xor: maximum number of xor sources, 0 if no capability
570 * @max_pq: maximum number of PQ sources and PQ-continue capability
571 * @copy_align: alignment shift for memcpy operations
572 * @xor_align: alignment shift for xor operations
573 * @pq_align: alignment shift for pq operations
574 * @fill_align: alignment shift for memset operations
575 * @dev_id: unique device ID
576 * @dev: struct device reference for dma mapping api
577 * @src_addr_widths: bit mask of src addr widths the device supports
578 * @dst_addr_widths: bit mask of dst addr widths the device supports
579 * @directions: bit mask of slave direction the device supports since
580 * the enum dma_transfer_direction is not defined as bits for
581 * each type of direction, the dma controller should fill (1 <<
582 * <TYPE>) and same should be checked by controller as well
583 * @residue_granularity: granularity of the transfer residue reported
585 * @device_alloc_chan_resources: allocate resources and return the
586 * number of allocated descriptors
587 * @device_free_chan_resources: release DMA channel's resources
588 * @device_prep_dma_memcpy: prepares a memcpy operation
589 * @device_prep_dma_xor: prepares a xor operation
590 * @device_prep_dma_xor_val: prepares a xor validation operation
591 * @device_prep_dma_pq: prepares a pq operation
592 * @device_prep_dma_pq_val: prepares a pqzero_sum operation
593 * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
594 * @device_prep_slave_sg: prepares a slave dma operation
595 * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
596 * The function takes a buffer of size buf_len. The callback function will
597 * be called after period_len bytes have been transferred.
598 * @device_prep_interleaved_dma: Transfer expression in a generic way.
599 * @device_config: Pushes a new configuration to a channel, return 0 or an error
601 * @device_pause: Pauses any transfer happening on a channel. Returns
603 * @device_resume: Resumes any transfer on a channel previously
604 * paused. Returns 0 or an error code
605 * @device_terminate_all: Aborts all transfers on a channel. Returns 0
607 * @device_tx_status: poll for transaction completion, the optional
608 * txstate parameter can be supplied with a pointer to get a
609 * struct with auxiliary transfer status information, otherwise the call
610 * will just return a simple status code
611 * @device_issue_pending: push pending transactions to hardware
615 unsigned int chancnt;
616 unsigned int privatecnt;
617 struct list_head channels;
618 struct list_head global_node;
619 dma_cap_mask_t cap_mask;
620 unsigned short max_xor;
621 unsigned short max_pq;
626 #define DMA_HAS_PQ_CONTINUE (1 << 15)
634 enum dma_residue_granularity residue_granularity;
636 int (*device_alloc_chan_resources)(struct dma_chan *chan);
637 void (*device_free_chan_resources)(struct dma_chan *chan);
639 struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
640 struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
641 size_t len, unsigned long flags);
642 struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
643 struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
644 unsigned int src_cnt, size_t len, unsigned long flags);
645 struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
646 struct dma_chan *chan, dma_addr_t *src, unsigned int src_cnt,
647 size_t len, enum sum_check_flags *result, unsigned long flags);
648 struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
649 struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
650 unsigned int src_cnt, const unsigned char *scf,
651 size_t len, unsigned long flags);
652 struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
653 struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
654 unsigned int src_cnt, const unsigned char *scf, size_t len,
655 enum sum_check_flags *pqres, unsigned long flags);
656 struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
657 struct dma_chan *chan, unsigned long flags);
658 struct dma_async_tx_descriptor *(*device_prep_dma_sg)(
659 struct dma_chan *chan,
660 struct scatterlist *dst_sg, unsigned int dst_nents,
661 struct scatterlist *src_sg, unsigned int src_nents,
662 unsigned long flags);
664 struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
665 struct dma_chan *chan, struct scatterlist *sgl,
666 unsigned int sg_len, enum dma_transfer_direction direction,
667 unsigned long flags, void *context);
668 struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
669 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
670 size_t period_len, enum dma_transfer_direction direction,
671 unsigned long flags);
672 struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
673 struct dma_chan *chan, struct dma_interleaved_template *xt,
674 unsigned long flags);
676 int (*device_config)(struct dma_chan *chan,
677 struct dma_slave_config *config);
678 int (*device_pause)(struct dma_chan *chan);
679 int (*device_resume)(struct dma_chan *chan);
680 int (*device_terminate_all)(struct dma_chan *chan);
682 enum dma_status (*device_tx_status)(struct dma_chan *chan,
684 struct dma_tx_state *txstate);
685 void (*device_issue_pending)(struct dma_chan *chan);
688 static inline int dmaengine_slave_config(struct dma_chan *chan,
689 struct dma_slave_config *config)
691 if (chan->device->device_config)
692 return chan->device->device_config(chan, config);
697 static inline bool is_slave_direction(enum dma_transfer_direction direction)
699 return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
702 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
703 struct dma_chan *chan, dma_addr_t buf, size_t len,
704 enum dma_transfer_direction dir, unsigned long flags)
706 struct scatterlist sg;
707 sg_init_table(&sg, 1);
708 sg_dma_address(&sg) = buf;
709 sg_dma_len(&sg) = len;
711 return chan->device->device_prep_slave_sg(chan, &sg, 1,
715 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
716 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
717 enum dma_transfer_direction dir, unsigned long flags)
719 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
723 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
725 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
726 struct dma_chan *chan, struct scatterlist *sgl, unsigned int sg_len,
727 enum dma_transfer_direction dir, unsigned long flags,
728 struct rio_dma_ext *rio_ext)
730 return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
731 dir, flags, rio_ext);
735 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
736 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
737 size_t period_len, enum dma_transfer_direction dir,
740 return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
741 period_len, dir, flags);
744 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
745 struct dma_chan *chan, struct dma_interleaved_template *xt,
748 return chan->device->device_prep_interleaved_dma(chan, xt, flags);
751 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_sg(
752 struct dma_chan *chan,
753 struct scatterlist *dst_sg, unsigned int dst_nents,
754 struct scatterlist *src_sg, unsigned int src_nents,
757 return chan->device->device_prep_dma_sg(chan, dst_sg, dst_nents,
758 src_sg, src_nents, flags);
761 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
763 static inline int dmaengine_terminate_all(struct dma_chan *chan)
765 if (chan->device->device_terminate_all)
766 return chan->device->device_terminate_all(chan);
771 static inline int dmaengine_pause(struct dma_chan *chan)
773 if (chan->device->device_pause)
774 return chan->device->device_pause(chan);
779 static inline int dmaengine_resume(struct dma_chan *chan)
781 if (chan->device->device_resume)
782 return chan->device->device_resume(chan);
787 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
788 dma_cookie_t cookie, struct dma_tx_state *state)
790 return chan->device->device_tx_status(chan, cookie, state);
793 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
795 return desc->tx_submit(desc);
798 static inline bool dmaengine_check_align(u8 align, size_t off1, size_t off2, size_t len)
804 mask = (1 << align) - 1;
805 if (mask & (off1 | off2 | len))
810 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
811 size_t off2, size_t len)
813 return dmaengine_check_align(dev->copy_align, off1, off2, len);
816 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
817 size_t off2, size_t len)
819 return dmaengine_check_align(dev->xor_align, off1, off2, len);
822 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
823 size_t off2, size_t len)
825 return dmaengine_check_align(dev->pq_align, off1, off2, len);
828 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
829 size_t off2, size_t len)
831 return dmaengine_check_align(dev->fill_align, off1, off2, len);
835 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
839 dma->max_pq |= DMA_HAS_PQ_CONTINUE;
842 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
844 return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
847 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
849 enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
851 return (flags & mask) == mask;
854 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
856 return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
859 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
861 return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
864 /* dma_maxpq - reduce maxpq in the face of continued operations
865 * @dma - dma device with PQ capability
866 * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
868 * When an engine does not support native continuation we need 3 extra
869 * source slots to reuse P and Q with the following coefficients:
870 * 1/ {00} * P : remove P from Q', but use it as a source for P'
871 * 2/ {01} * Q : use Q to continue Q' calculation
872 * 3/ {00} * Q : subtract Q from P' to cancel (2)
874 * In the case where P is disabled we only need 1 extra source:
875 * 1/ {01} * Q : use Q to continue Q' calculation
877 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
879 if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
880 return dma_dev_to_maxpq(dma);
881 else if (dmaf_p_disabled_continue(flags))
882 return dma_dev_to_maxpq(dma) - 1;
883 else if (dmaf_continue(flags))
884 return dma_dev_to_maxpq(dma) - 3;
888 /* --- public DMA engine API --- */
890 #ifdef CONFIG_DMA_ENGINE
891 void dmaengine_get(void);
892 void dmaengine_put(void);
894 static inline void dmaengine_get(void)
897 static inline void dmaengine_put(void)
902 #ifdef CONFIG_ASYNC_TX_DMA
903 #define async_dmaengine_get() dmaengine_get()
904 #define async_dmaengine_put() dmaengine_put()
905 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
906 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
908 #define async_dma_find_channel(type) dma_find_channel(type)
909 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
911 static inline void async_dmaengine_get(void)
914 static inline void async_dmaengine_put(void)
917 static inline struct dma_chan *
918 async_dma_find_channel(enum dma_transaction_type type)
922 #endif /* CONFIG_ASYNC_TX_DMA */
923 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
924 struct dma_chan *chan);
926 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
928 tx->flags |= DMA_CTRL_ACK;
931 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
933 tx->flags &= ~DMA_CTRL_ACK;
936 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
938 return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
941 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
943 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
945 set_bit(tx_type, dstp->bits);
948 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
950 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
952 clear_bit(tx_type, dstp->bits);
955 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
956 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
958 bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
961 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
963 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
965 return test_bit(tx_type, srcp->bits);
968 #define for_each_dma_cap_mask(cap, mask) \
969 for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
972 * dma_async_issue_pending - flush pending transactions to HW
973 * @chan: target DMA channel
975 * This allows drivers to push copies to HW in batches,
976 * reducing MMIO writes where possible.
978 static inline void dma_async_issue_pending(struct dma_chan *chan)
980 chan->device->device_issue_pending(chan);
984 * dma_async_is_tx_complete - poll for transaction completion
986 * @cookie: transaction identifier to check status of
987 * @last: returns last completed cookie, can be NULL
988 * @used: returns last issued cookie, can be NULL
990 * If @last and @used are passed in, upon return they reflect the driver
991 * internal state and can be used with dma_async_is_complete() to check
992 * the status of multiple cookies without re-checking hardware state.
994 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
995 dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
997 struct dma_tx_state state;
998 enum dma_status status;
1000 status = chan->device->device_tx_status(chan, cookie, &state);
1009 * dma_async_is_complete - test a cookie against chan state
1010 * @cookie: transaction identifier to test status of
1011 * @last_complete: last know completed transaction
1012 * @last_used: last cookie value handed out
1014 * dma_async_is_complete() is used in dma_async_is_tx_complete()
1015 * the test logic is separated for lightweight testing of multiple cookies
1017 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1018 dma_cookie_t last_complete, dma_cookie_t last_used)
1020 if (last_complete <= last_used) {
1021 if ((cookie <= last_complete) || (cookie > last_used))
1022 return DMA_COMPLETE;
1024 if ((cookie <= last_complete) && (cookie > last_used))
1025 return DMA_COMPLETE;
1027 return DMA_IN_PROGRESS;
1031 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1036 st->residue = residue;
1040 #ifdef CONFIG_DMA_ENGINE
1041 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1042 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1043 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1044 void dma_issue_pending_all(void);
1045 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1046 dma_filter_fn fn, void *fn_param);
1047 struct dma_chan *dma_request_slave_channel_reason(struct device *dev,
1049 struct dma_chan *dma_request_slave_channel(struct device *dev, const char *name);
1050 void dma_release_channel(struct dma_chan *chan);
1052 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1056 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1058 return DMA_COMPLETE;
1060 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1062 return DMA_COMPLETE;
1064 static inline void dma_issue_pending_all(void)
1067 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1068 dma_filter_fn fn, void *fn_param)
1072 static inline struct dma_chan *dma_request_slave_channel_reason(
1073 struct device *dev, const char *name)
1075 return ERR_PTR(-ENODEV);
1077 static inline struct dma_chan *dma_request_slave_channel(struct device *dev,
1082 static inline void dma_release_channel(struct dma_chan *chan)
1087 /* --- DMA device --- */
1089 int dma_async_device_register(struct dma_device *device);
1090 void dma_async_device_unregister(struct dma_device *device);
1091 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1092 struct dma_chan *dma_get_slave_channel(struct dma_chan *chan);
1093 struct dma_chan *dma_get_any_slave_channel(struct dma_device *device);
1094 struct dma_chan *net_dma_find_channel(void);
1095 #define dma_request_channel(mask, x, y) __dma_request_channel(&(mask), x, y)
1096 #define dma_request_slave_channel_compat(mask, x, y, dev, name) \
1097 __dma_request_slave_channel_compat(&(mask), x, y, dev, name)
1099 static inline struct dma_chan
1100 *__dma_request_slave_channel_compat(const dma_cap_mask_t *mask,
1101 dma_filter_fn fn, void *fn_param,
1102 struct device *dev, char *name)
1104 struct dma_chan *chan;
1106 chan = dma_request_slave_channel(dev, name);
1110 return __dma_request_channel(mask, fn, fn_param);
1113 /* --- Helper iov-locking functions --- */
1115 struct dma_page_list {
1116 char __user *base_address;
1118 struct page **pages;
1121 struct dma_pinned_list {
1123 struct dma_page_list page_list[0];
1126 struct dma_pinned_list *dma_pin_iovec_pages(struct iovec *iov, size_t len);
1127 void dma_unpin_iovec_pages(struct dma_pinned_list* pinned_list);
1129 dma_cookie_t dma_memcpy_to_iovec(struct dma_chan *chan, struct iovec *iov,
1130 struct dma_pinned_list *pinned_list, unsigned char *kdata, size_t len);
1131 dma_cookie_t dma_memcpy_pg_to_iovec(struct dma_chan *chan, struct iovec *iov,
1132 struct dma_pinned_list *pinned_list, struct page *page,
1133 unsigned int offset, size_t len);
1135 #endif /* DMAENGINE_H */