2 * linux/include/linux/clk-provider.h
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
14 #include <linux/clk.h>
16 #ifdef CONFIG_COMMON_CLK
19 * flags used across common struct clk. these flags should only affect the
20 * top-level framework. custom flags for dealing with hardware specifics
21 * belong in struct clk_foo
23 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
24 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
26 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
27 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
28 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
29 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
30 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 #define CLK_SET_RATE_PARENT_IN_ORDER BIT(8) /* consider the order of re-parent
32 and set_div on rate change */
38 * struct clk_ops - Callback operations for hardware clocks; these are to
39 * be provided by the clock implementation, and will be called by drivers
40 * through the clk_* api.
42 * @prepare: Prepare the clock for enabling. This must not return until
43 * the clock is fully prepared, and it's safe to call clk_enable.
44 * This callback is intended to allow clock implementations to
45 * do any initialisation that may sleep. Called with
48 * @unprepare: Release the clock from its prepared state. This will typically
49 * undo any work done in the @prepare callback. Called with
52 * @is_prepared: Queries the hardware to determine if the clock is prepared.
53 * This function is allowed to sleep. Optional, if this op is not
54 * set then the prepare count will be used.
56 * @unprepare_unused: Unprepare the clock atomically. Only called from
57 * clk_disable_unused for prepare clocks with special needs.
58 * Called with prepare mutex held. This function may sleep.
60 * @enable: Enable the clock atomically. This must not return until the
61 * clock is generating a valid clock signal, usable by consumer
62 * devices. Called with enable_lock held. This function must not
65 * @disable: Disable the clock atomically. Called with enable_lock held.
66 * This function must not sleep.
68 * @is_enabled: Queries the hardware to determine if the clock is enabled.
69 * This function must not sleep. Optional, if this op is not
70 * set then the enable count will be used.
72 * @disable_unused: Disable the clock atomically. Only called from
73 * clk_disable_unused for gate clocks with special needs.
74 * Called with enable_lock held. This function must not
77 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
78 * parent rate is an input parameter. It is up to the caller to
79 * ensure that the prepare_mutex is held across this call.
80 * Returns the calculated rate. Optional, but recommended - if
81 * this op is not set then clock rate will be initialized to 0.
83 * @round_rate: Given a target rate as input, returns the closest rate actually
84 * supported by the clock.
86 * @determine_rate: Given a target rate as input, returns the closest rate
87 * actually supported by the clock, and optionally the parent clock
88 * that should be used to provide the clock rate.
90 * @get_parent: Queries the hardware to determine the parent of a clock. The
91 * return value is a u8 which specifies the index corresponding to
92 * the parent clock. This index can be applied to either the
93 * .parent_names or .parents arrays. In short, this function
94 * translates the parent value read from hardware into an array
95 * index. Currently only called when the clock is initialized by
96 * __clk_init. This callback is mandatory for clocks with
97 * multiple parents. It is optional (and unnecessary) for clocks
98 * with 0 or 1 parents.
100 * @set_parent: Change the input source of this clock; for clocks with multiple
101 * possible parents specify a new parent by passing in the index
102 * as a u8 corresponding to the parent in either the .parent_names
103 * or .parents arrays. This function in affect translates an
104 * array index into the value programmed into the hardware.
105 * Returns 0 on success, -EERROR otherwise.
107 * @set_rate: Change the rate of this clock. The requested rate is specified
108 * by the second argument, which should typically be the return
109 * of .round_rate call. The third argument gives the parent rate
110 * which is likely helpful for most .set_rate implementation.
111 * Returns 0 on success, -EERROR otherwise.
113 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
114 * implementations to split any work between atomic (enable) and sleepable
115 * (prepare) contexts. If enabling a clock requires code that might sleep,
116 * this must be done in clk_prepare. Clock enable code that will never be
117 * called in a sleepable context may be implemented in clk_enable.
119 * Typically, drivers will call clk_prepare when a clock may be needed later
120 * (eg. when a device is opened), and clk_enable when the clock is actually
121 * required (eg. from an interrupt). Note that clk_prepare MUST have been
122 * called before clk_enable.
125 int (*prepare)(struct clk_hw *hw);
126 void (*unprepare)(struct clk_hw *hw);
127 int (*is_prepared)(struct clk_hw *hw);
128 void (*unprepare_unused)(struct clk_hw *hw);
129 int (*enable)(struct clk_hw *hw);
130 void (*disable)(struct clk_hw *hw);
131 int (*is_enabled)(struct clk_hw *hw);
132 void (*disable_unused)(struct clk_hw *hw);
133 unsigned long (*recalc_rate)(struct clk_hw *hw,
134 unsigned long parent_rate);
135 long (*round_rate)(struct clk_hw *hw, unsigned long,
137 long (*determine_rate)(struct clk_hw *hw, unsigned long rate,
138 unsigned long *best_parent_rate,
139 struct clk **best_parent_clk);
140 int (*set_parent)(struct clk_hw *hw, u8 index);
141 u8 (*get_parent)(struct clk_hw *hw);
142 int (*set_rate)(struct clk_hw *hw, unsigned long,
144 void (*init)(struct clk_hw *hw);
148 * struct clk_init_data - holds init data that's common to all clocks and is
149 * shared between the clock provider and the common clock framework.
152 * @ops: operations this clock supports
153 * @parent_names: array of string names for all possible parents
154 * @num_parents: number of possible parents
155 * @flags: framework-level hints and quirks
157 struct clk_init_data {
159 const struct clk_ops *ops;
160 const char **parent_names;
166 * struct clk_hw - handle for traversing from a struct clk to its corresponding
167 * hardware-specific structure. struct clk_hw should be declared within struct
168 * clk_foo and then referenced by the struct clk instance that uses struct
171 * @clk: pointer to the struct clk instance that points back to this struct
174 * @init: pointer to struct clk_init_data that contains the init data shared
175 * with the common clock framework.
179 const struct clk_init_data *init;
183 * DOC: Basic clock implementations common to many platforms
185 * Each basic clock hardware type is comprised of a structure describing the
186 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
187 * unique flags for that hardware type, a registration function and an
188 * alternative macro for static initialization
192 * struct clk_fixed_rate - fixed-rate clock
193 * @hw: handle between common and hardware-specific interfaces
194 * @fixed_rate: constant frequency of clock
196 struct clk_fixed_rate {
198 unsigned long fixed_rate;
202 extern const struct clk_ops clk_fixed_rate_ops;
203 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
204 const char *parent_name, unsigned long flags,
205 unsigned long fixed_rate);
207 void of_fixed_clk_setup(struct device_node *np);
210 * struct clk_gate - gating clock
212 * @hw: handle between common and hardware-specific interfaces
213 * @reg: register controlling gate
214 * @bit_idx: single bit controlling gate
215 * @flags: hardware-specific flags
216 * @lock: register lock
218 * Clock which can gate its output. Implements .enable & .disable
221 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
222 * enable the clock. Setting this flag does the opposite: setting the bit
223 * disable the clock and clearing it enables the clock
224 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
225 * of this register, and mask of gate bits are in higher 16-bit of this
226 * register. While setting the gate bits, higher 16-bit should also be
227 * updated to indicate changing gate bits.
237 #define CLK_GATE_SET_TO_DISABLE BIT(0)
238 #define CLK_GATE_HIWORD_MASK BIT(1)
240 extern const struct clk_ops clk_gate_ops;
241 struct clk *clk_register_gate(struct device *dev, const char *name,
242 const char *parent_name, unsigned long flags,
243 void __iomem *reg, u8 bit_idx,
244 u8 clk_gate_flags, spinlock_t *lock);
246 struct clk_div_table {
252 * struct clk_divider - adjustable divider clock
254 * @hw: handle between common and hardware-specific interfaces
255 * @reg: register containing the divider
256 * @shift: shift to the divider bit field
257 * @width: width of the divider bit field
258 * @table: array of value/divider pairs, last entry should have div = 0
259 * @lock: register lock
261 * Clock with an adjustable divider affecting its output frequency. Implements
262 * .recalc_rate, .set_rate and .round_rate
265 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
266 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
267 * the raw value read from the register, with the value of zero considered
268 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
269 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
270 * the hardware register
271 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
272 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
273 * Some hardware implementations gracefully handle this case and allow a
274 * zero divisor by not modifying their input clock
275 * (divide by one / bypass).
276 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
277 * of this register, and mask of divider bits are in higher 16-bit of this
278 * register. While setting the divider bits, higher 16-bit should also be
279 * updated to indicate changing divider bits.
287 const struct clk_div_table *table;
291 #define CLK_DIVIDER_ONE_BASED BIT(0)
292 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
293 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
294 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
296 extern const struct clk_ops clk_divider_ops;
297 struct clk *clk_register_divider(struct device *dev, const char *name,
298 const char *parent_name, unsigned long flags,
299 void __iomem *reg, u8 shift, u8 width,
300 u8 clk_divider_flags, spinlock_t *lock);
301 struct clk *clk_register_divider_table(struct device *dev, const char *name,
302 const char *parent_name, unsigned long flags,
303 void __iomem *reg, u8 shift, u8 width,
304 u8 clk_divider_flags, const struct clk_div_table *table,
308 * struct clk_mux - multiplexer clock
310 * @hw: handle between common and hardware-specific interfaces
311 * @reg: register controlling multiplexer
312 * @shift: shift to multiplexer bit field
313 * @width: width of mutliplexer bit field
314 * @flags: hardware-specific flags
315 * @lock: register lock
317 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
321 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
322 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
323 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
324 * register, and mask of mux bits are in higher 16-bit of this register.
325 * While setting the mux bits, higher 16-bit should also be updated to
326 * indicate changing mux bits.
338 #define CLK_MUX_INDEX_ONE BIT(0)
339 #define CLK_MUX_INDEX_BIT BIT(1)
340 #define CLK_MUX_HIWORD_MASK BIT(2)
342 extern const struct clk_ops clk_mux_ops;
344 struct clk *clk_register_mux(struct device *dev, const char *name,
345 const char **parent_names, u8 num_parents, unsigned long flags,
346 void __iomem *reg, u8 shift, u8 width,
347 u8 clk_mux_flags, spinlock_t *lock);
349 struct clk *clk_register_mux_table(struct device *dev, const char *name,
350 const char **parent_names, u8 num_parents, unsigned long flags,
351 void __iomem *reg, u8 shift, u32 mask,
352 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
354 void of_fixed_factor_clk_setup(struct device_node *node);
357 * struct clk_fixed_factor - fixed multiplier and divider clock
359 * @hw: handle between common and hardware-specific interfaces
363 * Clock with a fixed multiplier and divider. The output frequency is the
364 * parent clock rate divided by div and multiplied by mult.
365 * Implements .recalc_rate, .set_rate and .round_rate
368 struct clk_fixed_factor {
374 extern struct clk_ops clk_fixed_factor_ops;
375 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
376 const char *parent_name, unsigned long flags,
377 unsigned int mult, unsigned int div);
380 * struct clk_composite - aggregate clock of mux, divider and gate clocks
382 * @hw: handle between common and hardware-specific interfaces
383 * @mux_hw: handle between composite and hardware-specific mux clock
384 * @rate_hw: handle between composite and hardware-specific rate clock
385 * @gate_hw: handle between composite and hardware-specific gate clock
386 * @mux_ops: clock ops for mux
387 * @rate_ops: clock ops for rate
388 * @gate_ops: clock ops for gate
390 struct clk_composite {
394 struct clk_hw *mux_hw;
395 struct clk_hw *rate_hw;
396 struct clk_hw *gate_hw;
398 const struct clk_ops *mux_ops;
399 const struct clk_ops *rate_ops;
400 const struct clk_ops *gate_ops;
403 struct clk *clk_register_composite(struct device *dev, const char *name,
404 const char **parent_names, int num_parents,
405 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
406 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
407 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
408 unsigned long flags);
411 * clk_register - allocate a new clock, register it and return an opaque cookie
412 * @dev: device that is registering this clock
413 * @hw: link to hardware-specific clock data
415 * clk_register is the primary interface for populating the clock tree with new
416 * clock nodes. It returns a pointer to the newly allocated struct clk which
417 * cannot be dereferenced by driver code but may be used in conjuction with the
418 * rest of the clock API. In the event of an error clk_register will return an
419 * error code; drivers must test for an error code after calling clk_register.
421 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
422 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
424 void clk_unregister(struct clk *clk);
425 void devm_clk_unregister(struct device *dev, struct clk *clk);
427 /* helper functions */
428 const char *__clk_get_name(struct clk *clk);
429 struct clk_hw *__clk_get_hw(struct clk *clk);
430 u8 __clk_get_num_parents(struct clk *clk);
431 struct clk *__clk_get_parent(struct clk *clk);
432 struct clk *clk_get_parent_by_index(struct clk *clk, u8 index);
433 unsigned int __clk_get_enable_count(struct clk *clk);
434 unsigned int __clk_get_prepare_count(struct clk *clk);
435 unsigned long __clk_get_rate(struct clk *clk);
436 unsigned long __clk_get_flags(struct clk *clk);
437 bool __clk_is_prepared(struct clk *clk);
438 bool __clk_is_enabled(struct clk *clk);
439 struct clk *__clk_lookup(const char *name);
440 long __clk_mux_determine_rate(struct clk_hw *hw, unsigned long rate,
441 unsigned long *best_parent_rate,
442 struct clk **best_parent_p);
445 * FIXME clock api without lock protection
447 int __clk_prepare(struct clk *clk);
448 void __clk_unprepare(struct clk *clk);
449 void __clk_reparent(struct clk *clk, struct clk *new_parent);
450 unsigned long __clk_round_rate(struct clk *clk, unsigned long rate);
454 typedef void (*of_clk_init_cb_t)(struct device_node *);
456 int of_clk_add_provider(struct device_node *np,
457 struct clk *(*clk_src_get)(struct of_phandle_args *args,
460 void of_clk_del_provider(struct device_node *np);
461 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
463 struct clk_onecell_data {
465 unsigned int clk_num;
467 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
468 int of_clk_get_parent_count(struct device_node *np);
469 const char *of_clk_get_parent_name(struct device_node *np, int index);
471 void of_clk_init(const struct of_device_id *matches);
473 #define CLK_OF_DECLARE(name, compat, fn) \
474 static const struct of_device_id __clk_of_table_##name \
475 __used __section(__clk_of_table) \
476 = { .compatible = compat, .data = fn };
478 #endif /* CONFIG_COMMON_CLK */
479 #endif /* CLK_PROVIDER_H */