2 * linux/include/linux/clk-provider.h
4 * Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
5 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
11 #ifndef __LINUX_CLK_PROVIDER_H
12 #define __LINUX_CLK_PROVIDER_H
17 #ifdef CONFIG_COMMON_CLK
20 * flags used across common struct clk. these flags should only affect the
21 * top-level framework. custom flags for dealing with hardware specifics
22 * belong in struct clk_foo
24 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
25 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
27 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
28 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
29 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
30 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
31 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
32 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
33 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
34 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
35 #define CLK_KEEP_REQ_RATE BIT(12) /* keep reqrate on parent rate change */
43 * struct clk_rate_request - Structure encoding the clk constraints that
44 * a clock user might require.
46 * @rate: Requested clock rate. This field will be adjusted by
47 * clock drivers according to hardware capabilities.
48 * @min_rate: Minimum rate imposed by clk users.
49 * @max_rate: Maximum rate a imposed by clk users.
50 * @best_parent_rate: The best parent rate a parent can provide to fulfill the
51 * requested constraints.
52 * @best_parent_hw: The most appropriate parent clock that fulfills the
53 * requested constraints.
56 struct clk_rate_request {
58 unsigned long min_rate;
59 unsigned long max_rate;
60 unsigned long best_parent_rate;
61 struct clk_hw *best_parent_hw;
65 * struct clk_ops - Callback operations for hardware clocks; these are to
66 * be provided by the clock implementation, and will be called by drivers
67 * through the clk_* api.
69 * @prepare: Prepare the clock for enabling. This must not return until
70 * the clock is fully prepared, and it's safe to call clk_enable.
71 * This callback is intended to allow clock implementations to
72 * do any initialisation that may sleep. Called with
75 * @unprepare: Release the clock from its prepared state. This will typically
76 * undo any work done in the @prepare callback. Called with
79 * @is_prepared: Queries the hardware to determine if the clock is prepared.
80 * This function is allowed to sleep. Optional, if this op is not
81 * set then the prepare count will be used.
83 * @unprepare_unused: Unprepare the clock atomically. Only called from
84 * clk_disable_unused for prepare clocks with special needs.
85 * Called with prepare mutex held. This function may sleep.
87 * @enable: Enable the clock atomically. This must not return until the
88 * clock is generating a valid clock signal, usable by consumer
89 * devices. Called with enable_lock held. This function must not
92 * @disable: Disable the clock atomically. Called with enable_lock held.
93 * This function must not sleep.
95 * @is_enabled: Queries the hardware to determine if the clock is enabled.
96 * This function must not sleep. Optional, if this op is not
97 * set then the enable count will be used.
99 * @disable_unused: Disable the clock atomically. Only called from
100 * clk_disable_unused for gate clocks with special needs.
101 * Called with enable_lock held. This function must not
104 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
105 * parent rate is an input parameter. It is up to the caller to
106 * ensure that the prepare_mutex is held across this call.
107 * Returns the calculated rate. Optional, but recommended - if
108 * this op is not set then clock rate will be initialized to 0.
110 * @round_rate: Given a target rate as input, returns the closest rate actually
111 * supported by the clock. The parent rate is an input/output
114 * @determine_rate: Given a target rate as input, returns the closest rate
115 * actually supported by the clock, and optionally the parent clock
116 * that should be used to provide the clock rate.
118 * @set_parent: Change the input source of this clock; for clocks with multiple
119 * possible parents specify a new parent by passing in the index
120 * as a u8 corresponding to the parent in either the .parent_names
121 * or .parents arrays. This function in affect translates an
122 * array index into the value programmed into the hardware.
123 * Returns 0 on success, -EERROR otherwise.
125 * @get_parent: Queries the hardware to determine the parent of a clock. The
126 * return value is a u8 which specifies the index corresponding to
127 * the parent clock. This index can be applied to either the
128 * .parent_names or .parents arrays. In short, this function
129 * translates the parent value read from hardware into an array
130 * index. Currently only called when the clock is initialized by
131 * __clk_init. This callback is mandatory for clocks with
132 * multiple parents. It is optional (and unnecessary) for clocks
133 * with 0 or 1 parents.
135 * @set_rate: Change the rate of this clock. The requested rate is specified
136 * by the second argument, which should typically be the return
137 * of .round_rate call. The third argument gives the parent rate
138 * which is likely helpful for most .set_rate implementation.
139 * Returns 0 on success, -EERROR otherwise.
141 * @set_rate_and_parent: Change the rate and the parent of this clock. The
142 * requested rate is specified by the second argument, which
143 * should typically be the return of .round_rate call. The
144 * third argument gives the parent rate which is likely helpful
145 * for most .set_rate_and_parent implementation. The fourth
146 * argument gives the parent index. This callback is optional (and
147 * unnecessary) for clocks with 0 or 1 parents as well as
148 * for clocks that can tolerate switching the rate and the parent
149 * separately via calls to .set_parent and .set_rate.
150 * Returns 0 on success, -EERROR otherwise.
152 * @recalc_accuracy: Recalculate the accuracy of this clock. The clock accuracy
153 * is expressed in ppb (parts per billion). The parent accuracy is
154 * an input parameter.
155 * Returns the calculated accuracy. Optional - if this op is not
156 * set then clock accuracy will be initialized to parent accuracy
157 * or 0 (perfect clock) if clock has no parent.
159 * @get_phase: Queries the hardware to get the current phase of a clock.
160 * Returned values are 0-359 degrees on success, negative
161 * error codes on failure.
163 * @set_phase: Shift the phase this clock signal in degrees specified
164 * by the second argument. Valid values for degrees are
165 * 0-359. Return 0 on success, otherwise -EERROR.
167 * @init: Perform platform-specific initialization magic.
168 * This is not not used by any of the basic clock types.
169 * Please consider other ways of solving initialization problems
170 * before using this callback, as its use is discouraged.
172 * @debug_init: Set up type-specific debugfs entries for this clock. This
173 * is called once, after the debugfs directory entry for this
174 * clock has been created. The dentry pointer representing that
175 * directory is provided as an argument. Called with
176 * prepare_lock held. Returns 0 on success, -EERROR otherwise.
179 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
180 * implementations to split any work between atomic (enable) and sleepable
181 * (prepare) contexts. If enabling a clock requires code that might sleep,
182 * this must be done in clk_prepare. Clock enable code that will never be
183 * called in a sleepable context may be implemented in clk_enable.
185 * Typically, drivers will call clk_prepare when a clock may be needed later
186 * (eg. when a device is opened), and clk_enable when the clock is actually
187 * required (eg. from an interrupt). Note that clk_prepare MUST have been
188 * called before clk_enable.
191 int (*prepare)(struct clk_hw *hw);
192 void (*unprepare)(struct clk_hw *hw);
193 int (*is_prepared)(struct clk_hw *hw);
194 void (*unprepare_unused)(struct clk_hw *hw);
195 int (*enable)(struct clk_hw *hw);
196 void (*disable)(struct clk_hw *hw);
197 int (*is_enabled)(struct clk_hw *hw);
198 void (*disable_unused)(struct clk_hw *hw);
199 unsigned long (*recalc_rate)(struct clk_hw *hw,
200 unsigned long parent_rate);
201 long (*round_rate)(struct clk_hw *hw, unsigned long rate,
202 unsigned long *parent_rate);
203 int (*determine_rate)(struct clk_hw *hw,
204 struct clk_rate_request *req);
205 int (*set_parent)(struct clk_hw *hw, u8 index);
206 u8 (*get_parent)(struct clk_hw *hw);
207 int (*set_rate)(struct clk_hw *hw, unsigned long rate,
208 unsigned long parent_rate);
209 int (*set_rate_and_parent)(struct clk_hw *hw,
211 unsigned long parent_rate, u8 index);
212 unsigned long (*recalc_accuracy)(struct clk_hw *hw,
213 unsigned long parent_accuracy);
214 int (*get_phase)(struct clk_hw *hw);
215 int (*set_phase)(struct clk_hw *hw, int degrees);
216 void (*init)(struct clk_hw *hw);
217 int (*debug_init)(struct clk_hw *hw, struct dentry *dentry);
221 * struct clk_init_data - holds init data that's common to all clocks and is
222 * shared between the clock provider and the common clock framework.
225 * @ops: operations this clock supports
226 * @parent_names: array of string names for all possible parents
227 * @num_parents: number of possible parents
228 * @flags: framework-level hints and quirks
230 struct clk_init_data {
232 const struct clk_ops *ops;
233 const char * const *parent_names;
239 * struct clk_hw - handle for traversing from a struct clk to its corresponding
240 * hardware-specific structure. struct clk_hw should be declared within struct
241 * clk_foo and then referenced by the struct clk instance that uses struct
244 * @core: pointer to the struct clk_core instance that points back to this
245 * struct clk_hw instance
247 * @clk: pointer to the per-user struct clk instance that can be used to call
250 * @init: pointer to struct clk_init_data that contains the init data shared
251 * with the common clock framework.
254 struct clk_core *core;
256 const struct clk_init_data *init;
260 * DOC: Basic clock implementations common to many platforms
262 * Each basic clock hardware type is comprised of a structure describing the
263 * clock hardware, implementations of the relevant callbacks in struct clk_ops,
264 * unique flags for that hardware type, a registration function and an
265 * alternative macro for static initialization
269 * struct clk_fixed_rate - fixed-rate clock
270 * @hw: handle between common and hardware-specific interfaces
271 * @fixed_rate: constant frequency of clock
273 struct clk_fixed_rate {
275 unsigned long fixed_rate;
276 unsigned long fixed_accuracy;
280 extern const struct clk_ops clk_fixed_rate_ops;
281 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
282 const char *parent_name, unsigned long flags,
283 unsigned long fixed_rate);
284 struct clk *clk_register_fixed_rate_with_accuracy(struct device *dev,
285 const char *name, const char *parent_name, unsigned long flags,
286 unsigned long fixed_rate, unsigned long fixed_accuracy);
288 void of_fixed_clk_setup(struct device_node *np);
291 * struct clk_gate - gating clock
293 * @hw: handle between common and hardware-specific interfaces
294 * @reg: register controlling gate
295 * @bit_idx: single bit controlling gate
296 * @flags: hardware-specific flags
297 * @lock: register lock
299 * Clock which can gate its output. Implements .enable & .disable
302 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
303 * enable the clock. Setting this flag does the opposite: setting the bit
304 * disable the clock and clearing it enables the clock
305 * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
306 * of this register, and mask of gate bits are in higher 16-bit of this
307 * register. While setting the gate bits, higher 16-bit should also be
308 * updated to indicate changing gate bits.
318 #define CLK_GATE_SET_TO_DISABLE BIT(0)
319 #define CLK_GATE_HIWORD_MASK BIT(1)
321 extern const struct clk_ops clk_gate_ops;
322 struct clk *clk_register_gate(struct device *dev, const char *name,
323 const char *parent_name, unsigned long flags,
324 void __iomem *reg, u8 bit_idx,
325 u8 clk_gate_flags, spinlock_t *lock);
326 void clk_unregister_gate(struct clk *clk);
328 struct clk_div_table {
334 * struct clk_divider - adjustable divider clock
336 * @hw: handle between common and hardware-specific interfaces
337 * @reg: register containing the divider
338 * @shift: shift to the divider bit field
339 * @width: width of the divider bit field
340 * @table: array of value/divider pairs, last entry should have div = 0
341 * @lock: register lock
343 * Clock with an adjustable divider affecting its output frequency. Implements
344 * .recalc_rate, .set_rate and .round_rate
347 * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
348 * register plus one. If CLK_DIVIDER_ONE_BASED is set then the divider is
349 * the raw value read from the register, with the value of zero considered
350 * invalid, unless CLK_DIVIDER_ALLOW_ZERO is set.
351 * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
352 * the hardware register
353 * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors. For dividers which have
354 * CLK_DIVIDER_ONE_BASED set, it is possible to end up with a zero divisor.
355 * Some hardware implementations gracefully handle this case and allow a
356 * zero divisor by not modifying their input clock
357 * (divide by one / bypass).
358 * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
359 * of this register, and mask of divider bits are in higher 16-bit of this
360 * register. While setting the divider bits, higher 16-bit should also be
361 * updated to indicate changing divider bits.
362 * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
363 * to the closest integer instead of the up one.
364 * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
365 * not be changed by the clock framework.
366 * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
367 * except when the value read from the register is zero, the divisor is
368 * 2^width of the field.
376 const struct clk_div_table *table;
380 #define CLK_DIVIDER_ONE_BASED BIT(0)
381 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
382 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
383 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
384 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
385 #define CLK_DIVIDER_READ_ONLY BIT(5)
386 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)
388 extern const struct clk_ops clk_divider_ops;
389 extern const struct clk_ops clk_divider_ro_ops;
391 unsigned long divider_recalc_rate(struct clk_hw *hw, unsigned long parent_rate,
392 unsigned int val, const struct clk_div_table *table,
393 unsigned long flags);
394 long divider_round_rate(struct clk_hw *hw, unsigned long rate,
395 unsigned long *prate, const struct clk_div_table *table,
396 u8 width, unsigned long flags);
397 int divider_get_val(unsigned long rate, unsigned long parent_rate,
398 const struct clk_div_table *table, u8 width,
399 unsigned long flags);
401 struct clk *clk_register_divider(struct device *dev, const char *name,
402 const char *parent_name, unsigned long flags,
403 void __iomem *reg, u8 shift, u8 width,
404 u8 clk_divider_flags, spinlock_t *lock);
405 struct clk *clk_register_divider_table(struct device *dev, const char *name,
406 const char *parent_name, unsigned long flags,
407 void __iomem *reg, u8 shift, u8 width,
408 u8 clk_divider_flags, const struct clk_div_table *table,
410 void clk_unregister_divider(struct clk *clk);
413 * struct clk_mux - multiplexer clock
415 * @hw: handle between common and hardware-specific interfaces
416 * @reg: register controlling multiplexer
417 * @shift: shift to multiplexer bit field
418 * @width: width of mutliplexer bit field
419 * @flags: hardware-specific flags
420 * @lock: register lock
422 * Clock with multiple selectable parents. Implements .get_parent, .set_parent
426 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
427 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
428 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
429 * register, and mask of mux bits are in higher 16-bit of this register.
430 * While setting the mux bits, higher 16-bit should also be updated to
431 * indicate changing mux bits.
432 * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
445 #define CLK_MUX_INDEX_ONE BIT(0)
446 #define CLK_MUX_INDEX_BIT BIT(1)
447 #define CLK_MUX_HIWORD_MASK BIT(2)
448 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
449 #define CLK_MUX_ROUND_CLOSEST BIT(4)
451 extern const struct clk_ops clk_mux_ops;
452 extern const struct clk_ops clk_mux_ro_ops;
454 struct clk *clk_register_mux(struct device *dev, const char *name,
455 const char * const *parent_names, u8 num_parents,
457 void __iomem *reg, u8 shift, u8 width,
458 u8 clk_mux_flags, spinlock_t *lock);
460 struct clk *clk_register_mux_table(struct device *dev, const char *name,
461 const char * const *parent_names, u8 num_parents,
463 void __iomem *reg, u8 shift, u32 mask,
464 u8 clk_mux_flags, u32 *table, spinlock_t *lock);
466 void clk_unregister_mux(struct clk *clk);
468 void of_fixed_factor_clk_setup(struct device_node *node);
471 * struct clk_fixed_factor - fixed multiplier and divider clock
473 * @hw: handle between common and hardware-specific interfaces
477 * Clock with a fixed multiplier and divider. The output frequency is the
478 * parent clock rate divided by div and multiplied by mult.
479 * Implements .recalc_rate, .set_rate and .round_rate
482 struct clk_fixed_factor {
488 extern const struct clk_ops clk_fixed_factor_ops;
489 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
490 const char *parent_name, unsigned long flags,
491 unsigned int mult, unsigned int div);
494 * struct clk_fractional_divider - adjustable fractional divider clock
496 * @hw: handle between common and hardware-specific interfaces
497 * @reg: register containing the divider
498 * @mshift: shift to the numerator bit field
499 * @mwidth: width of the numerator bit field
500 * @nshift: shift to the denominator bit field
501 * @nwidth: width of the denominator bit field
502 * @lock: register lock
504 * Clock with adjustable fractional divider affecting its output frequency.
506 struct clk_fractional_divider {
519 extern const struct clk_ops clk_fractional_divider_ops;
520 struct clk *clk_register_fractional_divider(struct device *dev,
521 const char *name, const char *parent_name, unsigned long flags,
522 void __iomem *reg, u8 mshift, u8 mwidth, u8 nshift, u8 nwidth,
523 u8 clk_divider_flags, spinlock_t *lock);
526 * struct clk_multiplier - adjustable multiplier clock
528 * @hw: handle between common and hardware-specific interfaces
529 * @reg: register containing the multiplier
530 * @shift: shift to the multiplier bit field
531 * @width: width of the multiplier bit field
532 * @lock: register lock
534 * Clock with an adjustable multiplier affecting its output frequency.
535 * Implements .recalc_rate, .set_rate and .round_rate
538 * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
539 * from the register, with 0 being a valid value effectively
540 * zeroing the output clock rate. If CLK_MULTIPLIER_ZERO_BYPASS is
541 * set, then a null multiplier will be considered as a bypass,
542 * leaving the parent rate unmodified.
543 * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
544 * rounded to the closest integer instead of the down one.
546 struct clk_multiplier {
555 #define CLK_MULTIPLIER_ZERO_BYPASS BIT(0)
556 #define CLK_MULTIPLIER_ROUND_CLOSEST BIT(1)
558 extern const struct clk_ops clk_multiplier_ops;
561 * struct clk_composite - aggregate clock of mux, divider and gate clocks
563 * @hw: handle between common and hardware-specific interfaces
564 * @mux_hw: handle between composite and hardware-specific mux clock
565 * @rate_hw: handle between composite and hardware-specific rate clock
566 * @gate_hw: handle between composite and hardware-specific gate clock
567 * @mux_ops: clock ops for mux
568 * @rate_ops: clock ops for rate
569 * @gate_ops: clock ops for gate
571 struct clk_composite {
575 struct clk_hw *mux_hw;
576 struct clk_hw *rate_hw;
577 struct clk_hw *gate_hw;
579 const struct clk_ops *mux_ops;
580 const struct clk_ops *rate_ops;
581 const struct clk_ops *gate_ops;
584 struct clk *clk_register_composite(struct device *dev, const char *name,
585 const char * const *parent_names, int num_parents,
586 struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
587 struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
588 struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
589 unsigned long flags);
592 * struct clk_gpio_gate - gpio gated clock
594 * @hw: handle between common and hardware-specific interfaces
595 * @gpiod: gpio descriptor
597 * Clock with a gpio control for enabling and disabling the parent clock.
598 * Implements .enable, .disable and .is_enabled
603 struct gpio_desc *gpiod;
606 extern const struct clk_ops clk_gpio_gate_ops;
607 struct clk *clk_register_gpio_gate(struct device *dev, const char *name,
608 const char *parent_name, unsigned gpio, bool active_low,
609 unsigned long flags);
611 void of_gpio_clk_gate_setup(struct device_node *node);
614 * struct clk_gpio_mux - gpio controlled clock multiplexer
616 * @hw: see struct clk_gpio
617 * @gpiod: gpio descriptor to select the parent of this clock multiplexer
619 * Clock with a gpio control for selecting the parent clock.
620 * Implements .get_parent, .set_parent and .determine_rate
623 extern const struct clk_ops clk_gpio_mux_ops;
624 struct clk *clk_register_gpio_mux(struct device *dev, const char *name,
625 const char * const *parent_names, u8 num_parents, unsigned gpio,
626 bool active_low, unsigned long flags);
628 void of_gpio_mux_clk_setup(struct device_node *node);
631 * clk_register - allocate a new clock, register it and return an opaque cookie
632 * @dev: device that is registering this clock
633 * @hw: link to hardware-specific clock data
635 * clk_register is the primary interface for populating the clock tree with new
636 * clock nodes. It returns a pointer to the newly allocated struct clk which
637 * cannot be dereferenced by driver code but may be used in conjuction with the
638 * rest of the clock API. In the event of an error clk_register will return an
639 * error code; drivers must test for an error code after calling clk_register.
641 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
642 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
644 void clk_unregister(struct clk *clk);
645 void devm_clk_unregister(struct device *dev, struct clk *clk);
647 /* helper functions */
648 const char *__clk_get_name(const struct clk *clk);
649 const char *clk_hw_get_name(const struct clk_hw *hw);
650 struct clk_hw *__clk_get_hw(struct clk *clk);
651 unsigned int clk_hw_get_num_parents(const struct clk_hw *hw);
652 struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw);
653 struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw,
655 unsigned int __clk_get_enable_count(struct clk *clk);
656 unsigned long clk_hw_get_rate(const struct clk_hw *hw);
657 unsigned long __clk_get_flags(struct clk *clk);
658 unsigned long clk_hw_get_flags(const struct clk_hw *hw);
659 bool clk_hw_is_prepared(const struct clk_hw *hw);
660 bool clk_hw_is_enabled(const struct clk_hw *hw);
661 bool __clk_is_enabled(struct clk *clk);
662 struct clk *__clk_lookup(const char *name);
663 int __clk_mux_determine_rate(struct clk_hw *hw,
664 struct clk_rate_request *req);
665 int __clk_determine_rate(struct clk_hw *core, struct clk_rate_request *req);
666 int __clk_mux_determine_rate_closest(struct clk_hw *hw,
667 struct clk_rate_request *req);
668 void clk_hw_reparent(struct clk_hw *hw, struct clk_hw *new_parent);
669 void clk_hw_set_rate_range(struct clk_hw *hw, unsigned long min_rate,
670 unsigned long max_rate);
672 static inline void __clk_hw_set_clk(struct clk_hw *dst, struct clk_hw *src)
675 dst->core = src->core;
679 * FIXME clock api without lock protection
681 unsigned long clk_hw_round_rate(struct clk_hw *hw, unsigned long rate);
685 typedef void (*of_clk_init_cb_t)(struct device_node *);
687 struct clk_onecell_data {
689 unsigned int clk_num;
692 extern struct of_device_id __clk_of_table;
694 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
697 int of_clk_add_provider(struct device_node *np,
698 struct clk *(*clk_src_get)(struct of_phandle_args *args,
701 void of_clk_del_provider(struct device_node *np);
702 struct clk *of_clk_src_simple_get(struct of_phandle_args *clkspec,
704 struct clk *of_clk_src_onecell_get(struct of_phandle_args *clkspec, void *data);
705 int of_clk_get_parent_count(struct device_node *np);
706 int of_clk_parent_fill(struct device_node *np, const char **parents,
708 const char *of_clk_get_parent_name(struct device_node *np, int index);
710 void of_clk_init(const struct of_device_id *matches);
712 #else /* !CONFIG_OF */
714 static inline int of_clk_add_provider(struct device_node *np,
715 struct clk *(*clk_src_get)(struct of_phandle_args *args,
721 #define of_clk_del_provider(np) \
723 static inline struct clk *of_clk_src_simple_get(
724 struct of_phandle_args *clkspec, void *data)
726 return ERR_PTR(-ENOENT);
728 static inline struct clk *of_clk_src_onecell_get(
729 struct of_phandle_args *clkspec, void *data)
731 return ERR_PTR(-ENOENT);
733 static inline int of_clk_get_parent_count(struct device_node *np)
737 static inline int of_clk_parent_fill(struct device_node *np,
738 const char **parents, unsigned int size)
742 static inline const char *of_clk_get_parent_name(struct device_node *np,
747 #define of_clk_init(matches) \
749 #endif /* CONFIG_OF */
752 * wrap access to peripherals in accessor routines
753 * for improved portability across platforms
756 #if IS_ENABLED(CONFIG_PPC)
758 static inline u32 clk_readl(u32 __iomem *reg)
760 return ioread32be(reg);
763 static inline void clk_writel(u32 val, u32 __iomem *reg)
765 iowrite32be(val, reg);
768 #else /* platform dependent I/O accessors */
770 static inline u32 clk_readl(u32 __iomem *reg)
775 static inline void clk_writel(u32 val, u32 __iomem *reg)
780 #endif /* platform dependent I/O accessors */
782 #ifdef CONFIG_DEBUG_FS
783 struct dentry *clk_debugfs_add_file(struct clk_hw *hw, char *name, umode_t mode,
784 void *data, const struct file_operations *fops);
787 #endif /* CONFIG_COMMON_CLK */
788 #endif /* CLK_PROVIDER_H */