2 * Copyright (C) 2012 ARM Ltd.
3 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 #ifndef __ASM_ARM_KVM_VGIC_H
20 #define __ASM_ARM_KVM_VGIC_H
22 #include <linux/kernel.h>
23 #include <linux/kvm.h>
24 #include <linux/irqreturn.h>
25 #include <linux/spinlock.h>
26 #include <linux/types.h>
28 #define VGIC_NR_IRQS 256
29 #define VGIC_NR_SGIS 16
30 #define VGIC_NR_PPIS 16
31 #define VGIC_NR_PRIVATE_IRQS (VGIC_NR_SGIS + VGIC_NR_PPIS)
33 #define VGIC_V2_MAX_LRS (1 << 6)
34 #define VGIC_V3_MAX_LRS 16
36 /* Sanity checks... */
37 #if (KVM_MAX_VCPUS > 8)
38 #error Invalid number of CPU interfaces
41 #if (VGIC_NR_IRQS & 31)
42 #error "VGIC_NR_IRQS must be a multiple of 32"
45 #if (VGIC_NR_IRQS > 1024)
46 #error "VGIC_NR_IRQS must be <= 1024"
50 * The GIC distributor registers describing interrupts have two parts:
51 * - 32 per-CPU interrupts (SGI + PPI)
52 * - a bunch of shared interrupts (SPI)
56 * - One UL per VCPU for private interrupts (assumes UL is at
58 * - As many UL as necessary for shared interrupts.
60 * The private interrupts are accessed via the "private"
61 * field, one UL per vcpu (the state for vcpu n is in
62 * private[n]). The shared interrupts are accessed via the
63 * "shared" pointer (IRQn state is at bit n-32 in the bitmap).
65 unsigned long *private;
66 unsigned long *shared;
71 * - 8 u32 per VCPU for private interrupts
72 * - As many u32 as necessary for shared interrupts.
74 * The private interrupts are accessed via the "private"
75 * field, (the state for vcpu n is in private[n*8] to
76 * private[n*8 + 7]). The shared interrupts are accessed via
77 * the "shared" pointer (IRQn state is at byte (n-32)%4 of the
78 * shared[(n-32)/4] word).
87 VGIC_V2, /* Good ol' GICv2 */
88 VGIC_V3, /* New fancy GICv3 */
91 #define LR_STATE_PENDING (1 << 0)
92 #define LR_STATE_ACTIVE (1 << 1)
93 #define LR_STATE_MASK (3 << 0)
94 #define LR_EOI_INT (1 << 2)
110 struct vgic_lr (*get_lr)(const struct kvm_vcpu *, int);
111 void (*set_lr)(struct kvm_vcpu *, int, struct vgic_lr);
112 void (*sync_lr_elrsr)(struct kvm_vcpu *, int, struct vgic_lr);
113 u64 (*get_elrsr)(const struct kvm_vcpu *vcpu);
114 u64 (*get_eisr)(const struct kvm_vcpu *vcpu);
115 u32 (*get_interrupt_status)(const struct kvm_vcpu *vcpu);
116 void (*enable_underflow)(struct kvm_vcpu *vcpu);
117 void (*disable_underflow)(struct kvm_vcpu *vcpu);
118 void (*get_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
119 void (*set_vmcr)(struct kvm_vcpu *vcpu, struct vgic_vmcr *vmcr);
120 void (*enable)(struct kvm_vcpu *vcpu);
126 /* Physical address of vgic virtual cpu interface */
127 phys_addr_t vcpu_base;
128 /* Number of list registers */
130 /* Interrupt number */
131 unsigned int maint_irq;
132 /* Virtual control interface base address */
133 void __iomem *vctrl_base;
137 #ifdef CONFIG_KVM_ARM_VGIC
145 /* Virtual control interface mapping */
146 void __iomem *vctrl_base;
148 /* Distributor and vcpu interface mapping in the guest */
149 phys_addr_t vgic_dist_base;
150 phys_addr_t vgic_cpu_base;
152 /* Distributor enabled */
155 /* Interrupt enabled (one bit per IRQ) */
156 struct vgic_bitmap irq_enabled;
158 /* Level-triggered interrupt external input is asserted */
159 struct vgic_bitmap irq_level;
162 * Interrupt state is pending on the distributor
164 struct vgic_bitmap irq_pending;
167 * Tracks writes to GICD_ISPENDRn and GICD_ICPENDRn for level-triggered
168 * interrupts. Essentially holds the state of the flip-flop in
169 * Figure 4-10 on page 4-101 in ARM IHI 0048B.b.
170 * Once set, it is only cleared for level-triggered interrupts on
171 * guest ACKs (when we queue it) or writes to GICD_ICPENDRn.
173 struct vgic_bitmap irq_soft_pend;
175 /* Level-triggered interrupt queued on VCPU interface */
176 struct vgic_bitmap irq_queued;
178 /* Interrupt priority. Not used yet. */
179 struct vgic_bytemap irq_priority;
181 /* Level/edge triggered */
182 struct vgic_bitmap irq_cfg;
185 * Source CPU per SGI and target CPU:
187 * Each byte represent a SGI observable on a VCPU, each bit of
188 * this byte indicating if the corresponding VCPU has
189 * generated this interrupt. This is a GICv2 feature only.
191 * For VCPUn (n < 8), irq_sgi_sources[n*16] to [n*16 + 15] are
192 * the SGIs observable on VCPUn.
197 * Target CPU for each SPI:
199 * Array of available SPI, each byte indicating the target
200 * VCPU for SPI. IRQn (n >=32) is at irq_spi_cpu[n-32].
205 * Reverse lookup of irq_spi_cpu for faster compute pending:
207 * Array of bitmaps, one per VCPU, describing if IRQn is
208 * routed to a particular VCPU.
210 struct vgic_bitmap *irq_spi_target;
212 /* Bitmap indicating which CPU has something pending */
213 unsigned long *irq_pending_on_cpu;
217 struct vgic_v2_cpu_if {
220 u32 vgic_misr; /* Saved only */
221 u32 vgic_eisr[2]; /* Saved only */
222 u32 vgic_elrsr[2]; /* Saved only */
224 u32 vgic_lr[VGIC_V2_MAX_LRS];
227 struct vgic_v3_cpu_if {
228 #ifdef CONFIG_ARM_GIC_V3
231 u32 vgic_misr; /* Saved only */
232 u32 vgic_eisr; /* Saved only */
233 u32 vgic_elrsr; /* Saved only */
236 u64 vgic_lr[VGIC_V3_MAX_LRS];
241 #ifdef CONFIG_KVM_ARM_VGIC
242 /* per IRQ to LR mapping */
245 /* Pending interrupts on this VCPU */
246 DECLARE_BITMAP( pending_percpu, VGIC_NR_PRIVATE_IRQS);
247 unsigned long *pending_shared;
249 /* Bitmap of used/free list registers */
250 DECLARE_BITMAP( lr_used, VGIC_V2_MAX_LRS);
252 /* Number of list registers on this CPU */
255 /* CPU vif control registers for world switch */
257 struct vgic_v2_cpu_if vgic_v2;
258 struct vgic_v3_cpu_if vgic_v3;
263 #define LR_EMPTY 0xff
265 #define INT_STATUS_EOI (1 << 0)
266 #define INT_STATUS_UNDERFLOW (1 << 1)
271 struct kvm_exit_mmio;
273 #ifdef CONFIG_KVM_ARM_VGIC
274 int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write);
275 int kvm_vgic_hyp_init(void);
276 int kvm_vgic_init(struct kvm *kvm);
277 int kvm_vgic_create(struct kvm *kvm);
278 void kvm_vgic_destroy(struct kvm *kvm);
279 int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu);
280 void kvm_vgic_vcpu_destroy(struct kvm_vcpu *vcpu);
281 void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu);
282 void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu);
283 int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid, unsigned int irq_num,
285 int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu);
286 bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
287 struct kvm_exit_mmio *mmio);
289 #define irqchip_in_kernel(k) (!!((k)->arch.vgic.in_kernel))
290 #define vgic_initialized(k) ((k)->arch.vgic.ready)
292 int vgic_v2_probe(struct device_node *vgic_node,
293 const struct vgic_ops **ops,
294 const struct vgic_params **params);
295 #ifdef CONFIG_ARM_GIC_V3
296 int vgic_v3_probe(struct device_node *vgic_node,
297 const struct vgic_ops **ops,
298 const struct vgic_params **params);
300 static inline int vgic_v3_probe(struct device_node *vgic_node,
301 const struct vgic_ops **ops,
302 const struct vgic_params **params)
309 static inline int kvm_vgic_hyp_init(void)
314 static inline int kvm_vgic_set_addr(struct kvm *kvm, unsigned long type, u64 addr)
319 static inline int kvm_vgic_addr(struct kvm *kvm, unsigned long type, u64 *addr, bool write)
324 static inline int kvm_vgic_init(struct kvm *kvm)
329 static inline int kvm_vgic_create(struct kvm *kvm)
334 static inline int kvm_vgic_vcpu_init(struct kvm_vcpu *vcpu)
339 static inline void kvm_vgic_flush_hwstate(struct kvm_vcpu *vcpu) {}
340 static inline void kvm_vgic_sync_hwstate(struct kvm_vcpu *vcpu) {}
342 static inline int kvm_vgic_inject_irq(struct kvm *kvm, int cpuid,
343 unsigned int irq_num, bool level)
348 static inline int kvm_vgic_vcpu_pending_irq(struct kvm_vcpu *vcpu)
353 static inline bool vgic_handle_mmio(struct kvm_vcpu *vcpu, struct kvm_run *run,
354 struct kvm_exit_mmio *mmio)
359 static inline int irqchip_in_kernel(struct kvm *kvm)
364 static inline bool vgic_initialized(struct kvm *kvm)