include/dt-bindings/rkfb/rk_fb.h

   1 #ifndef _DT_BINDINGS_RKFB_H_
   2 #define _DT_BINDINGS_RKFB_H_
   3 #define GPIO            0
   4 #define REGULATOR       1
   5
   6 #define PRMRY           1               /*primary display device*/
   7 #define EXTEND          2               /*extend display device*/
   8
   9 #define NO_DUAL         0
  10 #define ONE_DUAL        1
  11 #define DUAL            2
  12
  13 #define OUT_P888            0   //24bit screen,connect to lcdc D0~D23
  14 #define OUT_P666            1   //18bit screen,connect to lcdc D0~D17
  15 #define OUT_P565            2
  16 #define OUT_S888x           4
  17 #define OUT_CCIR656         6
  18 #define OUT_S888            8
  19 #define OUT_S888DUMY        12
  20 #define OUT_P16BPP4         24
  21 #define OUT_D888_P666       0x21        //18bit screen,connect to lcdc D2~D7, D10~D15, D18~D23
  22 #define OUT_D888_P565       0x22
  23
  24 #define SCREEN_NULL        0
  25 #define SCREEN_RGB         1
  26 #define SCREEN_LVDS        2
  27 #define SCREEN_DUAL_LVDS   3
  28 #define SCREEN_MCU         4
  29 #define SCREEN_TVOUT       5
  30 #define SCREEN_HDMI        6
  31 #define SCREEN_MIPI        7
  32 #define SCREEN_DUAL_MIPI   8
  33 #define SCREEN_EDP         9
  34 #define SCREEN_TVOUT_TEST  10
  35
  36 #define LVDS_8BIT_1     0
  37 #define LVDS_8BIT_2     1
  38 #define LVDS_8BIT_3     2
  39 #define LVDS_6BIT       3
  40
  41 #define NO_MIRROR       0
  42 #define X_MIRROR        1
  43 #define Y_MIRROR        2
  44 #define X_Y_MIRROR      3
  45 #define ROTATE_90       4
  46 #define ROTATE_180      8
  47 #define ROTATE_270      12
  48
  49 #define COLOR_RGB       0
  50 #define COLOR_YCBCR     1
  51
  52 /* fb win map */
  53 #define FB_DEFAULT_ORDER                0
  54 #define FB0_WIN2_FB1_WIN1_FB2_WIN0      12
  55 #define FB0_WIN1_FB1_WIN2_FB2_WIN0      21
  56 #define FB0_WIN2_FB1_WIN0_FB2_WIN1      102
  57 #define FB0_WIN0_FB1_WIN2_FB2_WIN1      120
  58 #define FB0_WIN0_FB1_WIN1_FB2_WIN2      210
  59 #define FB0_WIN1_FB1_WIN0_FB2_WIN2      201
  60 #define FB0_WIN0_FB1_WIN1_FB2_WIN2_FB3_WIN3     3210
  61
  62 /*              lvds connect config
  63  *
  64  *              LVDS_8BIT_1    LVDS_8BIT_2     LVDS_8BIT_3     LVDS_6BIT
  65 ----------------------------------------------------------------------
  66         TX0     R0              R2              R2              R0
  67         TX1     R1              R3              R3              R1
  68         TX2     R2              R4              R4              R2
  69 Y       TX3     R3              R5              R5              R3
  70 0       TX4     R4              R6              R6              R4
  71         TX6     R5              R7              R7              R5
  72         TX7     G0              G2              G2              G0
  73 ----------------------------------------------------------------------
  74         TX8     G1              G3              G3              G1
  75         TX9     G2              G4              G4              G2
  76 Y       TX12    G3              G5              G5              G3
  77 1       TX13    G4              G6              G6              G4
  78         TX14    G5              G7              G7              G5
  79         TX15    B0              B2              B2              B0
  80         TX18    B1              B3              B3              B1
  81 ----------------------------------------------------------------------
  82         TX19    B2              B4              B4              B2
  83         TX20    B3              B5              B5              B3
  84         TX21    B4              B6              B6              B4
  85 Y       TX22    B5              B7              B7              B5
  86 2       TX24    HSYNC           HSYNC           HSYNC           HSYNC
  87         TX25    VSYNC           VSYNC           VSYNC           VSYNC
  88         TX26    ENABLE          ENABLE          ENABLE          ENABLE
  89 ----------------------------------------------------------------------
  90         TX27    R6              R0              GND             GND
  91         TX5     R7              R1              GND             GND
  92         TX10    G6              G0              GND             GND
  93 Y       TX11    G7              G1              GND             GND
  94 3       TX16    B6              B0              GND             GND
  95         TX17    B7              B1              GND             GND
  96         TX23    RSVD            RSVD            RSVD            RSVD
  97 ----------------------------------------------------------------------
  98 */
  99
 100 #endif