include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi

   1 /*
   2  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   3  *
   4  * This file is dual-licensed: you can use it either under the terms
   5  * of the GPL or the X11 license, at your option. Note that this dual
   6  * licensing only applies to this file, and not this project as a
   7  * whole.
   8  *
   9  *  a) This file is free software; you can redistribute it and/or
  10  *     modify it under the terms of the GNU General Public License as
  11  *     published by the Free Software Foundation; either version 2 of the
  12  *     License, or (at your option) any later version.
  13  *
  14  *     This file is distributed in the hope that it will be useful,
  15  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  *     GNU General Public License for more details.
  18  *
  19  * Or, alternatively,
  20  *
  21  *  b) Permission is hereby granted, free of charge, to any person
  22  *     obtaining a copy of this software and associated documentation
  23  *     files (the "Software"), to deal in the Software without
  24  *     restriction, including without limitation the rights to use,
  25  *     copy, modify, merge, publish, distribute, sublicense, and/or
  26  *     sell copies of the Software, and to permit persons to whom the
  27  *     Software is furnished to do so, subject to the following
  28  *     conditions:
  29  *
  30  *     The above copyright notice and this permission notice shall be
  31  *     included in all copies or substantial portions of the Software.
  32  *
  33  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  34  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  35  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  36  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  37  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  38  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  39  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  40  *     OTHER DEALINGS IN THE SOFTWARE.
  41  *
  42  * include/dt-bindings/display/screen-timing/lcd-ls055r1sx04-mipi.dtsi
  43  * author: xbl@rock-chips.com
  44  * create date: 2016-05-16
  45  * lcd model: sharp ls055r1sx04
  46  * resolution: 1440 * 2560
  47  * mipi channel: double
  48  */
  49
  50 /* about mipi */
  51 disp_mipi_init: mipi_dsi_init{
  52         compatible = "rockchip,mipi_dsi_init";
  53         rockchip,screen_init    = <1>;
  54         rockchip,dsi_lane       = <4>;
  55         rockchip,dsi_hs_clk     = <850>;
  56         rockchip,mipi_dsi_num   = <2>;
  57 };
  58
  59 disp_mipi_power_ctr: mipi_power_ctr {
  60         compatible = "rockchip,mipi_power_ctr";
  61         /* mipi_lcd_rst:mipi_lcd_rst{
  62                         compatible = "rockchip,lcd_rst";
  63                         rockchip,gpios = <&gpio2 GPIO_B7 GPIO_ACTIVE_LOW>;
  64                         rockchip,delay = <100>;
  65         };
  66         mipi_lcd_en:mipi_lcd_en {
  67                         compatible = "rockchip,lcd_en";
  68                         rockchip,gpios = <&gpio0 GPIO_C1 GPIO_ACTIVE_HIGH>;
  69                         rockchip,delay = <100>;
  70         };
  71         */
  72 };
  73
  74 disp_mipi_init_cmds: screen-on-cmds {
  75         compatible = "rockchip,screen-on-cmds";
  76         rockchip,cmd_debug = <1>;
  77         rockchip,on-cmds1 {
  78                         compatible = "rockchip,on-cmds";
  79                         rockchip,cmd_type = <LPDT>;
  80                         rockchip,dsi_id = <2>;
  81                         rockchip,cmd = <0x29 0xb0 0x00>;
  82                         rockchip,cmd_delay = <0>;
  83         };
  84         rockchip,on-cmds2 {
  85                         compatible = "rockchip,on-cmds";
  86                         rockchip,cmd_type = <LPDT>;
  87                         rockchip,dsi_id = <2>;
  88                         rockchip,cmd = <0x29 0xd6 0x01>;
  89                         rockchip,cmd_delay = <0>;
  90         };
  91         rockchip,on-cmds3 {
  92                         compatible = "rockchip,on-cmds";
  93                         rockchip,cmd_type = <LPDT>;
  94                         rockchip,dsi_id = <2>;
  95                         rockchip,cmd = <0x29 0xb3 0x18>;
  96                         rockchip,cmd_delay = <0>;
  97         };
  98         rockchip,on-cmds4 {
  99                         compatible = "rockchip,on-cmds";
 100                         rockchip,cmd_type = <LPDT>;
 101                         rockchip,dsi_id = <2>;
 102                         rockchip,cmd = <0x39 0x51 0xff>;
 103                         rockchip,cmd_delay = <0>;
 104         };
 105         rockchip,on-cmds5 {
 106                         compatible = "rockchip,on-cmds";
 107                         rockchip,cmd_type = <LPDT>;
 108                         rockchip,dsi_id = <2>;
 109                         rockchip,cmd = <0x39 0x53 0x0c>;
 110                         rockchip,cmd_delay = <0>;
 111         };
 112         rockchip,on-cmds6 {
 113                         compatible = "rockchip,on-cmds";
 114                         rockchip,cmd_type = <LPDT>;
 115                         rockchip,dsi_id = <2>;
 116                         rockchip,cmd = <0x39 0x35 0x00>;
 117                         rockchip,cmd_delay = <0>;
 118         };
 119 /*
 120         rockchip,on-cmds7 {
 121                         compatible = "rockchip,on-cmds";
 122                         rockchip,cmd_type = <LPDT>;
 123                         rockchip,dsi_id = <2>;
 124                         rockchip,cmd = <0x29 0xb0 0x03>;
 125                         rockchip,cmd_delay = <0>;
 126         };
 127 */
 128         rockchip,on-cmds7 {
 129                         compatible = "rockchip,on-cmds";
 130                         rockchip,cmd_type = <LPDT>;
 131                         rockchip,dsi_id = <2>;
 132                         rockchip,cmd = <0x05 dcs_set_display_on>;
 133                         rockchip,cmd_delay = <10>;
 134         };
 135         rockchip,on-cmds8 {
 136                         compatible = "rockchip,on-cmds";
 137                         rockchip,cmd_type = <LPDT>;
 138                         rockchip,dsi_id = <2>;
 139                         rockchip,cmd = <0x05 dcs_exit_sleep_mode>;
 140                         rockchip,cmd_delay = <10>;
 141         };
 142 };
 143
 144 disp_timings: display-timings {
 145         native-mode = <&timing0>;
 146         compatible = "rockchip,display-timings";
 147         timing0: timing0 {
 148                 screen-type = <SCREEN_DUAL_MIPI>;
 149                 lvds-format = <LVDS_8BIT_2>;
 150                 out-face    = <OUT_P888>;
 151                 clock-frequency = <245000000>;
 152                 hactive = <1440>;
 153                 vactive = <2560>;
 154                 hback-porch = <40>;
 155                 hfront-porch = <100>;
 156                 vback-porch = <3>;
 157                 vfront-porch = <4>;
 158                 hsync-len = <6>;
 159                 vsync-len = <1>;
 160                 hsync-active = <0>;
 161                 vsync-active = <0>;
 162                 de-active = <0>;
 163                 pixelclk-active = <0>;
 164                 swap-rb = <0>;
 165                 swap-rg = <0>;
 166                 swap-gb = <0>;
 167         };
 168 };