1 #ifndef _DT_BINDINGS_CLOCK_ROCKCHIP_H
2 #define _DT_BINDINGS_CLOCK_ROCKCHIP_H
5 #define BIT(nr) (1 << (nr))
8 #define CLK_DIVIDER_PLUS_ONE (0)
9 #define CLK_DIVIDER_ONE_BASED BIT(0)
10 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
11 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
12 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
14 /* Rockchip special defined */
15 //#define CLK_DIVIDER_FIXED BIT(6)
16 #define CLK_DIVIDER_USER_DEFINE BIT(7)
19 * flags used across common struct clk. these flags should only affect the
20 * top-level framework. custom flags for dealing with hardware specifics
21 * belong in struct clk_foo
23 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
24 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
25 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
26 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
27 #define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
28 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
29 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
30 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 #define CLK_SET_RATE_PARENT_IN_ORDER BIT(8) /* consider the order of re-parent
32 and set_div on rate change */
36 /* Rockchip pll flags */
37 #define CLK_PLL_3188 BIT(0)
38 #define CLK_PLL_3188_APLL BIT(1)
39 #define CLK_PLL_3188PLUS BIT(2)
40 #define CLK_PLL_3188PLUS_APLL BIT(3)
41 #define CLK_PLL_3288_APLL BIT(4)
42 #define CLK_PLL_3188PLUS_AUTO BIT(5)
43 #define CLK_PLL_3036_APLL BIT(6)
44 #define CLK_PLL_3036PLUS_AUTO BIT(7)
45 #define CLK_PLL_312XPLUS BIT(8)
46 #define CLK_PLL_3368_APLLB BIT(9)
47 #define CLK_PLL_3368_APLLL BIT(10)
48 #define CLK_PLL_3368_LOW_JITTER BIT(11)
52 #define CLKOPS_RATE_MUX_DIV 1
53 #define CLKOPS_RATE_EVENDIV 2
54 #define CLKOPS_RATE_MUX_EVENDIV 3
55 #define CLKOPS_RATE_I2S_FRAC 4
56 #define CLKOPS_RATE_FRAC 5
57 #define CLKOPS_RATE_I2S 6
58 #define CLKOPS_RATE_CIFOUT 7
59 #define CLKOPS_RATE_UART 8
60 #define CLKOPS_RATE_HSADC 9
61 #define CLKOPS_RATE_MAC_REF 10
62 #define CLKOPS_RATE_CORE 11
63 #define CLKOPS_RATE_CORE_CHILD 12
64 #define CLKOPS_RATE_DDR 13
65 #define CLKOPS_RATE_RK3288_I2S 14
66 #define CLKOPS_RATE_RK3288_USB480M 15
67 #define CLKOPS_RATE_RK3288_DCLK_LCDC0 16
68 #define CLKOPS_RATE_RK3288_DCLK_LCDC1 17
69 #define CLKOPS_RATE_DDR_DIV2 18
70 #define CLKOPS_RATE_DDR_DIV4 19
71 #define CLKOPS_RATE_RK3368_MUX_DIV_NPLL 20
72 #define CLKOPS_RATE_RK3368_DCLK_LCDC 21
73 #define CLKOPS_RATE_RK3368_DDR 22
75 #define CLKOPS_TABLE_END (~0)
81 #define CLK_PD_CPU_0 3
82 #define CLK_PD_CPU_1 4
83 #define CLK_PD_CPU_2 5
84 #define CLK_PD_CPU_3 6
88 #define CLK_PD_PERI 10
90 #define CLK_PD_VIDEO 12
92 #define CLK_PD_GPU_0 14
93 #define CLK_PD_GPU_1 15
95 #define CLK_PD_VIRT 255
98 #define ROCKCHIP_RESET_HIWORD_MASK BIT(0)
100 #endif /* _DT_BINDINGS_CLOCK_ROCKCHIP_H */