2 * Copyright (c) 2015 Rockchip Electronics Co. Ltd.
3 * Author: Jeffy Chen <jeffy.chen@rock-chips.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
17 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3228_H
26 /* sclk gates (special clocks) */
40 #define SCLK_TIMER0 85
41 #define SCLK_TIMER1 86
42 #define SCLK_TIMER2 87
43 #define SCLK_TIMER3 88
44 #define SCLK_TIMER4 89
45 #define SCLK_TIMER5 90
46 #define SCLK_I2S_OUT 113
47 #define SCLK_SDMMC_DRV 114
48 #define SCLK_SDIO_DRV 115
49 #define SCLK_EMMC_DRV 117
50 #define SCLK_SDMMC_SAMPLE 118
51 #define SCLK_SDIO_SAMPLE 119
52 #define SCLK_EMMC_SAMPLE 121
64 #define PCLK_GPIO0 320
65 #define PCLK_GPIO1 321
66 #define PCLK_GPIO2 322
67 #define PCLK_GPIO3 323
74 #define PCLK_UART0 341
75 #define PCLK_UART1 342
76 #define PCLK_UART2 343
77 #define PCLK_TSADC 344
79 #define PCLK_TIMER 353
84 #define HCLK_NANDC 453
85 #define HCLK_SDMMC 456
90 #define CLK_NR_CLKS (HCLK_PERI + 1)
92 /* soft-reset indices */
93 #define SRST_CORE0_PO 0
94 #define SRST_CORE1_PO 1
95 #define SRST_CORE2_PO 2
96 #define SRST_CORE3_PO 3
101 #define SRST_CORE0_DBG 8
102 #define SRST_CORE1_DBG 9
103 #define SRST_CORE2_DBG 10
104 #define SRST_CORE3_DBG 11
105 #define SRST_TOPDBG 12
106 #define SRST_ACLK_CORE 13
110 #define SRST_CPUSYS_H 18
111 #define SRST_BUSSYS_H 19
112 #define SRST_SPDIF 20
113 #define SRST_INTMEM 21
115 #define SRST_OTG_ADP 23
119 #define SRST_ACODEC_P 27
120 #define SRST_DFIMON 28
122 #define SRST_EFUSE1024 30
123 #define SRST_EFUSE256 31
125 #define SRST_GPIO0 32
126 #define SRST_GPIO1 33
127 #define SRST_GPIO2 34
128 #define SRST_GPIO3 35
129 #define SRST_PERIPH_NOC_A 36
130 #define SRST_PERIPH_NOC_BUS_H 37
131 #define SRST_PERIPH_NOC_P 38
132 #define SRST_UART0 39
133 #define SRST_UART1 40
134 #define SRST_UART2 41
135 #define SRST_PHYNOC 42
142 #define SRST_A53_GIC 49
144 #define SRST_DAP_NOC 52
145 #define SRST_CRYPTO 53
149 #define SRST_PERIPH_NOC_H 58
150 #define SRST_MACPHY 63
153 #define SRST_NANDC 68
154 #define SRST_USBOTG 69
156 #define SRST_USBHOST0 71
157 #define SRST_HOST_CTRL0 72
158 #define SRST_USBHOST1 73
159 #define SRST_HOST_CTRL1 74
160 #define SRST_USBHOST2 75
161 #define SRST_HOST_CTRL2 76
162 #define SRST_USBPOR0 77
163 #define SRST_USBPOR1 78
164 #define SRST_DDRMSCH 79
166 #define SRST_SMART_CARD 80
167 #define SRST_SDMMC 81
171 #define SRST_TSP_H 85
173 #define SRST_TSADC 87
174 #define SRST_DDRPHY 88
175 #define SRST_DDRPHY_P 89
176 #define SRST_DDRCTRL 90
177 #define SRST_DDRCTRL_P 91
178 #define SRST_HOST0_ECHI 92
179 #define SRST_HOST1_ECHI 93
180 #define SRST_HOST2_ECHI 94
181 #define SRST_VOP_NOC_A 95
183 #define SRST_HDMI_P 96
184 #define SRST_VIO_ARBI_H 97
185 #define SRST_IEP_NOC_A 98
186 #define SRST_VIO_NOC_H 99
187 #define SRST_VOP_A 100
188 #define SRST_VOP_H 101
189 #define SRST_VOP_D 102
190 #define SRST_UTMI0 103
191 #define SRST_UTMI1 104
192 #define SRST_UTMI2 105
193 #define SRST_UTMI3 106
195 #define SRST_RGA_NOC_A 108
196 #define SRST_RGA_A 109
197 #define SRST_RGA_H 110
198 #define SRST_HDCP_A 111
200 #define SRST_VPU_A 112
201 #define SRST_VPU_H 113
202 #define SRST_VPU_NOC_A 116
203 #define SRST_VPU_NOC_H 117
204 #define SRST_RKVDEC_A 118
205 #define SRST_RKVDEC_NOC_A 119
206 #define SRST_RKVDEC_H 120
207 #define SRST_RKVDEC_NOC_H 121
208 #define SRST_RKVDEC_CORE 122
209 #define SRST_RKVDEC_CABAC 123
210 #define SRST_IEP_A 124
211 #define SRST_IEP_H 125
212 #define SRST_GPU_A 126
213 #define SRST_GPU_NOC_A 127
215 #define SRST_CORE_DBG 128
216 #define SRST_DBG_P 129
217 #define SRST_TIMER0 130
218 #define SRST_TIMER1 131
219 #define SRST_TIMER2 132
220 #define SRST_TIMER3 133
221 #define SRST_TIMER4 134
222 #define SRST_TIMER5 135
223 #define SRST_VIO_H2P 136
224 #define SRST_HDMIPHY 139
225 #define SRST_VDAC 140
226 #define SRST_TIMER_6CH_P 141