include/dt-bindings/clock/exynos5433.h

   1 /*
   2  * Copyright (c) 2014 Samsung Electronics Co., Ltd.
   3  * Author: Chanwoo Choi <cw00.choi@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #ifndef _DT_BINDINGS_CLOCK_EXYNOS5433_H
  11 #define _DT_BINDINGS_CLOCK_EXYNOS5433_H
  12
  13 /* CMU_TOP */
  14 #define CLK_FOUT_ISP_PLL                1
  15 #define CLK_FOUT_AUD_PLL                2
  16
  17 #define CLK_MOUT_AUD_PLL                10
  18 #define CLK_MOUT_ISP_PLL                11
  19 #define CLK_MOUT_AUD_PLL_USER_T         12
  20 #define CLK_MOUT_MPHY_PLL_USER          13
  21 #define CLK_MOUT_MFC_PLL_USER           14
  22 #define CLK_MOUT_BUS_PLL_USER           15
  23 #define CLK_MOUT_ACLK_HEVC_400          16
  24 #define CLK_MOUT_ACLK_CAM1_333          17
  25 #define CLK_MOUT_ACLK_CAM1_552_B        18
  26 #define CLK_MOUT_ACLK_CAM1_552_A        19
  27 #define CLK_MOUT_ACLK_ISP_DIS_400       20
  28 #define CLK_MOUT_ACLK_ISP_400           21
  29 #define CLK_MOUT_ACLK_BUS0_400          22
  30 #define CLK_MOUT_ACLK_MSCL_400_B        23
  31 #define CLK_MOUT_ACLK_MSCL_400_A        24
  32 #define CLK_MOUT_ACLK_GSCL_333          25
  33 #define CLK_MOUT_ACLK_G2D_400_B         26
  34 #define CLK_MOUT_ACLK_G2D_400_A         27
  35 #define CLK_MOUT_SCLK_JPEG_C            28
  36 #define CLK_MOUT_SCLK_JPEG_B            29
  37 #define CLK_MOUT_SCLK_JPEG_A            30
  38 #define CLK_MOUT_SCLK_MMC2_B            31
  39 #define CLK_MOUT_SCLK_MMC2_A            32
  40 #define CLK_MOUT_SCLK_MMC1_B            33
  41 #define CLK_MOUT_SCLK_MMC1_A            34
  42 #define CLK_MOUT_SCLK_MMC0_D            35
  43 #define CLK_MOUT_SCLK_MMC0_C            36
  44 #define CLK_MOUT_SCLK_MMC0_B            37
  45 #define CLK_MOUT_SCLK_MMC0_A            38
  46 #define CLK_MOUT_SCLK_SPI4              39
  47 #define CLK_MOUT_SCLK_SPI3              40
  48 #define CLK_MOUT_SCLK_UART2             41
  49 #define CLK_MOUT_SCLK_UART1             42
  50 #define CLK_MOUT_SCLK_UART0             43
  51 #define CLK_MOUT_SCLK_SPI2              44
  52 #define CLK_MOUT_SCLK_SPI1              45
  53 #define CLK_MOUT_SCLK_SPI0              46
  54 #define CLK_MOUT_ACLK_MFC_400_C         47
  55 #define CLK_MOUT_ACLK_MFC_400_B         48
  56 #define CLK_MOUT_ACLK_MFC_400_A         49
  57 #define CLK_MOUT_SCLK_ISP_SENSOR2       50
  58 #define CLK_MOUT_SCLK_ISP_SENSOR1       51
  59 #define CLK_MOUT_SCLK_ISP_SENSOR0       52
  60 #define CLK_MOUT_SCLK_ISP_UART          53
  61 #define CLK_MOUT_SCLK_ISP_SPI1          54
  62 #define CLK_MOUT_SCLK_ISP_SPI0          55
  63 #define CLK_MOUT_SCLK_PCIE_100          56
  64 #define CLK_MOUT_SCLK_UFSUNIPRO         57
  65 #define CLK_MOUT_SCLK_USBHOST30         58
  66 #define CLK_MOUT_SCLK_USBDRD30          59
  67 #define CLK_MOUT_SCLK_SLIMBUS           60
  68 #define CLK_MOUT_SCLK_SPDIF             61
  69 #define CLK_MOUT_SCLK_AUDIO1            62
  70 #define CLK_MOUT_SCLK_AUDIO0            63
  71
  72 #define CLK_DIV_ACLK_FSYS_200           100
  73 #define CLK_DIV_ACLK_IMEM_SSSX_266      101
  74 #define CLK_DIV_ACLK_IMEM_200           102
  75 #define CLK_DIV_ACLK_IMEM_266           103
  76 #define CLK_DIV_ACLK_PERIC_66_B         104
  77 #define CLK_DIV_ACLK_PERIC_66_A         105
  78 #define CLK_DIV_ACLK_PERIS_66_B         106
  79 #define CLK_DIV_ACLK_PERIS_66_A         107
  80 #define CLK_DIV_SCLK_MMC1_B             108
  81 #define CLK_DIV_SCLK_MMC1_A             109
  82 #define CLK_DIV_SCLK_MMC0_B             110
  83 #define CLK_DIV_SCLK_MMC0_A             111
  84 #define CLK_DIV_SCLK_MMC2_B             112
  85 #define CLK_DIV_SCLK_MMC2_A             113
  86 #define CLK_DIV_SCLK_SPI1_B             114
  87 #define CLK_DIV_SCLK_SPI1_A             115
  88 #define CLK_DIV_SCLK_SPI0_B             116
  89 #define CLK_DIV_SCLK_SPI0_A             117
  90 #define CLK_DIV_SCLK_SPI2_B             118
  91 #define CLK_DIV_SCLK_SPI2_A             119
  92 #define CLK_DIV_SCLK_UART2              120
  93 #define CLK_DIV_SCLK_UART1              121
  94 #define CLK_DIV_SCLK_UART0              122
  95 #define CLK_DIV_SCLK_SPI4_B             123
  96 #define CLK_DIV_SCLK_SPI4_A             124
  97 #define CLK_DIV_SCLK_SPI3_B             125
  98 #define CLK_DIV_SCLK_SPI3_A             126
  99 #define CLK_DIV_SCLK_I2S1               127
 100 #define CLK_DIV_SCLK_PCM1               128
 101 #define CLK_DIV_SCLK_AUDIO1             129
 102 #define CLK_DIV_SCLK_AUDIO0             130
 103 #define CLK_DIV_ACLK_GSCL_111           131
 104 #define CLK_DIV_ACLK_GSCL_333           132
 105 #define CLK_DIV_ACLK_HEVC_400           133
 106 #define CLK_DIV_ACLK_MFC_400            134
 107 #define CLK_DIV_ACLK_G2D_266            135
 108 #define CLK_DIV_ACLK_G2D_400            136
 109
 110 #define CLK_ACLK_PERIC_66               200
 111 #define CLK_ACLK_PERIS_66               201
 112 #define CLK_ACLK_FSYS_200               202
 113 #define CLK_SCLK_MMC2_FSYS              203
 114 #define CLK_SCLK_MMC1_FSYS              204
 115 #define CLK_SCLK_MMC0_FSYS              205
 116 #define CLK_SCLK_SPI4_PERIC             206
 117 #define CLK_SCLK_SPI3_PERIC             207
 118 #define CLK_SCLK_UART2_PERIC            208
 119 #define CLK_SCLK_UART1_PERIC            209
 120 #define CLK_SCLK_UART0_PERIC            210
 121 #define CLK_SCLK_SPI2_PERIC             211
 122 #define CLK_SCLK_SPI1_PERIC             212
 123 #define CLK_SCLK_SPI0_PERIC             213
 124 #define CLK_SCLK_SPDIF_PERIC            214
 125 #define CLK_SCLK_I2S1_PERIC             215
 126 #define CLK_SCLK_PCM1_PERIC             216
 127 #define CLK_SCLK_SLIMBUS                217
 128 #define CLK_SCLK_AUDIO1                 218
 129 #define CLK_SCLK_AUDIO0                 219
 130 #define CLK_ACLK_G2D_266                220
 131 #define CLK_ACLK_G2D_400                221
 132
 133 #define TOP_NR_CLK                      222
 134
 135 /* CMU_CPIF */
 136 #define CLK_FOUT_MPHY_PLL               1
 137
 138 #define CLK_MOUT_MPHY_PLL               2
 139
 140 #define CLK_DIV_SCLK_MPHY               10
 141
 142 #define CLK_SCLK_MPHY_PLL               11
 143 #define CLK_SCLK_UFS_MPHY               11
 144
 145 #define CPIF_NR_CLK                     12
 146
 147 /* CMU_MIF */
 148 #define CLK_FOUT_MEM0_PLL               1
 149 #define CLK_FOUT_MEM1_PLL               2
 150 #define CLK_FOUT_BUS_PLL                3
 151 #define CLK_FOUT_MFC_PLL                4
 152
 153 #define MIF_NR_CLK                      5
 154
 155 /* CMU_PERIC */
 156 #define CLK_PCLK_SPI2                   1
 157 #define CLK_PCLK_SPI1                   2
 158 #define CLK_PCLK_SPI0                   3
 159 #define CLK_PCLK_UART2                  4
 160 #define CLK_PCLK_UART1                  5
 161 #define CLK_PCLK_UART0                  6
 162 #define CLK_PCLK_HSI2C3                 7
 163 #define CLK_PCLK_HSI2C2                 8
 164 #define CLK_PCLK_HSI2C1                 9
 165 #define CLK_PCLK_HSI2C0                 10
 166 #define CLK_PCLK_I2C7                   11
 167 #define CLK_PCLK_I2C6                   12
 168 #define CLK_PCLK_I2C5                   13
 169 #define CLK_PCLK_I2C4                   14
 170 #define CLK_PCLK_I2C3                   15
 171 #define CLK_PCLK_I2C2                   16
 172 #define CLK_PCLK_I2C1                   17
 173 #define CLK_PCLK_I2C0                   18
 174 #define CLK_PCLK_SPI4                   19
 175 #define CLK_PCLK_SPI3                   20
 176 #define CLK_PCLK_HSI2C11                21
 177 #define CLK_PCLK_HSI2C10                22
 178 #define CLK_PCLK_HSI2C9                 23
 179 #define CLK_PCLK_HSI2C8                 24
 180 #define CLK_PCLK_HSI2C7                 25
 181 #define CLK_PCLK_HSI2C6                 26
 182 #define CLK_PCLK_HSI2C5                 27
 183 #define CLK_PCLK_HSI2C4                 28
 184 #define CLK_SCLK_SPI4                   29
 185 #define CLK_SCLK_SPI3                   30
 186 #define CLK_SCLK_SPI2                   31
 187 #define CLK_SCLK_SPI1                   32
 188 #define CLK_SCLK_SPI0                   33
 189 #define CLK_SCLK_UART2                  34
 190 #define CLK_SCLK_UART1                  35
 191 #define CLK_SCLK_UART0                  36
 192 #define CLK_ACLK_AHB2APB_PERIC2P        37
 193 #define CLK_ACLK_AHB2APB_PERIC1P        38
 194 #define CLK_ACLK_AHB2APB_PERIC0P        39
 195 #define CLK_ACLK_PERICNP_66             40
 196 #define CLK_PCLK_SCI                    41
 197 #define CLK_PCLK_GPIO_FINGER            42
 198 #define CLK_PCLK_GPIO_ESE               43
 199 #define CLK_PCLK_PWM                    44
 200 #define CLK_PCLK_SPDIF                  45
 201 #define CLK_PCLK_PCM1                   46
 202 #define CLK_PCLK_I2S1                   47
 203 #define CLK_PCLK_ADCIF                  48
 204 #define CLK_PCLK_GPIO_TOUCH             49
 205 #define CLK_PCLK_GPIO_NFC               50
 206 #define CLK_PCLK_GPIO_PERIC             51
 207 #define CLK_PCLK_PMU_PERIC              52
 208 #define CLK_PCLK_SYSREG_PERIC           53
 209 #define CLK_SCLK_IOCLK_SPI4             54
 210 #define CLK_SCLK_IOCLK_SPI3             55
 211 #define CLK_SCLK_SCI                    56
 212 #define CLK_SCLK_SC_IN                  57
 213 #define CLK_SCLK_PWM                    58
 214 #define CLK_SCLK_IOCLK_SPI2             59
 215 #define CLK_SCLK_IOCLK_SPI1             60
 216 #define CLK_SCLK_IOCLK_SPI0             61
 217 #define CLK_SCLK_IOCLK_I2S1_BCLK        62
 218 #define CLK_SCLK_SPDIF                  63
 219 #define CLK_SCLK_PCM1                   64
 220 #define CLK_SCLK_I2S1                   65
 221
 222 #define CLK_DIV_SCLK_SCI                70
 223 #define CLK_DIV_SCLK_SC_IN              71
 224
 225 #define PERIC_NR_CLK                    72
 226
 227 /* CMU_PERIS */
 228 #define CLK_PCLK_HPM_APBIF              1
 229 #define CLK_PCLK_TMU1_APBIF             2
 230 #define CLK_PCLK_TMU0_APBIF             3
 231 #define CLK_PCLK_PMU_PERIS              4
 232 #define CLK_PCLK_SYSREG_PERIS           5
 233 #define CLK_PCLK_CMU_TOP_APBIF          6
 234 #define CLK_PCLK_WDT_APOLLO             7
 235 #define CLK_PCLK_WDT_ATLAS              8
 236 #define CLK_PCLK_MCT                    9
 237 #define CLK_PCLK_HDMI_CEC               10
 238 #define CLK_ACLK_AHB2APB_PERIS1P        11
 239 #define CLK_ACLK_AHB2APB_PERIS0P        12
 240 #define CLK_ACLK_PERISNP_66             13
 241 #define CLK_PCLK_TZPC12                 14
 242 #define CLK_PCLK_TZPC11                 15
 243 #define CLK_PCLK_TZPC10                 16
 244 #define CLK_PCLK_TZPC9                  17
 245 #define CLK_PCLK_TZPC8                  18
 246 #define CLK_PCLK_TZPC7                  19
 247 #define CLK_PCLK_TZPC6                  20
 248 #define CLK_PCLK_TZPC5                  21
 249 #define CLK_PCLK_TZPC4                  22
 250 #define CLK_PCLK_TZPC3                  23
 251 #define CLK_PCLK_TZPC2                  24
 252 #define CLK_PCLK_TZPC1                  25
 253 #define CLK_PCLK_TZPC0                  26
 254 #define CLK_PCLK_SECKEY_APBIF           27
 255 #define CLK_PCLK_CHIPID_APBIF           28
 256 #define CLK_PCLK_TOPRTC                 29
 257 #define CLK_PCLK_CUSTOM_EFUSE_APBIF     30
 258 #define CLK_PCLK_ANTIRBK_CNT_APBIF      31
 259 #define CLK_PCLK_OTP_CON_APBIF          32
 260 #define CLK_SCLK_ASV_TB                 33
 261 #define CLK_SCLK_TMU1                   34
 262 #define CLK_SCLK_TMU0                   35
 263 #define CLK_SCLK_SECKEY                 36
 264 #define CLK_SCLK_CHIPID                 37
 265 #define CLK_SCLK_TOPRTC                 38
 266 #define CLK_SCLK_CUSTOM_EFUSE           39
 267 #define CLK_SCLK_ANTIRBK_CNT            40
 268 #define CLK_SCLK_OTP_CON                41
 269
 270 #define PERIS_NR_CLK                    42
 271
 272 /* CMU_FSYS */
 273 #define CLK_MOUT_ACLK_FSYS_200_USER     1
 274 #define CLK_MOUT_SCLK_MMC2_USER         2
 275 #define CLK_MOUT_SCLK_MMC1_USER         3
 276 #define CLK_MOUT_SCLK_MMC0_USER         4
 277
 278 #define CLK_ACLK_PCIE                   50
 279 #define CLK_ACLK_PDMA1                  51
 280 #define CLK_ACLK_TSI                    52
 281 #define CLK_ACLK_MMC2                   53
 282 #define CLK_ACLK_MMC1                   54
 283 #define CLK_ACLK_MMC0                   55
 284 #define CLK_ACLK_UFS                    56
 285 #define CLK_ACLK_USBHOST20              57
 286 #define CLK_ACLK_USBHOST30              58
 287 #define CLK_ACLK_USBDRD30               59
 288 #define CLK_ACLK_PDMA0                  60
 289 #define CLK_SCLK_MMC2                   61
 290 #define CLK_SCLK_MMC1                   62
 291 #define CLK_SCLK_MMC0                   63
 292 #define CLK_PDMA1                       64
 293 #define CLK_PDMA0                       65
 294
 295 #define FSYS_NR_CLK                     66
 296
 297 /* CMU_G2D */
 298 #define CLK_MUX_ACLK_G2D_266_USER       1
 299 #define CLK_MUX_ACLK_G2D_400_USER       2
 300
 301 #define CLK_DIV_PCLK_G2D                3
 302
 303 #define CLK_ACLK_SMMU_MDMA1             4
 304 #define CLK_ACLK_BTS_MDMA1              5
 305 #define CLK_ACLK_BTS_G2D                6
 306 #define CLK_ACLK_ALB_G2D                7
 307 #define CLK_ACLK_AXIUS_G2DX             8
 308 #define CLK_ACLK_ASYNCAXI_SYSX          9
 309 #define CLK_ACLK_AHB2APB_G2D1P          10
 310 #define CLK_ACLK_AHB2APB_G2D0P          11
 311 #define CLK_ACLK_XIU_G2DX               12
 312 #define CLK_ACLK_G2DNP_133              13
 313 #define CLK_ACLK_G2DND_400              14
 314 #define CLK_ACLK_MDMA1                  15
 315 #define CLK_ACLK_G2D                    16
 316 #define CLK_ACLK_SMMU_G2D               17
 317 #define CLK_PCLK_SMMU_MDMA1             18
 318 #define CLK_PCLK_BTS_MDMA1              19
 319 #define CLK_PCLK_BTS_G2D                20
 320 #define CLK_PCLK_ALB_G2D                21
 321 #define CLK_PCLK_ASYNCAXI_SYSX          22
 322 #define CLK_PCLK_PMU_G2D                23
 323 #define CLK_PCLK_SYSREG_G2D             24
 324 #define CLK_PCLK_G2D                    25
 325 #define CLK_PCLK_SMMU_G2D               26
 326
 327 #define G2D_NR_CLK                      27
 328
 329 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */