2 * PowerPC memory management structures
9 #include <linux/config.h>
14 * Define physical address type. Machines using split size
15 * virtual/physical addressing like 32-bit virtual / 36-bit
16 * physical need a larger than native word size type. -Matt
18 #ifndef CONFIG_PHYS_64BIT
19 typedef unsigned long phys_addr_t;
20 #define PHYS_FMT "%.8lx"
22 typedef unsigned long long phys_addr_t;
23 extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
24 #define PHYS_FMT "%16Lx"
29 unsigned long vdso_base;
32 /* Hardware Page Table Entry */
34 #ifdef CONFIG_PPC64BRIDGE
35 unsigned long long vsid:52;
40 unsigned long long rpn:52;
41 #else /* CONFIG_PPC64BRIDGE */
42 unsigned long v:1; /* Entry is valid */
43 unsigned long vsid:24; /* Virtual segment identifier */
44 unsigned long h:1; /* Hash algorithm indicator */
45 unsigned long api:6; /* Abbreviated page index */
46 unsigned long rpn:20; /* Real (physical) page number */
47 #endif /* CONFIG_PPC64BRIDGE */
48 unsigned long :3; /* Unused */
49 unsigned long r:1; /* Referenced */
50 unsigned long c:1; /* Changed */
51 unsigned long w:1; /* Write-thru cache mode */
52 unsigned long i:1; /* Cache inhibited */
53 unsigned long m:1; /* Memory coherence */
54 unsigned long g:1; /* Guarded */
55 unsigned long :1; /* Unused */
56 unsigned long pp:2; /* Page protection */
59 /* Values for PP (assumes Ks=0, Kp=1) */
60 #define PP_RWXX 0 /* Supervisor read/write, User none */
61 #define PP_RWRX 1 /* Supervisor read/write, User read */
62 #define PP_RWRW 2 /* Supervisor read/write, User read/write */
63 #define PP_RXRX 3 /* Supervisor read, User read */
65 /* Segment Register */
66 typedef struct _SEGREG {
67 unsigned long t:1; /* Normal or I/O type */
68 unsigned long ks:1; /* Supervisor 'key' (normally 0) */
69 unsigned long kp:1; /* User 'key' (normally 1) */
70 unsigned long n:1; /* No-execute */
71 unsigned long :4; /* Unused */
72 unsigned long vsid:24; /* Virtual Segment Identifier */
75 /* Block Address Translation (BAT) Registers */
76 typedef struct _P601_BATU { /* Upper part of BAT for 601 processor */
77 unsigned long bepi:15; /* Effective page index (virtual address) */
78 unsigned long :8; /* unused */
80 unsigned long i:1; /* Cache inhibit */
81 unsigned long m:1; /* Memory coherence */
82 unsigned long ks:1; /* Supervisor key (normally 0) */
83 unsigned long kp:1; /* User key (normally 1) */
84 unsigned long pp:2; /* Page access protections */
87 typedef struct _BATU { /* Upper part of BAT (all except 601) */
88 #ifdef CONFIG_PPC64BRIDGE
89 unsigned long long bepi:47;
90 #else /* CONFIG_PPC64BRIDGE */
91 unsigned long bepi:15; /* Effective page index (virtual address) */
92 #endif /* CONFIG_PPC64BRIDGE */
93 unsigned long :4; /* Unused */
94 unsigned long bl:11; /* Block size mask */
95 unsigned long vs:1; /* Supervisor valid */
96 unsigned long vp:1; /* User valid */
99 typedef struct _P601_BATL { /* Lower part of BAT for 601 processor */
100 unsigned long brpn:15; /* Real page index (physical address) */
101 unsigned long :10; /* Unused */
102 unsigned long v:1; /* Valid bit */
103 unsigned long bl:6; /* Block size mask */
106 typedef struct _BATL { /* Lower part of BAT (all except 601) */
107 #ifdef CONFIG_PPC64BRIDGE
108 unsigned long long brpn:47;
109 #else /* CONFIG_PPC64BRIDGE */
110 unsigned long brpn:15; /* Real page index (physical address) */
111 #endif /* CONFIG_PPC64BRIDGE */
112 unsigned long :10; /* Unused */
113 unsigned long w:1; /* Write-thru cache */
114 unsigned long i:1; /* Cache inhibit */
115 unsigned long m:1; /* Memory coherence */
116 unsigned long g:1; /* Guarded (MBZ in IBAT) */
117 unsigned long :1; /* Unused */
118 unsigned long pp:2; /* Page access protections */
121 typedef struct _BAT {
122 BATU batu; /* Upper register */
123 BATL batl; /* Lower register */
126 typedef struct _P601_BAT {
127 P601_BATU batu; /* Upper register */
128 P601_BATL batl; /* Lower register */
131 #endif /* __ASSEMBLY__ */
133 /* Block size masks */
134 #define BL_128K 0x000
135 #define BL_256K 0x001
136 #define BL_512K 0x003
144 #define BL_128M 0x3FF
145 #define BL_256M 0x7FF
147 /* BAT Access Protection */
148 #define BPP_XX 0x00 /* No access */
149 #define BPP_RX 0x01 /* Read only */
150 #define BPP_RW 0x02 /* Read/write */
152 /* Control/status registers for the MPC8xx.
153 * A write operation to these registers causes serialized access.
154 * During software tablewalk, the registers used perform mask/shift-add
155 * operations when written/read. A TLB entry is created when the Mx_RPN
156 * is written, and the contents of several registers are used to
159 #define SPRN_MI_CTR 784 /* Instruction TLB control register */
160 #define MI_GPM 0x80000000 /* Set domain manager mode */
161 #define MI_PPM 0x40000000 /* Set subpage protection */
162 #define MI_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
163 #define MI_RSV4I 0x08000000 /* Reserve 4 TLB entries */
164 #define MI_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
165 #define MI_IDXMASK 0x00001f00 /* TLB index to be loaded */
166 #define MI_RESETVAL 0x00000000 /* Value of register at reset */
168 /* These are the Ks and Kp from the PowerPC books. For proper operation,
171 #define SPRN_MI_AP 786
172 #define MI_Ks 0x80000000 /* Should not be set */
173 #define MI_Kp 0x40000000 /* Should always be set */
175 /* The effective page number register. When read, contains the information
176 * about the last instruction TLB miss. When MI_RPN is written, bits in
177 * this register are used to create the TLB entry.
179 #define SPRN_MI_EPN 787
180 #define MI_EPNMASK 0xfffff000 /* Effective page number for entry */
181 #define MI_EVALID 0x00000200 /* Entry is valid */
182 #define MI_ASIDMASK 0x0000000f /* ASID match value */
183 /* Reset value is undefined */
185 /* A "level 1" or "segment" or whatever you want to call it register.
186 * For the instruction TLB, it contains bits that get loaded into the
187 * TLB entry when the MI_RPN is written.
189 #define SPRN_MI_TWC 789
190 #define MI_APG 0x000001e0 /* Access protection group (0) */
191 #define MI_GUARDED 0x00000010 /* Guarded storage */
192 #define MI_PSMASK 0x0000000c /* Mask of page size bits */
193 #define MI_PS8MEG 0x0000000c /* 8M page size */
194 #define MI_PS512K 0x00000004 /* 512K page size */
195 #define MI_PS4K_16K 0x00000000 /* 4K or 16K page size */
196 #define MI_SVALID 0x00000001 /* Segment entry is valid */
197 /* Reset value is undefined */
199 /* Real page number. Defined by the pte. Writing this register
200 * causes a TLB entry to be created for the instruction TLB, using
201 * additional information from the MI_EPN, and MI_TWC registers.
203 #define SPRN_MI_RPN 790
205 /* Define an RPN value for mapping kernel memory to large virtual
206 * pages for boot initialization. This has real page number of 0,
207 * large page size, shared page, cache enabled, and valid.
208 * Also mark all subpages valid and write access.
210 #define MI_BOOTINIT 0x000001fd
212 #define SPRN_MD_CTR 792 /* Data TLB control register */
213 #define MD_GPM 0x80000000 /* Set domain manager mode */
214 #define MD_PPM 0x40000000 /* Set subpage protection */
215 #define MD_CIDEF 0x20000000 /* Set cache inhibit when MMU dis */
216 #define MD_WTDEF 0x10000000 /* Set writethrough when MMU dis */
217 #define MD_RSV4I 0x08000000 /* Reserve 4 TLB entries */
218 #define MD_TWAM 0x04000000 /* Use 4K page hardware assist */
219 #define MD_PPCS 0x02000000 /* Use MI_RPN prob/priv state */
220 #define MD_IDXMASK 0x00001f00 /* TLB index to be loaded */
221 #define MD_RESETVAL 0x04000000 /* Value of register at reset */
223 #define SPRN_M_CASID 793 /* Address space ID (context) to match */
224 #define MC_ASIDMASK 0x0000000f /* Bits used for ASID value */
227 /* These are the Ks and Kp from the PowerPC books. For proper operation,
230 #define SPRN_MD_AP 794
231 #define MD_Ks 0x80000000 /* Should not be set */
232 #define MD_Kp 0x40000000 /* Should always be set */
234 /* The effective page number register. When read, contains the information
235 * about the last instruction TLB miss. When MD_RPN is written, bits in
236 * this register are used to create the TLB entry.
238 #define SPRN_MD_EPN 795
239 #define MD_EPNMASK 0xfffff000 /* Effective page number for entry */
240 #define MD_EVALID 0x00000200 /* Entry is valid */
241 #define MD_ASIDMASK 0x0000000f /* ASID match value */
242 /* Reset value is undefined */
244 /* The pointer to the base address of the first level page table.
245 * During a software tablewalk, reading this register provides the address
246 * of the entry associated with MD_EPN.
248 #define SPRN_M_TWB 796
249 #define M_L1TB 0xfffff000 /* Level 1 table base address */
250 #define M_L1INDX 0x00000ffc /* Level 1 index, when read */
251 /* Reset value is undefined */
253 /* A "level 1" or "segment" or whatever you want to call it register.
254 * For the data TLB, it contains bits that get loaded into the TLB entry
255 * when the MD_RPN is written. It is also provides the hardware assist
256 * for finding the PTE address during software tablewalk.
258 #define SPRN_MD_TWC 797
259 #define MD_L2TB 0xfffff000 /* Level 2 table base address */
260 #define MD_L2INDX 0xfffffe00 /* Level 2 index (*pte), when read */
261 #define MD_APG 0x000001e0 /* Access protection group (0) */
262 #define MD_GUARDED 0x00000010 /* Guarded storage */
263 #define MD_PSMASK 0x0000000c /* Mask of page size bits */
264 #define MD_PS8MEG 0x0000000c /* 8M page size */
265 #define MD_PS512K 0x00000004 /* 512K page size */
266 #define MD_PS4K_16K 0x00000000 /* 4K or 16K page size */
267 #define MD_WT 0x00000002 /* Use writethrough page attribute */
268 #define MD_SVALID 0x00000001 /* Segment entry is valid */
269 /* Reset value is undefined */
272 /* Real page number. Defined by the pte. Writing this register
273 * causes a TLB entry to be created for the data TLB, using
274 * additional information from the MD_EPN, and MD_TWC registers.
276 #define SPRN_MD_RPN 798
278 /* This is a temporary storage register that could be used to save
279 * a processor working register during a tablewalk.
281 #define SPRN_M_TW 799
284 * At present, all PowerPC 400-class processors share a similar TLB
285 * architecture. The instruction and data sides share a unified,
286 * 64-entry, fully-associative TLB which is maintained totally under
287 * software control. In addition, the instruction side has a
288 * hardware-managed, 4-entry, fully- associative TLB which serves as a
289 * first level to the shared TLB. These two TLBs are known as the UTLB
290 * and ITLB, respectively.
293 #define PPC4XX_TLB_SIZE 64
296 * TLB entries are defined by a "high" tag portion and a "low" data
297 * portion. On all architectures, the data portion is 32-bits.
299 * TLB entries are managed entirely under software control by reading,
300 * writing, and searchoing using the 4xx-specific tlbre, tlbwr, and tlbsx
307 #define TLB_DATA TLB_LO
308 #define TLB_TAG TLB_HI
312 #define TLB_EPN_MASK 0xFFFFFC00 /* Effective Page Number */
313 #define TLB_PAGESZ_MASK 0x00000380
314 #define TLB_PAGESZ(x) (((x) & 0x7) << 7)
319 #define PAGESZ_256K 4
323 #define TLB_VALID 0x00000040 /* Entry is valid */
327 #define TLB_RPN_MASK 0xFFFFFC00 /* Real Page Number */
328 #define TLB_PERM_MASK 0x00000300
329 #define TLB_EX 0x00000200 /* Instruction execution allowed */
330 #define TLB_WR 0x00000100 /* Writes permitted */
331 #define TLB_ZSEL_MASK 0x000000F0
332 #define TLB_ZSEL(x) (((x) & 0xF) << 4)
333 #define TLB_ATTR_MASK 0x0000000F
334 #define TLB_W 0x00000008 /* Caching is write-through */
335 #define TLB_I 0x00000004 /* Caching is inhibited */
336 #define TLB_M 0x00000002 /* Memory is coherent */
337 #define TLB_G 0x00000001 /* Memory is guarded from prefetch */
342 #define PPC44x_MMUCR_TID 0x000000ff
343 #define PPC44x_MMUCR_STS 0x00010000
345 #define PPC44x_TLB_PAGEID 0
346 #define PPC44x_TLB_XLAT 1
347 #define PPC44x_TLB_ATTRIB 2
349 /* Page identification fields */
350 #define PPC44x_TLB_EPN_MASK 0xfffffc00 /* Effective Page Number */
351 #define PPC44x_TLB_VALID 0x00000200 /* Valid flag */
352 #define PPC44x_TLB_TS 0x00000100 /* Translation address space */
353 #define PPC44x_TLB_1K 0x00000000 /* Page sizes */
354 #define PPC44x_TLB_4K 0x00000010
355 #define PPC44x_TLB_16K 0x00000020
356 #define PPC44x_TLB_64K 0x00000030
357 #define PPC44x_TLB_256K 0x00000040
358 #define PPC44x_TLB_1M 0x00000050
359 #define PPC44x_TLB_16M 0x00000070
360 #define PPC44x_TLB_256M 0x00000090
362 /* Translation fields */
363 #define PPC44x_TLB_RPN_MASK 0xfffffc00 /* Real Page Number */
364 #define PPC44x_TLB_ERPN_MASK 0x0000000f
366 /* Storage attribute and access control fields */
367 #define PPC44x_TLB_ATTR_MASK 0x0000ff80
368 #define PPC44x_TLB_U0 0x00008000 /* User 0 */
369 #define PPC44x_TLB_U1 0x00004000 /* User 1 */
370 #define PPC44x_TLB_U2 0x00002000 /* User 2 */
371 #define PPC44x_TLB_U3 0x00001000 /* User 3 */
372 #define PPC44x_TLB_W 0x00000800 /* Caching is write-through */
373 #define PPC44x_TLB_I 0x00000400 /* Caching is inhibited */
374 #define PPC44x_TLB_M 0x00000200 /* Memory is coherent */
375 #define PPC44x_TLB_G 0x00000100 /* Memory is guarded */
376 #define PPC44x_TLB_E 0x00000080 /* Memory is guarded */
378 #define PPC44x_TLB_PERM_MASK 0x0000003f
379 #define PPC44x_TLB_UX 0x00000020 /* User execution */
380 #define PPC44x_TLB_UW 0x00000010 /* User write */
381 #define PPC44x_TLB_UR 0x00000008 /* User read */
382 #define PPC44x_TLB_SX 0x00000004 /* Super execution */
383 #define PPC44x_TLB_SW 0x00000002 /* Super write */
384 #define PPC44x_TLB_SR 0x00000001 /* Super read */
386 /* Book-E defined page sizes */
387 #define BOOKE_PAGESZ_1K 0
388 #define BOOKE_PAGESZ_4K 1
389 #define BOOKE_PAGESZ_16K 2
390 #define BOOKE_PAGESZ_64K 3
391 #define BOOKE_PAGESZ_256K 4
392 #define BOOKE_PAGESZ_1M 5
393 #define BOOKE_PAGESZ_4M 6
394 #define BOOKE_PAGESZ_16M 7
395 #define BOOKE_PAGESZ_64M 8
396 #define BOOKE_PAGESZ_256M 9
397 #define BOOKE_PAGESZ_1GB 10
398 #define BOOKE_PAGESZ_4GB 11
399 #define BOOKE_PAGESZ_16GB 12
400 #define BOOKE_PAGESZ_64GB 13
401 #define BOOKE_PAGESZ_256GB 14
402 #define BOOKE_PAGESZ_1TB 15
405 * Freescale Book-E MMU support
408 #define MAS0_TLBSEL(x) ((x << 28) & 0x30000000)
409 #define MAS0_ESEL(x) ((x << 16) & 0x0FFF0000)
410 #define MAS0_NV(x) ((x) & 0x00000FFF)
412 #define MAS1_VALID 0x80000000
413 #define MAS1_IPROT 0x40000000
414 #define MAS1_TID(x) ((x << 16) & 0x3FFF0000)
415 #define MAS1_TS 0x00001000
416 #define MAS1_TSIZE(x) ((x << 8) & 0x00000F00)
418 #define MAS2_EPN 0xFFFFF000
419 #define MAS2_X0 0x00000040
420 #define MAS2_X1 0x00000020
421 #define MAS2_W 0x00000010
422 #define MAS2_I 0x00000008
423 #define MAS2_M 0x00000004
424 #define MAS2_G 0x00000002
425 #define MAS2_E 0x00000001
427 #define MAS3_RPN 0xFFFFF000
428 #define MAS3_U0 0x00000200
429 #define MAS3_U1 0x00000100
430 #define MAS3_U2 0x00000080
431 #define MAS3_U3 0x00000040
432 #define MAS3_UX 0x00000020
433 #define MAS3_SX 0x00000010
434 #define MAS3_UW 0x00000008
435 #define MAS3_SW 0x00000004
436 #define MAS3_UR 0x00000002
437 #define MAS3_SR 0x00000001
439 #define MAS4_TLBSELD(x) MAS0_TLBSEL(x)
440 #define MAS4_TIDDSEL 0x000F0000
441 #define MAS4_TSIZED(x) MAS1_TSIZE(x)
442 #define MAS4_X0D 0x00000040
443 #define MAS4_X1D 0x00000020
444 #define MAS4_WD 0x00000010
445 #define MAS4_ID 0x00000008
446 #define MAS4_MD 0x00000004
447 #define MAS4_GD 0x00000002
448 #define MAS4_ED 0x00000001
450 #define MAS6_SPID0 0x3FFF0000
451 #define MAS6_SPID1 0x00007FFE
452 #define MAS6_SAS 0x00000001
453 #define MAS6_SPID MAS6_SPID0
455 #define MAS7_RPN 0xFFFFFFFF
457 #endif /* _PPC_MMU_H_ */
458 #endif /* __KERNEL__ */