2 * PCI Backend - Handles the virtual fields in the configuration space headers.
4 * Author: Ryan Wilson <hap9@epoch.ncsc.mil>
7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
9 #include <linux/kernel.h>
10 #include <linux/pci.h>
12 #include "conf_space.h"
24 #define is_enable_cmd(value) ((value)&(PCI_COMMAND_MEMORY|PCI_COMMAND_IO))
25 #define is_master_cmd(value) ((value)&PCI_COMMAND_MASTER)
27 /* Bits guests are allowed to control in permissive mode. */
28 #define PCI_COMMAND_GUEST (PCI_COMMAND_MASTER|PCI_COMMAND_SPECIAL| \
29 PCI_COMMAND_INVALIDATE|PCI_COMMAND_VGA_PALETTE| \
30 PCI_COMMAND_WAIT|PCI_COMMAND_FAST_BACK)
32 static void *command_init(struct pci_dev *dev, int offset)
34 struct pci_cmd_info *cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
38 return ERR_PTR(-ENOMEM);
40 err = pci_read_config_word(dev, PCI_COMMAND, &cmd->val);
49 static int command_read(struct pci_dev *dev, int offset, u16 *value, void *data)
51 int ret = pci_read_config_word(dev, offset, value);
52 const struct pci_cmd_info *cmd = data;
54 *value &= PCI_COMMAND_GUEST;
55 *value |= cmd->val & ~PCI_COMMAND_GUEST;
60 static int command_write(struct pci_dev *dev, int offset, u16 value, void *data)
62 struct xen_pcibk_dev_data *dev_data;
65 struct pci_cmd_info *cmd = data;
67 dev_data = pci_get_drvdata(dev);
68 if (!pci_is_enabled(dev) && is_enable_cmd(value)) {
69 if (unlikely(verbose_request))
70 printk(KERN_DEBUG DRV_NAME ": %s: enable\n",
72 err = pci_enable_device(dev);
76 dev_data->enable_intx = 1;
77 } else if (pci_is_enabled(dev) && !is_enable_cmd(value)) {
78 if (unlikely(verbose_request))
79 printk(KERN_DEBUG DRV_NAME ": %s: disable\n",
81 pci_disable_device(dev);
83 dev_data->enable_intx = 0;
86 if (!dev->is_busmaster && is_master_cmd(value)) {
87 if (unlikely(verbose_request))
88 printk(KERN_DEBUG DRV_NAME ": %s: set bus master\n",
93 if (value & PCI_COMMAND_INVALIDATE) {
94 if (unlikely(verbose_request))
96 DRV_NAME ": %s: enable memory-write-invalidate\n",
98 err = pci_set_mwi(dev);
100 pr_warn("%s: cannot enable memory-write-invalidate (%d)\n",
102 value &= ~PCI_COMMAND_INVALIDATE;
108 if (!permissive && (!dev_data || !dev_data->permissive))
111 /* Only allow the guest to control certain bits. */
112 err = pci_read_config_word(dev, offset, &val);
113 if (err || val == value)
116 value &= PCI_COMMAND_GUEST;
117 value |= val & ~PCI_COMMAND_GUEST;
119 return pci_write_config_word(dev, offset, value);
122 static int rom_write(struct pci_dev *dev, int offset, u32 value, void *data)
124 struct pci_bar_info *bar = data;
126 if (unlikely(!bar)) {
127 pr_warn(DRV_NAME ": driver data not found for %s\n",
129 return XEN_PCI_ERR_op_failed;
132 /* A write to obtain the length must happen as a 32-bit write.
133 * This does not (yet) support writing individual bytes
135 if (value == ~PCI_ROM_ADDRESS_ENABLE)
139 pci_read_config_dword(dev, offset, &tmpval);
140 if (tmpval != bar->val && value == bar->val) {
141 /* Allow restoration of bar value. */
142 pci_write_config_dword(dev, offset, bar->val);
147 /* Do we need to support enabling/disabling the rom address here? */
152 /* For the BARs, only allow writes which write ~0 or
153 * the correct resource information
154 * (Needed for when the driver probes the resource usage)
156 static int bar_write(struct pci_dev *dev, int offset, u32 value, void *data)
158 struct pci_bar_info *bar = data;
160 if (unlikely(!bar)) {
161 pr_warn(DRV_NAME ": driver data not found for %s\n",
163 return XEN_PCI_ERR_op_failed;
166 /* A write to obtain the length must happen as a 32-bit write.
167 * This does not (yet) support writing individual bytes
173 pci_read_config_dword(dev, offset, &tmpval);
174 if (tmpval != bar->val && value == bar->val) {
175 /* Allow restoration of bar value. */
176 pci_write_config_dword(dev, offset, bar->val);
184 static int bar_read(struct pci_dev *dev, int offset, u32 * value, void *data)
186 struct pci_bar_info *bar = data;
188 if (unlikely(!bar)) {
189 pr_warn(DRV_NAME ": driver data not found for %s\n",
191 return XEN_PCI_ERR_op_failed;
194 *value = bar->which ? bar->len_val : bar->val;
199 static inline void read_dev_bar(struct pci_dev *dev,
200 struct pci_bar_info *bar_info, int offset,
204 struct resource *res = dev->resource;
206 if (offset == PCI_ROM_ADDRESS || offset == PCI_ROM_ADDRESS1)
207 pos = PCI_ROM_RESOURCE;
209 pos = (offset - PCI_BASE_ADDRESS_0) / 4;
210 if (pos && ((res[pos - 1].flags & (PCI_BASE_ADDRESS_SPACE |
211 PCI_BASE_ADDRESS_MEM_TYPE_MASK)) ==
212 (PCI_BASE_ADDRESS_SPACE_MEMORY |
213 PCI_BASE_ADDRESS_MEM_TYPE_64))) {
214 bar_info->val = res[pos - 1].start >> 32;
215 bar_info->len_val = res[pos - 1].end >> 32;
220 bar_info->val = res[pos].start |
221 (res[pos].flags & PCI_REGION_FLAG_MASK);
222 bar_info->len_val = resource_size(&res[pos]);
225 static void *bar_init(struct pci_dev *dev, int offset)
227 struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
230 return ERR_PTR(-ENOMEM);
232 read_dev_bar(dev, bar, offset, ~0);
238 static void *rom_init(struct pci_dev *dev, int offset)
240 struct pci_bar_info *bar = kmalloc(sizeof(*bar), GFP_KERNEL);
243 return ERR_PTR(-ENOMEM);
245 read_dev_bar(dev, bar, offset, ~PCI_ROM_ADDRESS_ENABLE);
251 static void bar_reset(struct pci_dev *dev, int offset, void *data)
253 struct pci_bar_info *bar = data;
258 static void bar_release(struct pci_dev *dev, int offset, void *data)
263 static int xen_pcibk_read_vendor(struct pci_dev *dev, int offset,
264 u16 *value, void *data)
266 *value = dev->vendor;
271 static int xen_pcibk_read_device(struct pci_dev *dev, int offset,
272 u16 *value, void *data)
274 *value = dev->device;
279 static int interrupt_read(struct pci_dev *dev, int offset, u8 * value,
282 *value = (u8) dev->irq;
287 static int bist_write(struct pci_dev *dev, int offset, u8 value, void *data)
292 err = pci_read_config_byte(dev, offset, &cur_value);
296 if ((cur_value & ~PCI_BIST_START) == (value & ~PCI_BIST_START)
297 || value == PCI_BIST_START)
298 err = pci_write_config_byte(dev, offset, value);
304 static const struct config_field header_common[] = {
306 .offset = PCI_VENDOR_ID,
308 .u.w.read = xen_pcibk_read_vendor,
311 .offset = PCI_DEVICE_ID,
313 .u.w.read = xen_pcibk_read_device,
316 .offset = PCI_COMMAND,
318 .init = command_init,
319 .release = bar_release,
320 .u.w.read = command_read,
321 .u.w.write = command_write,
324 .offset = PCI_INTERRUPT_LINE,
326 .u.b.read = interrupt_read,
329 .offset = PCI_INTERRUPT_PIN,
331 .u.b.read = xen_pcibk_read_config_byte,
334 /* Any side effects of letting driver domain control cache line? */
335 .offset = PCI_CACHE_LINE_SIZE,
337 .u.b.read = xen_pcibk_read_config_byte,
338 .u.b.write = xen_pcibk_write_config_byte,
341 .offset = PCI_LATENCY_TIMER,
343 .u.b.read = xen_pcibk_read_config_byte,
348 .u.b.read = xen_pcibk_read_config_byte,
349 .u.b.write = bist_write,
354 #define CFG_FIELD_BAR(reg_offset) \
356 .offset = reg_offset, \
359 .reset = bar_reset, \
360 .release = bar_release, \
361 .u.dw.read = bar_read, \
362 .u.dw.write = bar_write, \
365 #define CFG_FIELD_ROM(reg_offset) \
367 .offset = reg_offset, \
370 .reset = bar_reset, \
371 .release = bar_release, \
372 .u.dw.read = bar_read, \
373 .u.dw.write = rom_write, \
376 static const struct config_field header_0[] = {
377 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
378 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
379 CFG_FIELD_BAR(PCI_BASE_ADDRESS_2),
380 CFG_FIELD_BAR(PCI_BASE_ADDRESS_3),
381 CFG_FIELD_BAR(PCI_BASE_ADDRESS_4),
382 CFG_FIELD_BAR(PCI_BASE_ADDRESS_5),
383 CFG_FIELD_ROM(PCI_ROM_ADDRESS),
387 static const struct config_field header_1[] = {
388 CFG_FIELD_BAR(PCI_BASE_ADDRESS_0),
389 CFG_FIELD_BAR(PCI_BASE_ADDRESS_1),
390 CFG_FIELD_ROM(PCI_ROM_ADDRESS1),
394 int xen_pcibk_config_header_add_fields(struct pci_dev *dev)
398 err = xen_pcibk_config_add_fields(dev, header_common);
402 switch (dev->hdr_type) {
403 case PCI_HEADER_TYPE_NORMAL:
404 err = xen_pcibk_config_add_fields(dev, header_0);
407 case PCI_HEADER_TYPE_BRIDGE:
408 err = xen_pcibk_config_add_fields(dev, header_1);
413 pr_err("%s: Unsupported header type %d!\n",
414 pci_name(dev), dev->hdr_type);