2 * intel TCO Watchdog Driver
4 * (c) Copyright 2006-2011 Wim Van Sebroeck <wim@iguana.be>.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 * Neither Wim Van Sebroeck nor Iguana vzw. admit liability nor
12 * provide warranty for any of this software. This material is
13 * provided "AS-IS" and at no charge.
15 * The TCO watchdog is implemented in the following I/O controller hubs:
16 * (See the intel documentation on http://developer.intel.com.)
17 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
18 * document number 290687-002, 298242-027: 82801BA (ICH2)
19 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
20 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
21 * document number 290744-001, 290745-025: 82801DB (ICH4)
22 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
23 * document number 273599-001, 273645-002: 82801E (C-ICH)
24 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
25 * document number 300641-004, 300884-013: 6300ESB
26 * document number 301473-002, 301474-026: 82801F (ICH6)
27 * document number 313082-001, 313075-006: 631xESB, 632xESB
28 * document number 307013-003, 307014-024: 82801G (ICH7)
29 * document number 322896-001, 322897-001: NM10
30 * document number 313056-003, 313057-017: 82801H (ICH8)
31 * document number 316972-004, 316973-012: 82801I (ICH9)
32 * document number 319973-002, 319974-002: 82801J (ICH10)
33 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
34 * document number 320066-003, 320257-008: EP80597 (IICH)
35 * document number 324645-001, 324646-001: Cougar Point (CPT)
36 * document number TBD : Patsburg (PBG)
37 * document number TBD : DH89xxCC
38 * document number TBD : Panther Point
42 * Includes, defines, variables, module parameters, ...
45 /* Module and version information */
46 #define DRV_NAME "iTCO_wdt"
47 #define DRV_VERSION "1.07"
48 #define PFX DRV_NAME ": "
51 #include <linux/module.h> /* For module specific items */
52 #include <linux/moduleparam.h> /* For new moduleparam's */
53 #include <linux/types.h> /* For standard types (like size_t) */
54 #include <linux/errno.h> /* For the -ENODEV/... values */
55 #include <linux/kernel.h> /* For printk/panic/... */
56 #include <linux/miscdevice.h> /* For MODULE_ALIAS_MISCDEV
58 #include <linux/watchdog.h> /* For the watchdog specific items */
59 #include <linux/init.h> /* For __init/__exit/... */
60 #include <linux/fs.h> /* For file operations */
61 #include <linux/platform_device.h> /* For platform_driver framework */
62 #include <linux/pci.h> /* For pci functions */
63 #include <linux/ioport.h> /* For io-port access */
64 #include <linux/spinlock.h> /* For spin_lock/spin_unlock/... */
65 #include <linux/uaccess.h> /* For copy_to_user/put_user/... */
66 #include <linux/io.h> /* For inb/outb/... */
68 #include "iTCO_vendor.h"
70 /* TCO related info */
72 TCO_ICH = 0, /* ICH */
75 TCO_ICH2M, /* ICH2-M */
76 TCO_ICH3, /* ICH3-S */
77 TCO_ICH3M, /* ICH3-M */
79 TCO_ICH4M, /* ICH4-M */
81 TCO_ICH5, /* ICH5 & ICH5R */
82 TCO_6300ESB, /* 6300ESB */
83 TCO_ICH6, /* ICH6 & ICH6R */
84 TCO_ICH6M, /* ICH6-M */
85 TCO_ICH6W, /* ICH6W & ICH6RW */
86 TCO_631XESB, /* 631xESB/632xESB */
87 TCO_ICH7, /* ICH7 & ICH7R */
88 TCO_ICH7DH, /* ICH7DH */
89 TCO_ICH7M, /* ICH7-M & ICH7-U */
90 TCO_ICH7MDH, /* ICH7-M DH */
92 TCO_ICH8, /* ICH8 & ICH8R */
93 TCO_ICH8DH, /* ICH8DH */
94 TCO_ICH8DO, /* ICH8DO */
95 TCO_ICH8M, /* ICH8M */
96 TCO_ICH8ME, /* ICH8M-E */
98 TCO_ICH9R, /* ICH9R */
99 TCO_ICH9DH, /* ICH9DH */
100 TCO_ICH9DO, /* ICH9DO */
101 TCO_ICH9M, /* ICH9M */
102 TCO_ICH9ME, /* ICH9M-E */
103 TCO_ICH10, /* ICH10 */
104 TCO_ICH10R, /* ICH10R */
105 TCO_ICH10D, /* ICH10D */
106 TCO_ICH10DO, /* ICH10DO */
107 TCO_PCH, /* PCH Desktop Full Featured */
108 TCO_PCHM, /* PCH Mobile Full Featured */
117 TCO_PCHMSFF, /* PCH Mobile SFF Full Featured */
122 TCO_EP80579, /* EP80579 */
123 TCO_CPT, /* Cougar Point */
124 TCO_CPTD, /* Cougar Point Desktop */
125 TCO_CPTM, /* Cougar Point Mobile */
126 TCO_PBG, /* Patsburg */
127 TCO_DH89XXCC, /* DH89xxCC */
128 TCO_PPT, /* Panther Point */
133 unsigned int iTCO_version;
134 } iTCO_chipset_info[] __devinitdata = {
144 {"ICH5 or ICH5R", 1},
146 {"ICH6 or ICH6R", 2},
148 {"ICH6W or ICH6RW", 2},
149 {"631xESB/632xESB", 2},
150 {"ICH7 or ICH7R", 2},
152 {"ICH7-M or ICH7-U", 2},
155 {"ICH8 or ICH8R", 2},
170 {"PCH Desktop Full Featured", 2},
171 {"PCH Mobile Full Featured", 2},
180 {"PCH Mobile SFF Full Featured", 2},
187 {"Cougar Point Desktop", 2},
188 {"Cougar Point Mobile", 2},
191 {"Panther Point", 2},
196 * This data only exists for exporting the supported PCI ids
197 * via MODULE_DEVICE_TABLE. We do not actually register a
198 * pci_driver, because the I/O Controller Hub has also other
199 * functions that probably will be registered by other drivers.
201 static DEFINE_PCI_DEVICE_TABLE(iTCO_wdt_pci_tbl) = {
202 { PCI_VDEVICE(INTEL, 0x2410), TCO_ICH},
203 { PCI_VDEVICE(INTEL, 0x2420), TCO_ICH0},
204 { PCI_VDEVICE(INTEL, 0x2440), TCO_ICH2},
205 { PCI_VDEVICE(INTEL, 0x244c), TCO_ICH2M},
206 { PCI_VDEVICE(INTEL, 0x2480), TCO_ICH3},
207 { PCI_VDEVICE(INTEL, 0x248c), TCO_ICH3M},
208 { PCI_VDEVICE(INTEL, 0x24c0), TCO_ICH4},
209 { PCI_VDEVICE(INTEL, 0x24cc), TCO_ICH4M},
210 { PCI_VDEVICE(INTEL, 0x2450), TCO_CICH},
211 { PCI_VDEVICE(INTEL, 0x24d0), TCO_ICH5},
212 { PCI_VDEVICE(INTEL, 0x25a1), TCO_6300ESB},
213 { PCI_VDEVICE(INTEL, 0x2640), TCO_ICH6},
214 { PCI_VDEVICE(INTEL, 0x2641), TCO_ICH6M},
215 { PCI_VDEVICE(INTEL, 0x2642), TCO_ICH6W},
216 { PCI_VDEVICE(INTEL, 0x2670), TCO_631XESB},
217 { PCI_VDEVICE(INTEL, 0x2671), TCO_631XESB},
218 { PCI_VDEVICE(INTEL, 0x2672), TCO_631XESB},
219 { PCI_VDEVICE(INTEL, 0x2673), TCO_631XESB},
220 { PCI_VDEVICE(INTEL, 0x2674), TCO_631XESB},
221 { PCI_VDEVICE(INTEL, 0x2675), TCO_631XESB},
222 { PCI_VDEVICE(INTEL, 0x2676), TCO_631XESB},
223 { PCI_VDEVICE(INTEL, 0x2677), TCO_631XESB},
224 { PCI_VDEVICE(INTEL, 0x2678), TCO_631XESB},
225 { PCI_VDEVICE(INTEL, 0x2679), TCO_631XESB},
226 { PCI_VDEVICE(INTEL, 0x267a), TCO_631XESB},
227 { PCI_VDEVICE(INTEL, 0x267b), TCO_631XESB},
228 { PCI_VDEVICE(INTEL, 0x267c), TCO_631XESB},
229 { PCI_VDEVICE(INTEL, 0x267d), TCO_631XESB},
230 { PCI_VDEVICE(INTEL, 0x267e), TCO_631XESB},
231 { PCI_VDEVICE(INTEL, 0x267f), TCO_631XESB},
232 { PCI_VDEVICE(INTEL, 0x27b8), TCO_ICH7},
233 { PCI_VDEVICE(INTEL, 0x27b0), TCO_ICH7DH},
234 { PCI_VDEVICE(INTEL, 0x27b9), TCO_ICH7M},
235 { PCI_VDEVICE(INTEL, 0x27bd), TCO_ICH7MDH},
236 { PCI_VDEVICE(INTEL, 0x27bc), TCO_NM10},
237 { PCI_VDEVICE(INTEL, 0x2810), TCO_ICH8},
238 { PCI_VDEVICE(INTEL, 0x2812), TCO_ICH8DH},
239 { PCI_VDEVICE(INTEL, 0x2814), TCO_ICH8DO},
240 { PCI_VDEVICE(INTEL, 0x2815), TCO_ICH8M},
241 { PCI_VDEVICE(INTEL, 0x2811), TCO_ICH8ME},
242 { PCI_VDEVICE(INTEL, 0x2918), TCO_ICH9},
243 { PCI_VDEVICE(INTEL, 0x2916), TCO_ICH9R},
244 { PCI_VDEVICE(INTEL, 0x2912), TCO_ICH9DH},
245 { PCI_VDEVICE(INTEL, 0x2914), TCO_ICH9DO},
246 { PCI_VDEVICE(INTEL, 0x2919), TCO_ICH9M},
247 { PCI_VDEVICE(INTEL, 0x2917), TCO_ICH9ME},
248 { PCI_VDEVICE(INTEL, 0x3a18), TCO_ICH10},
249 { PCI_VDEVICE(INTEL, 0x3a16), TCO_ICH10R},
250 { PCI_VDEVICE(INTEL, 0x3a1a), TCO_ICH10D},
251 { PCI_VDEVICE(INTEL, 0x3a14), TCO_ICH10DO},
252 { PCI_VDEVICE(INTEL, 0x3b00), TCO_PCH},
253 { PCI_VDEVICE(INTEL, 0x3b01), TCO_PCHM},
254 { PCI_VDEVICE(INTEL, 0x3b02), TCO_P55},
255 { PCI_VDEVICE(INTEL, 0x3b03), TCO_PM55},
256 { PCI_VDEVICE(INTEL, 0x3b06), TCO_H55},
257 { PCI_VDEVICE(INTEL, 0x3b07), TCO_QM57},
258 { PCI_VDEVICE(INTEL, 0x3b08), TCO_H57},
259 { PCI_VDEVICE(INTEL, 0x3b09), TCO_HM55},
260 { PCI_VDEVICE(INTEL, 0x3b0a), TCO_Q57},
261 { PCI_VDEVICE(INTEL, 0x3b0b), TCO_HM57},
262 { PCI_VDEVICE(INTEL, 0x3b0d), TCO_PCHMSFF},
263 { PCI_VDEVICE(INTEL, 0x3b0f), TCO_QS57},
264 { PCI_VDEVICE(INTEL, 0x3b12), TCO_3400},
265 { PCI_VDEVICE(INTEL, 0x3b14), TCO_3420},
266 { PCI_VDEVICE(INTEL, 0x3b16), TCO_3450},
267 { PCI_VDEVICE(INTEL, 0x5031), TCO_EP80579},
268 { PCI_VDEVICE(INTEL, 0x1c41), TCO_CPT},
269 { PCI_VDEVICE(INTEL, 0x1c42), TCO_CPTD},
270 { PCI_VDEVICE(INTEL, 0x1c43), TCO_CPTM},
271 { PCI_VDEVICE(INTEL, 0x1c44), TCO_CPT},
272 { PCI_VDEVICE(INTEL, 0x1c45), TCO_CPT},
273 { PCI_VDEVICE(INTEL, 0x1c46), TCO_CPT},
274 { PCI_VDEVICE(INTEL, 0x1c47), TCO_CPT},
275 { PCI_VDEVICE(INTEL, 0x1c48), TCO_CPT},
276 { PCI_VDEVICE(INTEL, 0x1c49), TCO_CPT},
277 { PCI_VDEVICE(INTEL, 0x1c4a), TCO_CPT},
278 { PCI_VDEVICE(INTEL, 0x1c4b), TCO_CPT},
279 { PCI_VDEVICE(INTEL, 0x1c4c), TCO_CPT},
280 { PCI_VDEVICE(INTEL, 0x1c4d), TCO_CPT},
281 { PCI_VDEVICE(INTEL, 0x1c4e), TCO_CPT},
282 { PCI_VDEVICE(INTEL, 0x1c4f), TCO_CPT},
283 { PCI_VDEVICE(INTEL, 0x1c50), TCO_CPT},
284 { PCI_VDEVICE(INTEL, 0x1c51), TCO_CPT},
285 { PCI_VDEVICE(INTEL, 0x1c52), TCO_CPT},
286 { PCI_VDEVICE(INTEL, 0x1c53), TCO_CPT},
287 { PCI_VDEVICE(INTEL, 0x1c54), TCO_CPT},
288 { PCI_VDEVICE(INTEL, 0x1c55), TCO_CPT},
289 { PCI_VDEVICE(INTEL, 0x1c56), TCO_CPT},
290 { PCI_VDEVICE(INTEL, 0x1c57), TCO_CPT},
291 { PCI_VDEVICE(INTEL, 0x1c58), TCO_CPT},
292 { PCI_VDEVICE(INTEL, 0x1c59), TCO_CPT},
293 { PCI_VDEVICE(INTEL, 0x1c5a), TCO_CPT},
294 { PCI_VDEVICE(INTEL, 0x1c5b), TCO_CPT},
295 { PCI_VDEVICE(INTEL, 0x1c5c), TCO_CPT},
296 { PCI_VDEVICE(INTEL, 0x1c5d), TCO_CPT},
297 { PCI_VDEVICE(INTEL, 0x1c5e), TCO_CPT},
298 { PCI_VDEVICE(INTEL, 0x1c5f), TCO_CPT},
299 { PCI_VDEVICE(INTEL, 0x1d40), TCO_PBG},
300 { PCI_VDEVICE(INTEL, 0x1d41), TCO_PBG},
301 { PCI_VDEVICE(INTEL, 0x2310), TCO_DH89XXCC},
302 { PCI_VDEVICE(INTEL, 0x1e40), TCO_PPT},
303 { PCI_VDEVICE(INTEL, 0x1e41), TCO_PPT},
304 { PCI_VDEVICE(INTEL, 0x1e42), TCO_PPT},
305 { PCI_VDEVICE(INTEL, 0x1e43), TCO_PPT},
306 { PCI_VDEVICE(INTEL, 0x1e44), TCO_PPT},
307 { PCI_VDEVICE(INTEL, 0x1e45), TCO_PPT},
308 { PCI_VDEVICE(INTEL, 0x1e46), TCO_PPT},
309 { PCI_VDEVICE(INTEL, 0x1e47), TCO_PPT},
310 { PCI_VDEVICE(INTEL, 0x1e48), TCO_PPT},
311 { PCI_VDEVICE(INTEL, 0x1e49), TCO_PPT},
312 { PCI_VDEVICE(INTEL, 0x1e4a), TCO_PPT},
313 { PCI_VDEVICE(INTEL, 0x1e4b), TCO_PPT},
314 { PCI_VDEVICE(INTEL, 0x1e4c), TCO_PPT},
315 { PCI_VDEVICE(INTEL, 0x1e4d), TCO_PPT},
316 { PCI_VDEVICE(INTEL, 0x1e4e), TCO_PPT},
317 { PCI_VDEVICE(INTEL, 0x1e4f), TCO_PPT},
318 { PCI_VDEVICE(INTEL, 0x1e50), TCO_PPT},
319 { PCI_VDEVICE(INTEL, 0x1e51), TCO_PPT},
320 { PCI_VDEVICE(INTEL, 0x1e52), TCO_PPT},
321 { PCI_VDEVICE(INTEL, 0x1e53), TCO_PPT},
322 { PCI_VDEVICE(INTEL, 0x1e54), TCO_PPT},
323 { PCI_VDEVICE(INTEL, 0x1e55), TCO_PPT},
324 { PCI_VDEVICE(INTEL, 0x1e56), TCO_PPT},
325 { PCI_VDEVICE(INTEL, 0x1e57), TCO_PPT},
326 { PCI_VDEVICE(INTEL, 0x1e58), TCO_PPT},
327 { PCI_VDEVICE(INTEL, 0x1e59), TCO_PPT},
328 { PCI_VDEVICE(INTEL, 0x1e5a), TCO_PPT},
329 { PCI_VDEVICE(INTEL, 0x1e5b), TCO_PPT},
330 { PCI_VDEVICE(INTEL, 0x1e5c), TCO_PPT},
331 { PCI_VDEVICE(INTEL, 0x1e5d), TCO_PPT},
332 { PCI_VDEVICE(INTEL, 0x1e5e), TCO_PPT},
333 { PCI_VDEVICE(INTEL, 0x1e5f), TCO_PPT},
334 { 0, }, /* End of list */
336 MODULE_DEVICE_TABLE(pci, iTCO_wdt_pci_tbl);
338 /* Address definitions for the TCO */
339 /* TCO base address */
340 #define TCOBASE (iTCO_wdt_private.ACPIBASE + 0x60)
341 /* SMI Control and Enable Register */
342 #define SMI_EN (iTCO_wdt_private.ACPIBASE + 0x30)
344 #define TCO_RLD (TCOBASE + 0x00) /* TCO Timer Reload and Curr. Value */
345 #define TCOv1_TMR (TCOBASE + 0x01) /* TCOv1 Timer Initial Value */
346 #define TCO_DAT_IN (TCOBASE + 0x02) /* TCO Data In Register */
347 #define TCO_DAT_OUT (TCOBASE + 0x03) /* TCO Data Out Register */
348 #define TCO1_STS (TCOBASE + 0x04) /* TCO1 Status Register */
349 #define TCO2_STS (TCOBASE + 0x06) /* TCO2 Status Register */
350 #define TCO1_CNT (TCOBASE + 0x08) /* TCO1 Control Register */
351 #define TCO2_CNT (TCOBASE + 0x0a) /* TCO2 Control Register */
352 #define TCOv2_TMR (TCOBASE + 0x12) /* TCOv2 Timer Initial Value */
354 /* internal variables */
355 static unsigned long is_active;
356 static char expect_release;
357 static struct { /* this is private data for the iTCO_wdt device */
358 /* TCO version/generation */
359 unsigned int iTCO_version;
360 /* The device's ACPIBASE address (TCOBASE = ACPIBASE+0x60) */
361 unsigned long ACPIBASE;
362 /* NO_REBOOT flag is Memory-Mapped GCS register bit 5 (TCO version 2)*/
363 unsigned long __iomem *gcs;
364 /* the lock for io operations */
367 struct pci_dev *pdev;
370 /* the watchdog platform device */
371 static struct platform_device *iTCO_wdt_platform_device;
373 /* module parameters */
374 #define WATCHDOG_HEARTBEAT 30 /* 30 sec default heartbeat */
375 static int heartbeat = WATCHDOG_HEARTBEAT; /* in seconds */
376 module_param(heartbeat, int, 0);
377 MODULE_PARM_DESC(heartbeat, "Watchdog timeout in seconds. "
378 "5..76 (TCO v1) or 3..614 (TCO v2), default="
379 __MODULE_STRING(WATCHDOG_HEARTBEAT) ")");
381 static int nowayout = WATCHDOG_NOWAYOUT;
382 module_param(nowayout, int, 0);
383 MODULE_PARM_DESC(nowayout,
384 "Watchdog cannot be stopped once started (default="
385 __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
387 static int turn_SMI_watchdog_clear_off = 0;
388 module_param(turn_SMI_watchdog_clear_off, int, 0);
389 MODULE_PARM_DESC(turn_SMI_watchdog_clear_off,
390 "Turn off SMI clearing watchdog (default=0)");
393 * Some TCO specific functions
396 static inline unsigned int seconds_to_ticks(int seconds)
398 /* the internal timer is stored as ticks which decrement
399 * every 0.6 seconds */
400 return (seconds * 10) / 6;
403 static void iTCO_wdt_set_NO_REBOOT_bit(void)
407 /* Set the NO_REBOOT bit: this disables reboots */
408 if (iTCO_wdt_private.iTCO_version == 2) {
409 val32 = readl(iTCO_wdt_private.gcs);
411 writel(val32, iTCO_wdt_private.gcs);
412 } else if (iTCO_wdt_private.iTCO_version == 1) {
413 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
415 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
419 static int iTCO_wdt_unset_NO_REBOOT_bit(void)
424 /* Unset the NO_REBOOT bit: this enables reboots */
425 if (iTCO_wdt_private.iTCO_version == 2) {
426 val32 = readl(iTCO_wdt_private.gcs);
428 writel(val32, iTCO_wdt_private.gcs);
430 val32 = readl(iTCO_wdt_private.gcs);
431 if (val32 & 0x00000020)
433 } else if (iTCO_wdt_private.iTCO_version == 1) {
434 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
436 pci_write_config_dword(iTCO_wdt_private.pdev, 0xd4, val32);
438 pci_read_config_dword(iTCO_wdt_private.pdev, 0xd4, &val32);
439 if (val32 & 0x00000002)
443 return ret; /* returns: 0 = OK, -EIO = Error */
446 static int iTCO_wdt_start(void)
450 spin_lock(&iTCO_wdt_private.io_lock);
452 iTCO_vendor_pre_start(iTCO_wdt_private.ACPIBASE, heartbeat);
454 /* disable chipset's NO_REBOOT bit */
455 if (iTCO_wdt_unset_NO_REBOOT_bit()) {
456 spin_unlock(&iTCO_wdt_private.io_lock);
457 printk(KERN_ERR PFX "failed to reset NO_REBOOT flag, "
458 "reboot disabled by hardware/BIOS\n");
462 /* Force the timer to its reload value by writing to the TCO_RLD
464 if (iTCO_wdt_private.iTCO_version == 2)
466 else if (iTCO_wdt_private.iTCO_version == 1)
469 /* Bit 11: TCO Timer Halt -> 0 = The TCO timer is enabled to count */
474 spin_unlock(&iTCO_wdt_private.io_lock);
481 static int iTCO_wdt_stop(void)
485 spin_lock(&iTCO_wdt_private.io_lock);
487 iTCO_vendor_pre_stop(iTCO_wdt_private.ACPIBASE);
489 /* Bit 11: TCO Timer Halt -> 1 = The TCO timer is disabled */
495 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
496 iTCO_wdt_set_NO_REBOOT_bit();
498 spin_unlock(&iTCO_wdt_private.io_lock);
500 if ((val & 0x0800) == 0)
505 static int iTCO_wdt_keepalive(void)
507 spin_lock(&iTCO_wdt_private.io_lock);
509 iTCO_vendor_pre_keepalive(iTCO_wdt_private.ACPIBASE, heartbeat);
511 /* Reload the timer by writing to the TCO Timer Counter register */
512 if (iTCO_wdt_private.iTCO_version == 2)
514 else if (iTCO_wdt_private.iTCO_version == 1) {
515 /* Reset the timeout status bit so that the timer
516 * needs to count down twice again before rebooting */
517 outw(0x0008, TCO1_STS); /* write 1 to clear bit */
522 spin_unlock(&iTCO_wdt_private.io_lock);
526 static int iTCO_wdt_set_heartbeat(int t)
532 tmrval = seconds_to_ticks(t);
534 /* For TCO v1 the timer counts down twice before rebooting */
535 if (iTCO_wdt_private.iTCO_version == 1)
538 /* from the specs: */
539 /* "Values of 0h-3h are ignored and should not be attempted" */
542 if (((iTCO_wdt_private.iTCO_version == 2) && (tmrval > 0x3ff)) ||
543 ((iTCO_wdt_private.iTCO_version == 1) && (tmrval > 0x03f)))
546 iTCO_vendor_pre_set_heartbeat(tmrval);
548 /* Write new heartbeat to watchdog */
549 if (iTCO_wdt_private.iTCO_version == 2) {
550 spin_lock(&iTCO_wdt_private.io_lock);
551 val16 = inw(TCOv2_TMR);
554 outw(val16, TCOv2_TMR);
555 val16 = inw(TCOv2_TMR);
556 spin_unlock(&iTCO_wdt_private.io_lock);
558 if ((val16 & 0x3ff) != tmrval)
560 } else if (iTCO_wdt_private.iTCO_version == 1) {
561 spin_lock(&iTCO_wdt_private.io_lock);
562 val8 = inb(TCOv1_TMR);
564 val8 |= (tmrval & 0xff);
565 outb(val8, TCOv1_TMR);
566 val8 = inb(TCOv1_TMR);
567 spin_unlock(&iTCO_wdt_private.io_lock);
569 if ((val8 & 0x3f) != tmrval)
577 static int iTCO_wdt_get_timeleft(int *time_left)
582 /* read the TCO Timer */
583 if (iTCO_wdt_private.iTCO_version == 2) {
584 spin_lock(&iTCO_wdt_private.io_lock);
585 val16 = inw(TCO_RLD);
587 spin_unlock(&iTCO_wdt_private.io_lock);
589 *time_left = (val16 * 6) / 10;
590 } else if (iTCO_wdt_private.iTCO_version == 1) {
591 spin_lock(&iTCO_wdt_private.io_lock);
594 if (!(inw(TCO1_STS) & 0x0008))
595 val8 += (inb(TCOv1_TMR) & 0x3f);
596 spin_unlock(&iTCO_wdt_private.io_lock);
598 *time_left = (val8 * 6) / 10;
605 * /dev/watchdog handling
608 static int iTCO_wdt_open(struct inode *inode, struct file *file)
610 /* /dev/watchdog can only be opened once */
611 if (test_and_set_bit(0, &is_active))
615 * Reload and activate timer
618 return nonseekable_open(inode, file);
621 static int iTCO_wdt_release(struct inode *inode, struct file *file)
624 * Shut off the timer.
626 if (expect_release == 42) {
630 "Unexpected close, not stopping watchdog!\n");
631 iTCO_wdt_keepalive();
633 clear_bit(0, &is_active);
638 static ssize_t iTCO_wdt_write(struct file *file, const char __user *data,
639 size_t len, loff_t *ppos)
641 /* See if we got the magic character 'V' and reload the timer */
646 /* note: just in case someone wrote the magic
647 character five months ago... */
650 /* scan to see whether or not we got the
652 for (i = 0; i != len; i++) {
654 if (get_user(c, data + i))
661 /* someone wrote to us, we should reload the timer */
662 iTCO_wdt_keepalive();
667 static long iTCO_wdt_ioctl(struct file *file, unsigned int cmd,
670 int new_options, retval = -EINVAL;
672 void __user *argp = (void __user *)arg;
673 int __user *p = argp;
674 static const struct watchdog_info ident = {
675 .options = WDIOF_SETTIMEOUT |
676 WDIOF_KEEPALIVEPING |
678 .firmware_version = 0,
679 .identity = DRV_NAME,
683 case WDIOC_GETSUPPORT:
684 return copy_to_user(argp, &ident, sizeof(ident)) ? -EFAULT : 0;
685 case WDIOC_GETSTATUS:
686 case WDIOC_GETBOOTSTATUS:
687 return put_user(0, p);
689 case WDIOC_SETOPTIONS:
691 if (get_user(new_options, p))
694 if (new_options & WDIOS_DISABLECARD) {
698 if (new_options & WDIOS_ENABLECARD) {
699 iTCO_wdt_keepalive();
705 case WDIOC_KEEPALIVE:
706 iTCO_wdt_keepalive();
709 case WDIOC_SETTIMEOUT:
711 if (get_user(new_heartbeat, p))
713 if (iTCO_wdt_set_heartbeat(new_heartbeat))
715 iTCO_wdt_keepalive();
718 case WDIOC_GETTIMEOUT:
719 return put_user(heartbeat, p);
720 case WDIOC_GETTIMELEFT:
723 if (iTCO_wdt_get_timeleft(&time_left))
725 return put_user(time_left, p);
736 static const struct file_operations iTCO_wdt_fops = {
737 .owner = THIS_MODULE,
739 .write = iTCO_wdt_write,
740 .unlocked_ioctl = iTCO_wdt_ioctl,
741 .open = iTCO_wdt_open,
742 .release = iTCO_wdt_release,
745 static struct miscdevice iTCO_wdt_miscdev = {
746 .minor = WATCHDOG_MINOR,
748 .fops = &iTCO_wdt_fops,
752 * Init & exit routines
755 static int __devinit iTCO_wdt_init(struct pci_dev *pdev,
756 const struct pci_device_id *ent, struct platform_device *dev)
764 * Find the ACPI/PM base I/O address which is the base
765 * for the TCO registers (TCOBASE=ACPIBASE + 0x60)
766 * ACPIBASE is bits [15:7] from 0x40-0x43
768 pci_read_config_dword(pdev, 0x40, &base_address);
769 base_address &= 0x0000ff80;
770 if (base_address == 0x00000000) {
771 /* Something's wrong here, ACPIBASE has to be set */
772 printk(KERN_ERR PFX "failed to get TCOBASE address, "
773 "device disabled by hardware/BIOS\n");
776 iTCO_wdt_private.iTCO_version =
777 iTCO_chipset_info[ent->driver_data].iTCO_version;
778 iTCO_wdt_private.ACPIBASE = base_address;
779 iTCO_wdt_private.pdev = pdev;
781 /* Get the Memory-Mapped GCS register, we need it for the
782 NO_REBOOT flag (TCO v2). To get access to it you have to
783 read RCBA from PCI Config space 0xf0 and use it as base.
784 GCS = RCBA + ICH6_GCS(0x3410). */
785 if (iTCO_wdt_private.iTCO_version == 2) {
786 pci_read_config_dword(pdev, 0xf0, &base_address);
787 if ((base_address & 1) == 0) {
788 printk(KERN_ERR PFX "RCBA is disabled by hardware"
789 "/BIOS, device disabled\n");
793 RCBA = base_address & 0xffffc000;
794 iTCO_wdt_private.gcs = ioremap((RCBA + 0x3410), 4);
797 /* Check chipset's NO_REBOOT bit */
798 if (iTCO_wdt_unset_NO_REBOOT_bit() && iTCO_vendor_check_noreboot_on()) {
799 printk(KERN_INFO PFX "unable to reset NO_REBOOT flag, "
800 "device disabled by hardware/BIOS\n");
801 ret = -ENODEV; /* Cannot reset NO_REBOOT bit */
805 /* Set the NO_REBOOT bit to prevent later reboots, just for sure */
806 iTCO_wdt_set_NO_REBOOT_bit();
808 /* The TCO logic uses the TCO_EN bit in the SMI_EN register */
809 if (!request_region(SMI_EN, 4, "iTCO_wdt")) {
811 "I/O address 0x%04lx already in use, "
812 "device disabled\n", SMI_EN);
816 if (turn_SMI_watchdog_clear_off) {
817 /* Bit 13: TCO_EN -> 0 = Disables TCO logic generating an SMI# */
819 val32 &= 0xffffdfff; /* Turn off SMI clearing watchdog */
823 /* The TCO I/O registers reside in a 32-byte range pointed to
824 by the TCOBASE value */
825 if (!request_region(TCOBASE, 0x20, "iTCO_wdt")) {
826 printk(KERN_ERR PFX "I/O address 0x%04lx already in use "
827 "device disabled\n", TCOBASE);
833 "Found a %s TCO device (Version=%d, TCOBASE=0x%04lx)\n",
834 iTCO_chipset_info[ent->driver_data].name,
835 iTCO_chipset_info[ent->driver_data].iTCO_version,
838 /* Clear out the (probably old) status */
839 outw(0x0008, TCO1_STS); /* Clear the Time Out Status bit */
840 outw(0x0002, TCO2_STS); /* Clear SECOND_TO_STS bit */
841 outw(0x0004, TCO2_STS); /* Clear BOOT_STS bit */
843 /* Make sure the watchdog is not running */
846 /* Check that the heartbeat value is within it's range;
847 if not reset to the default */
848 if (iTCO_wdt_set_heartbeat(heartbeat)) {
849 iTCO_wdt_set_heartbeat(WATCHDOG_HEARTBEAT);
851 "timeout value out of range, using %d\n", heartbeat);
854 ret = misc_register(&iTCO_wdt_miscdev);
857 "cannot register miscdev on minor=%d (err=%d)\n",
858 WATCHDOG_MINOR, ret);
862 printk(KERN_INFO PFX "initialized. heartbeat=%d sec (nowayout=%d)\n",
863 heartbeat, nowayout);
868 release_region(TCOBASE, 0x20);
870 release_region(SMI_EN, 4);
872 if (iTCO_wdt_private.iTCO_version == 2)
873 iounmap(iTCO_wdt_private.gcs);
875 iTCO_wdt_private.ACPIBASE = 0;
879 static void __devexit iTCO_wdt_cleanup(void)
881 /* Stop the timer before we leave */
886 misc_deregister(&iTCO_wdt_miscdev);
887 release_region(TCOBASE, 0x20);
888 release_region(SMI_EN, 4);
889 if (iTCO_wdt_private.iTCO_version == 2)
890 iounmap(iTCO_wdt_private.gcs);
891 pci_dev_put(iTCO_wdt_private.pdev);
892 iTCO_wdt_private.ACPIBASE = 0;
895 static int __devinit iTCO_wdt_probe(struct platform_device *dev)
899 struct pci_dev *pdev = NULL;
900 const struct pci_device_id *ent;
902 spin_lock_init(&iTCO_wdt_private.io_lock);
904 for_each_pci_dev(pdev) {
905 ent = pci_match_id(iTCO_wdt_pci_tbl, pdev);
908 ret = iTCO_wdt_init(pdev, ent, dev);
915 printk(KERN_INFO PFX "No device detected.\n");
920 static int __devexit iTCO_wdt_remove(struct platform_device *dev)
922 if (iTCO_wdt_private.ACPIBASE)
928 static void iTCO_wdt_shutdown(struct platform_device *dev)
933 static struct platform_driver iTCO_wdt_driver = {
934 .probe = iTCO_wdt_probe,
935 .remove = __devexit_p(iTCO_wdt_remove),
936 .shutdown = iTCO_wdt_shutdown,
938 .owner = THIS_MODULE,
943 static int __init iTCO_wdt_init_module(void)
947 printk(KERN_INFO PFX "Intel TCO WatchDog Timer Driver v%s\n",
950 err = platform_driver_register(&iTCO_wdt_driver);
954 iTCO_wdt_platform_device = platform_device_register_simple(DRV_NAME,
956 if (IS_ERR(iTCO_wdt_platform_device)) {
957 err = PTR_ERR(iTCO_wdt_platform_device);
958 goto unreg_platform_driver;
963 unreg_platform_driver:
964 platform_driver_unregister(&iTCO_wdt_driver);
968 static void __exit iTCO_wdt_cleanup_module(void)
970 platform_device_unregister(iTCO_wdt_platform_device);
971 platform_driver_unregister(&iTCO_wdt_driver);
972 printk(KERN_INFO PFX "Watchdog Module Unloaded.\n");
975 module_init(iTCO_wdt_init_module);
976 module_exit(iTCO_wdt_cleanup_module);
978 MODULE_AUTHOR("Wim Van Sebroeck <wim@iguana.be>");
979 MODULE_DESCRIPTION("Intel TCO WatchDog Timer Driver");
980 MODULE_VERSION(DRV_VERSION);
981 MODULE_LICENSE("GPL");
982 MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);