2 * drivers/w1/masters/omap_hdq.c
4 * Copyright (C) 2007,2012 Texas Instruments, Inc.
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/interrupt.h>
15 #include <linux/slab.h>
16 #include <linux/err.h>
18 #include <linux/sched.h>
19 #include <linux/pm_runtime.h>
23 #include "../w1_int.h"
25 #define MOD_NAME "OMAP_HDQ:"
27 #define OMAP_HDQ_REVISION 0x00
28 #define OMAP_HDQ_TX_DATA 0x04
29 #define OMAP_HDQ_RX_DATA 0x08
30 #define OMAP_HDQ_CTRL_STATUS 0x0c
31 #define OMAP_HDQ_CTRL_STATUS_SINGLE BIT(7)
32 #define OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK BIT(6)
33 #define OMAP_HDQ_CTRL_STATUS_CLOCKENABLE BIT(5)
34 #define OMAP_HDQ_CTRL_STATUS_GO BIT(4)
35 #define OMAP_HDQ_CTRL_STATUS_PRESENCE BIT(3)
36 #define OMAP_HDQ_CTRL_STATUS_INITIALIZATION BIT(2)
37 #define OMAP_HDQ_CTRL_STATUS_DIR BIT(1)
38 #define OMAP_HDQ_INT_STATUS 0x10
39 #define OMAP_HDQ_INT_STATUS_TXCOMPLETE BIT(2)
40 #define OMAP_HDQ_INT_STATUS_RXCOMPLETE BIT(1)
41 #define OMAP_HDQ_INT_STATUS_TIMEOUT BIT(0)
42 #define OMAP_HDQ_SYSCONFIG 0x14
43 #define OMAP_HDQ_SYSCONFIG_SOFTRESET BIT(1)
44 #define OMAP_HDQ_SYSCONFIG_AUTOIDLE BIT(0)
45 #define OMAP_HDQ_SYSCONFIG_NOIDLE 0x0
46 #define OMAP_HDQ_SYSSTATUS 0x18
47 #define OMAP_HDQ_SYSSTATUS_RESETDONE BIT(0)
49 #define OMAP_HDQ_FLAG_CLEAR 0
50 #define OMAP_HDQ_FLAG_SET 1
51 #define OMAP_HDQ_TIMEOUT (HZ/5)
53 #define OMAP_HDQ_MAX_USER 4
55 static DECLARE_WAIT_QUEUE_HEAD(hdq_wait_queue);
60 void __iomem *hdq_base;
61 /* lock status update */
62 struct mutex hdq_mutex;
66 spinlock_t hdq_spinlock;
68 * Used to control the call to omap_hdq_get and omap_hdq_put.
69 * HDQ Protocol: Write the CMD|REG_address first, followed by
70 * the data wrire or read.
74 /* mode: 0-HDQ 1-W1 */
79 static int omap_hdq_probe(struct platform_device *pdev);
80 static int omap_hdq_remove(struct platform_device *pdev);
82 static const struct of_device_id omap_hdq_dt_ids[] = {
83 { .compatible = "ti,omap3-1w" },
84 { .compatible = "ti,am4372-hdq" },
87 MODULE_DEVICE_TABLE(of, omap_hdq_dt_ids);
89 static struct platform_driver omap_hdq_driver = {
90 .probe = omap_hdq_probe,
91 .remove = omap_hdq_remove,
94 .of_match_table = omap_hdq_dt_ids,
98 static u8 omap_w1_read_byte(void *_hdq);
99 static void omap_w1_write_byte(void *_hdq, u8 byte);
100 static u8 omap_w1_reset_bus(void *_hdq);
103 static struct w1_bus_master omap_w1_master = {
104 .read_byte = omap_w1_read_byte,
105 .write_byte = omap_w1_write_byte,
106 .reset_bus = omap_w1_reset_bus,
109 /* HDQ register I/O routines */
110 static inline u8 hdq_reg_in(struct hdq_data *hdq_data, u32 offset)
112 return __raw_readl(hdq_data->hdq_base + offset);
115 static inline void hdq_reg_out(struct hdq_data *hdq_data, u32 offset, u8 val)
117 __raw_writel(val, hdq_data->hdq_base + offset);
120 static inline u8 hdq_reg_merge(struct hdq_data *hdq_data, u32 offset,
123 u8 new_val = (__raw_readl(hdq_data->hdq_base + offset) & ~mask)
125 __raw_writel(new_val, hdq_data->hdq_base + offset);
130 static void hdq_disable_interrupt(struct hdq_data *hdq_data, u32 offset,
135 ie = readl(hdq_data->hdq_base + offset);
136 writel(ie & mask, hdq_data->hdq_base + offset);
140 * Wait for one or more bits in flag change.
141 * HDQ_FLAG_SET: wait until any bit in the flag is set.
142 * HDQ_FLAG_CLEAR: wait until all bits in the flag are cleared.
143 * return 0 on success and -ETIMEDOUT in the case of timeout.
145 static int hdq_wait_for_flag(struct hdq_data *hdq_data, u32 offset,
146 u8 flag, u8 flag_set, u8 *status)
149 unsigned long timeout = jiffies + OMAP_HDQ_TIMEOUT;
151 if (flag_set == OMAP_HDQ_FLAG_CLEAR) {
152 /* wait for the flag clear */
153 while (((*status = hdq_reg_in(hdq_data, offset)) & flag)
154 && time_before(jiffies, timeout)) {
155 schedule_timeout_uninterruptible(1);
159 } else if (flag_set == OMAP_HDQ_FLAG_SET) {
160 /* wait for the flag set */
161 while (!((*status = hdq_reg_in(hdq_data, offset)) & flag)
162 && time_before(jiffies, timeout)) {
163 schedule_timeout_uninterruptible(1);
165 if (!(*status & flag))
173 /* write out a byte and fill *status with HDQ_INT_STATUS */
174 static int hdq_write_byte(struct hdq_data *hdq_data, u8 val, u8 *status)
178 unsigned long irqflags;
182 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
183 /* clear interrupt flags via a dummy read */
184 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
185 /* ISR loads it with new INT_STATUS */
186 hdq_data->hdq_irqstatus = 0;
187 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
189 hdq_reg_out(hdq_data, OMAP_HDQ_TX_DATA, val);
192 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, OMAP_HDQ_CTRL_STATUS_GO,
193 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
194 /* wait for the TXCOMPLETE bit */
195 ret = wait_event_timeout(hdq_wait_queue,
196 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
198 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
203 *status = hdq_data->hdq_irqstatus;
204 /* check irqstatus */
205 if (!(*status & OMAP_HDQ_INT_STATUS_TXCOMPLETE)) {
206 dev_dbg(hdq_data->dev, "timeout waiting for"
207 " TXCOMPLETE/RXCOMPLETE, %x", *status);
212 /* wait for the GO bit return to zero */
213 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
214 OMAP_HDQ_CTRL_STATUS_GO,
215 OMAP_HDQ_FLAG_CLEAR, &tmp_status);
217 dev_dbg(hdq_data->dev, "timeout waiting GO bit"
218 " return to zero, %x", tmp_status);
225 /* HDQ Interrupt service routine */
226 static irqreturn_t hdq_isr(int irq, void *_hdq)
228 struct hdq_data *hdq_data = _hdq;
229 unsigned long irqflags;
231 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
232 hdq_data->hdq_irqstatus = hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
233 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
234 dev_dbg(hdq_data->dev, "hdq_isr: %x", hdq_data->hdq_irqstatus);
236 if (hdq_data->hdq_irqstatus &
237 (OMAP_HDQ_INT_STATUS_TXCOMPLETE | OMAP_HDQ_INT_STATUS_RXCOMPLETE
238 | OMAP_HDQ_INT_STATUS_TIMEOUT)) {
239 /* wake up sleeping process */
240 wake_up(&hdq_wait_queue);
246 /* W1 search callback function in HDQ mode */
247 static void omap_w1_search_bus(void *_hdq, struct w1_master *master_dev,
248 u8 search_type, w1_slave_found_callback slave_found)
250 u64 module_id, rn_le, cs, id;
257 rn_le = cpu_to_le64(module_id);
259 * HDQ might not obey truly the 1-wire spec.
260 * So calculate CRC based on module parameter.
262 cs = w1_calc_crc8((u8 *)&rn_le, 7);
263 id = (cs << 56) | module_id;
265 slave_found(master_dev, id);
268 static int _omap_hdq_reset(struct hdq_data *hdq_data)
273 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
274 OMAP_HDQ_SYSCONFIG_SOFTRESET);
276 * Select HDQ/1W mode & enable clocks.
277 * It is observed that INT flags can't be cleared via a read and GO/INIT
278 * won't return to zero if interrupt is disabled. So we always enable
281 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
282 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
283 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
285 /* wait for reset to complete */
286 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_SYSSTATUS,
287 OMAP_HDQ_SYSSTATUS_RESETDONE, OMAP_HDQ_FLAG_SET, &tmp_status);
289 dev_dbg(hdq_data->dev, "timeout waiting HDQ reset, %x",
292 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
293 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
294 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
296 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
297 OMAP_HDQ_SYSCONFIG_AUTOIDLE);
303 /* Issue break pulse to the device */
304 static int omap_hdq_break(struct hdq_data *hdq_data)
308 unsigned long irqflags;
310 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
312 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
317 spin_lock_irqsave(&hdq_data->hdq_spinlock, irqflags);
318 /* clear interrupt flags via a dummy read */
319 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
320 /* ISR loads it with new INT_STATUS */
321 hdq_data->hdq_irqstatus = 0;
322 spin_unlock_irqrestore(&hdq_data->hdq_spinlock, irqflags);
324 /* set the INIT and GO bit */
325 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
326 OMAP_HDQ_CTRL_STATUS_INITIALIZATION | OMAP_HDQ_CTRL_STATUS_GO,
327 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
328 OMAP_HDQ_CTRL_STATUS_GO);
330 /* wait for the TIMEOUT bit */
331 ret = wait_event_timeout(hdq_wait_queue,
332 hdq_data->hdq_irqstatus, OMAP_HDQ_TIMEOUT);
334 dev_dbg(hdq_data->dev, "break wait elapsed\n");
339 tmp_status = hdq_data->hdq_irqstatus;
340 /* check irqstatus */
341 if (!(tmp_status & OMAP_HDQ_INT_STATUS_TIMEOUT)) {
342 dev_dbg(hdq_data->dev, "timeout waiting for TIMEOUT, %x",
349 * check for the presence detect bit to get
350 * set to show that the slave is responding
352 if (!(hdq_reg_in(hdq_data, OMAP_HDQ_CTRL_STATUS) &
353 OMAP_HDQ_CTRL_STATUS_PRESENCE)) {
354 dev_dbg(hdq_data->dev, "Presence bit not set\n");
360 * wait for both INIT and GO bits rerurn to zero.
361 * zero wait time expected for interrupt mode.
363 ret = hdq_wait_for_flag(hdq_data, OMAP_HDQ_CTRL_STATUS,
364 OMAP_HDQ_CTRL_STATUS_INITIALIZATION |
365 OMAP_HDQ_CTRL_STATUS_GO, OMAP_HDQ_FLAG_CLEAR,
368 dev_dbg(hdq_data->dev, "timeout waiting INIT&GO bits"
369 " return to zero, %x", tmp_status);
372 mutex_unlock(&hdq_data->hdq_mutex);
377 static int hdq_read_byte(struct hdq_data *hdq_data, u8 *val)
382 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
388 if (!hdq_data->hdq_usecount) {
393 hdq_data->hdq_irqstatus = 0;
395 if (!(hdq_data->hdq_irqstatus & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
396 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS,
397 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO,
398 OMAP_HDQ_CTRL_STATUS_DIR | OMAP_HDQ_CTRL_STATUS_GO);
400 * The RX comes immediately after TX.
402 wait_event_timeout(hdq_wait_queue,
403 (hdq_data->hdq_irqstatus
404 & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
407 hdq_reg_merge(hdq_data, OMAP_HDQ_CTRL_STATUS, 0,
408 OMAP_HDQ_CTRL_STATUS_DIR);
409 status = hdq_data->hdq_irqstatus;
410 /* check irqstatus */
411 if (!(status & OMAP_HDQ_INT_STATUS_RXCOMPLETE)) {
412 dev_dbg(hdq_data->dev, "timeout waiting for"
413 " RXCOMPLETE, %x", status);
418 /* the data is ready. Read it in! */
419 *val = hdq_reg_in(hdq_data, OMAP_HDQ_RX_DATA);
421 mutex_unlock(&hdq_data->hdq_mutex);
427 /* Enable clocks and set the controller to HDQ/1W mode */
428 static int omap_hdq_get(struct hdq_data *hdq_data)
432 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
438 if (OMAP_HDQ_MAX_USER == hdq_data->hdq_usecount) {
439 dev_dbg(hdq_data->dev, "attempt to exceed the max use count");
443 hdq_data->hdq_usecount++;
444 try_module_get(THIS_MODULE);
445 if (1 == hdq_data->hdq_usecount) {
447 pm_runtime_get_sync(hdq_data->dev);
449 /* make sure HDQ/1W is out of reset */
450 if (!(hdq_reg_in(hdq_data, OMAP_HDQ_SYSSTATUS) &
451 OMAP_HDQ_SYSSTATUS_RESETDONE)) {
452 ret = _omap_hdq_reset(hdq_data);
454 /* back up the count */
455 hdq_data->hdq_usecount--;
457 /* select HDQ/1W mode & enable clocks */
458 hdq_reg_out(hdq_data, OMAP_HDQ_CTRL_STATUS,
459 OMAP_HDQ_CTRL_STATUS_CLOCKENABLE |
460 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK |
462 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
463 OMAP_HDQ_SYSCONFIG_NOIDLE);
464 hdq_reg_in(hdq_data, OMAP_HDQ_INT_STATUS);
470 mutex_unlock(&hdq_data->hdq_mutex);
475 /* Disable clocks to the module */
476 static int omap_hdq_put(struct hdq_data *hdq_data)
480 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
484 hdq_reg_out(hdq_data, OMAP_HDQ_SYSCONFIG,
485 OMAP_HDQ_SYSCONFIG_AUTOIDLE);
486 if (0 == hdq_data->hdq_usecount) {
487 dev_dbg(hdq_data->dev, "attempt to decrement use count"
491 hdq_data->hdq_usecount--;
492 module_put(THIS_MODULE);
493 if (0 == hdq_data->hdq_usecount)
494 pm_runtime_put_sync(hdq_data->dev);
496 mutex_unlock(&hdq_data->hdq_mutex);
502 * W1 triplet callback function - used for searching ROM addresses.
503 * Registered only when controller is in 1-wire mode.
505 static u8 omap_w1_triplet(void *_hdq, u8 bdir)
509 u8 ret = 0x3; /* no slaves responded */
510 struct hdq_data *hdq_data = _hdq;
511 u8 ctrl = OMAP_HDQ_CTRL_STATUS_SINGLE | OMAP_HDQ_CTRL_STATUS_GO |
512 OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK;
513 u8 mask = ctrl | OMAP_HDQ_CTRL_STATUS_DIR;
517 err = mutex_lock_interruptible(&hdq_data->hdq_mutex);
519 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
523 hdq_data->hdq_irqstatus = 0;
525 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
526 ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
527 err = wait_event_timeout(hdq_wait_queue,
528 (hdq_data->hdq_irqstatus
529 & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
532 dev_dbg(hdq_data->dev, "RX wait elapsed\n");
535 id_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
537 hdq_data->hdq_irqstatus = 0;
539 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS,
540 ctrl | OMAP_HDQ_CTRL_STATUS_DIR, mask);
541 err = wait_event_timeout(hdq_wait_queue,
542 (hdq_data->hdq_irqstatus
543 & OMAP_HDQ_INT_STATUS_RXCOMPLETE),
546 dev_dbg(hdq_data->dev, "RX wait elapsed\n");
549 comp_bit = (hdq_reg_in(_hdq, OMAP_HDQ_RX_DATA) & 0x01);
551 if (id_bit && comp_bit) {
552 ret = 0x03; /* no slaves responded */
555 if (!id_bit && !comp_bit) {
556 /* Both bits are valid, take the direction given */
557 ret = bdir ? 0x04 : 0;
559 /* Only one bit is valid, take that direction */
561 ret = id_bit ? 0x05 : 0x02;
565 hdq_reg_out(_hdq, OMAP_HDQ_TX_DATA, bdir);
566 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, ctrl, mask);
567 err = wait_event_timeout(hdq_wait_queue,
568 (hdq_data->hdq_irqstatus
569 & OMAP_HDQ_INT_STATUS_TXCOMPLETE),
572 dev_dbg(hdq_data->dev, "TX wait elapsed\n");
576 hdq_reg_merge(_hdq, OMAP_HDQ_CTRL_STATUS, 0,
577 OMAP_HDQ_CTRL_STATUS_SINGLE);
580 mutex_unlock(&hdq_data->hdq_mutex);
587 static u8 omap_w1_reset_bus(void *_hdq)
590 omap_hdq_break(_hdq);
595 /* Read a byte of data from the device */
596 static u8 omap_w1_read_byte(void *_hdq)
598 struct hdq_data *hdq_data = _hdq;
602 /* First write to initialize the transfer */
603 if (hdq_data->init_trans == 0)
604 omap_hdq_get(hdq_data);
606 ret = hdq_read_byte(hdq_data, &val);
608 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
610 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
613 hdq_data->init_trans = 0;
614 mutex_unlock(&hdq_data->hdq_mutex);
615 omap_hdq_put(hdq_data);
619 hdq_disable_interrupt(hdq_data, OMAP_HDQ_CTRL_STATUS,
620 ~OMAP_HDQ_CTRL_STATUS_INTERRUPTMASK);
621 hdq_data->hdq_usecount = 0;
623 /* Write followed by a read, release the module */
624 if (hdq_data->init_trans) {
625 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
627 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
630 hdq_data->init_trans = 0;
631 mutex_unlock(&hdq_data->hdq_mutex);
632 omap_hdq_put(hdq_data);
638 /* Write a byte of data to the device */
639 static void omap_w1_write_byte(void *_hdq, u8 byte)
641 struct hdq_data *hdq_data = _hdq;
645 /* First write to initialize the transfer */
646 if (hdq_data->init_trans == 0)
647 omap_hdq_get(hdq_data);
650 * We need to reset the slave before
651 * issuing the SKIP ROM command, else
652 * the slave will not work.
654 if (byte == W1_SKIP_ROM)
655 omap_hdq_break(hdq_data);
657 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
659 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
662 hdq_data->init_trans++;
663 mutex_unlock(&hdq_data->hdq_mutex);
665 ret = hdq_write_byte(hdq_data, byte, &status);
667 dev_dbg(hdq_data->dev, "TX failure:Ctrl status %x\n", status);
671 /* Second write, data transferred. Release the module */
672 if (hdq_data->init_trans > 1) {
673 omap_hdq_put(hdq_data);
674 ret = mutex_lock_interruptible(&hdq_data->hdq_mutex);
676 dev_dbg(hdq_data->dev, "Could not acquire mutex\n");
679 hdq_data->init_trans = 0;
680 mutex_unlock(&hdq_data->hdq_mutex);
684 static int omap_hdq_probe(struct platform_device *pdev)
686 struct device *dev = &pdev->dev;
687 struct hdq_data *hdq_data;
688 struct resource *res;
693 hdq_data = devm_kzalloc(dev, sizeof(*hdq_data), GFP_KERNEL);
695 dev_dbg(&pdev->dev, "unable to allocate memory\n");
700 platform_set_drvdata(pdev, hdq_data);
702 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
703 hdq_data->hdq_base = devm_ioremap_resource(dev, res);
704 if (IS_ERR(hdq_data->hdq_base))
705 return PTR_ERR(hdq_data->hdq_base);
707 hdq_data->hdq_usecount = 0;
709 mutex_init(&hdq_data->hdq_mutex);
711 pm_runtime_enable(&pdev->dev);
712 ret = pm_runtime_get_sync(&pdev->dev);
714 dev_dbg(&pdev->dev, "pm_runtime_get_sync failed\n");
718 ret = _omap_hdq_reset(hdq_data);
720 dev_dbg(&pdev->dev, "reset failed\n");
724 rev = hdq_reg_in(hdq_data, OMAP_HDQ_REVISION);
725 dev_info(&pdev->dev, "OMAP HDQ Hardware Rev %c.%c. Driver in %s mode\n",
726 (rev >> 4) + '0', (rev & 0x0f) + '0', "Interrupt");
728 spin_lock_init(&hdq_data->hdq_spinlock);
730 irq = platform_get_irq(pdev, 0);
736 ret = devm_request_irq(dev, irq, hdq_isr, 0, "omap_hdq", hdq_data);
738 dev_dbg(&pdev->dev, "could not request irq\n");
742 omap_hdq_break(hdq_data);
744 pm_runtime_put_sync(&pdev->dev);
746 ret = of_property_read_string(pdev->dev.of_node, "ti,mode", &mode);
747 if (ret < 0 || !strcmp(mode, "hdq")) {
749 omap_w1_master.search = omap_w1_search_bus;
752 omap_w1_master.triplet = omap_w1_triplet;
755 omap_w1_master.data = hdq_data;
757 ret = w1_add_master_device(&omap_w1_master);
759 dev_dbg(&pdev->dev, "Failure in registering w1 master\n");
766 pm_runtime_put_sync(&pdev->dev);
768 pm_runtime_disable(&pdev->dev);
773 static int omap_hdq_remove(struct platform_device *pdev)
775 struct hdq_data *hdq_data = platform_get_drvdata(pdev);
777 mutex_lock(&hdq_data->hdq_mutex);
779 if (hdq_data->hdq_usecount) {
780 dev_dbg(&pdev->dev, "removed when use count is not zero\n");
781 mutex_unlock(&hdq_data->hdq_mutex);
785 mutex_unlock(&hdq_data->hdq_mutex);
787 /* remove module dependency */
788 pm_runtime_disable(&pdev->dev);
793 module_platform_driver(omap_hdq_driver);
795 module_param(w1_id, int, S_IRUSR);
796 MODULE_PARM_DESC(w1_id, "1-wire id for the slave detection in HDQ mode");
798 MODULE_AUTHOR("Texas Instruments");
799 MODULE_DESCRIPTION("HDQ-1W driver Library");
800 MODULE_LICENSE("GPL");