drivers/video/tegrafb.c

   1 /*
   2  * drivers/video/tegrafb.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Colin Cross <ccross@android.com>
   6  *         Travis Geiselbrecht <travis@palm.com>
   7  *
   8  * This software is licensed under the terms of the GNU General Public
   9  * License version 2, as published by the Free Software Foundation, and
  10  * may be copied, distributed, and modified under those terms.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  */
  18
  19 #include <linux/fb.h>
  20 #include <linux/module.h>
  21 #include <linux/kernel.h>
  22 #include <linux/errno.h>
  23 #include <linux/string.h>
  24 #include <linux/mm.h>
  25 #include <linux/slab.h>
  26 #include <linux/delay.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/interrupt.h>
  29 #include <linux/clk.h>
  30 #include <linux/wait.h>
  31 #include <asm/cacheflush.h>
  32 #include <mach/tegra_fb.h>
  33
  34 #define DC_CMD_GENERAL_INCR_SYNCPT              0x000
  35 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL        0x001
  36 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR        0x002
  37 #define DC_CMD_WIN_A_INCR_SYNCPT                0x008
  38 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL          0x009
  39 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR          0x00a
  40 #define DC_CMD_WIN_B_INCR_SYNCPT                0x010
  41 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL          0x011
  42 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR          0x012
  43 #define DC_CMD_WIN_C_INCR_SYNCPT                0x018
  44 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL          0x019
  45 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR          0x01a
  46 #define DC_CMD_CONT_SYNCPT_VSYNC                0x028
  47 #define DC_CMD_DISPLAY_COMMAND_OPTION0          0x031
  48 #define DC_CMD_DISPLAY_COMMAND                  0x032
  49 #define DC_CMD_SIGNAL_RAISE                     0x033
  50 #define DC_CMD_INT_STATUS                       0x037
  51 #define DC_CMD_INT_MASK                         0x038
  52 #define DC_CMD_INT_ENABLE                       0x039
  53 #define DC_CMD_INT_TYPE                         0x03a
  54 #define DC_CMD_INT_POLARITY                     0x03b
  55 #define DC_CMD_SIGNAL_RAISE1                    0x03c
  56 #define DC_CMD_SIGNAL_RAISE2                    0x03d
  57 #define DC_CMD_SIGNAL_RAISE3                    0x03e
  58 #define DC_CMD_STATE_ACCESS                     0x040
  59 #define DC_CMD_STATE_CONTROL                    0x041
  60 #define DC_CMD_DISPLAY_WINDOW_HEADER            0x042
  61 #define DC_CMD_REG_ACT_CONTROL                  0x043
  62 #define DC_WINC_A_COLOR_PALETTE                 0x500
  63 #define DC_WINC_A_PALETTE_COLOR_EXT             0x600
  64 #define DC_WIN_A_WIN_OPTIONS                    0x700
  65 #define DC_WIN_A_BYTE_SWAP                      0x701
  66 #define DC_WIN_A_BUFFER_CONTROL                 0x702
  67 #define DC_WIN_A_COLOR_DEPTH                    0x703
  68 #define DC_WIN_A_POSITION                       0x704
  69 #define DC_WIN_A_SIZE                           0x705
  70 #define DC_WIN_A_PRESCALED_SIZE                 0x706
  71 #define DC_WIN_A_H_INITIAL_DDA                  0x707
  72 #define DC_WIN_A_V_INITIAL_DDA                  0x708
  73 #define DC_WIN_A_DDA_INCREMENT                  0x709
  74 #define DC_WIN_A_LINE_STRIDE                    0x70a
  75 #define DC_WIN_A_BUF_STRIDE                     0x70b
  76 #define DC_WINBUF_A_START_ADDR                  0x800
  77 #define DC_WINBUF_A_ADDR_H_OFFSET               0x806
  78 #define DC_WINBUF_A_ADDR_V_OFFSET               0x808
  79
  80
  81 #define DC_INT_CTXSW                            (1<<0)
  82 #define DC_INT_FRAME_END                        (1<<1)
  83 #define DC_INT_V_BLANK                          (1<<2)
  84 #define DC_INT_H_BLANK                          (1<<3)
  85 #define DC_INT_V_PULSE3                         (1<<4)
  86
  87 #define DC_COLOR_DEPTH_P1                       0
  88 #define DC_COLOR_DEPTH_P2                       1
  89 #define DC_COLOR_DEPTH_P4                       2
  90 #define DC_COLOR_DEPTH_P8                       3
  91 #define DC_COLOR_DEPTH_B4G4R4A4                 4
  92 #define DC_COLOR_DEPTH_B5G5R5A                  5
  93 #define DC_COLOR_DEPTH_B5G6R5                   6
  94 #define DC_COLOR_DEPTH_AB5G5R5                  7
  95 #define DC_COLOR_DEPTH_B8G8R8A8                 12
  96 #define DC_COLOR_DEPTH_R8G8B8A8                 13
  97 #define DC_COLOR_DEPTH_B6x2G6x2R6x2A8           14
  98 #define DC_COLOR_DEPTH_R6x2G6x2B6x2A8           15
  99 #define DC_COLOR_DEPTH_YCbCr422                 16
 100 #define DC_COLOR_DEPTH_YUV422                   17
 101 #define DC_COLOR_DEPTH_YCbCr420P                18
 102 #define DC_COLOR_DEPTH_YUV420P                  19
 103 #define DC_COLOR_DEPTH_YCbCr422P                20
 104 #define DC_COLOR_DEPTH_YUV422P                  21
 105 #define DC_COLOR_DEPTH_YCbCr422R                22
 106 #define DC_COLOR_DEPTH_YUV422R                  23
 107 #define DC_COLOR_DEPTH_YCbCr422RA               24
 108 #define DC_COLOR_DEPTH_YUV422RA                 25
 109
 110 struct tegra_fb_info {
 111         struct clk *clk;
 112         struct resource *reg_mem;
 113         struct resource *fb_mem;
 114         void __iomem *reg_base;
 115         wait_queue_head_t event_wq;
 116         unsigned int wait_condition;
 117         /* Resolution of the output to the LCD.  If different from the
 118            framebuffer resolution, the Tegra display block will scale it */
 119         int lcd_xres;
 120         int lcd_yres;
 121         int irq;
 122 };
 123
 124 static void tegra_fb_writel(struct tegra_fb_info *tegra_fb, u32 val, unsigned long reg)
 125 {
 126         writel(val, tegra_fb->reg_base + reg*sizeof(u32));
 127 }
 128
 129 static u32 tegra_fb_readl(struct tegra_fb_info *tegra_fb, unsigned long reg)
 130 {
 131         return readl(tegra_fb->reg_base + reg*sizeof(u32));
 132 }
 133
 134 /* palette attary used by the fbcon */
 135 u32 pseudo_palette[16];
 136
 137 irqreturn_t tegra_fb_irq(int irq, void *ptr)
 138 {
 139         struct fb_info *info = ptr;
 140         struct tegra_fb_info *tegra_fb = info->par;
 141
 142         u32 reg = tegra_fb_readl(tegra_fb, DC_CMD_INT_STATUS);
 143         tegra_fb_writel(tegra_fb, reg, DC_CMD_INT_STATUS);
 144
 145         tegra_fb->wait_condition = 1;
 146         wake_up(&tegra_fb->event_wq);
 147         return IRQ_HANDLED;
 148 }
 149
 150 static int tegra_fb_wait_for_event(struct tegra_fb_info *tegra_fb, unsigned long timeout, u32 irq_mask)
 151 {
 152         u32 reg;
 153
 154         tegra_fb->wait_condition = 0;
 155
 156         reg = tegra_fb_readl(tegra_fb, DC_CMD_INT_MASK);
 157         reg |= irq_mask;
 158         tegra_fb_writel(tegra_fb, reg, DC_CMD_INT_MASK);
 159
 160         /* Clear any pending interrupt */
 161         tegra_fb_writel(tegra_fb, irq_mask, DC_CMD_INT_STATUS);
 162
 163         tegra_fb_writel(tegra_fb, irq_mask, DC_CMD_INT_ENABLE);
 164
 165         /* Wait for the irq to fire */
 166         wait_event_interruptible_timeout(tegra_fb->event_wq, tegra_fb->wait_condition, timeout);
 167
 168         tegra_fb_writel(tegra_fb, 0, DC_CMD_INT_ENABLE);
 169
 170         if (!tegra_fb->wait_condition) {
 171                 pr_warning("%s: wait for vsync timed out\n", __func__);
 172                 return -ETIMEDOUT;
 173         }
 174         return 0;
 175 }
 176
 177 /* Writes to many registers in the display block are buffered.
 178  * tegra_fb_activate requests an update of the main registers from their
 179  * double-buffered registers, which takes effect at the end of the next frame,
 180  * and then waits for the frame_end IRQ.
 181  */
 182 static void tegra_fb_activate(struct tegra_fb_info *tegra_fb)
 183 {
 184         int vsync_count = 0;
 185
 186         if (unlikely(tegra_fb_readl(tegra_fb, DC_CMD_STATE_CONTROL) & 3)) {
 187                 pr_warning("%s: update already activated!\n", __func__);
 188                 return;
 189         }
 190
 191         tegra_fb_writel(tegra_fb, (1 << 8) | (1 << 9), DC_CMD_STATE_CONTROL);
 192         tegra_fb_writel(tegra_fb, (1 << 0) | (1 << 1), DC_CMD_STATE_CONTROL);
 193         while (tegra_fb_readl(tegra_fb, DC_CMD_STATE_CONTROL) & 3) {
 194                 vsync_count++;
 195                 if (tegra_fb_wait_for_event(tegra_fb, HZ/10, DC_INT_FRAME_END))
 196                         break;
 197         }
 198         if (unlikely(vsync_count > 1))
 199                 pr_warning("%s: waited for %d vsyncs\n", __func__, vsync_count);
 200 }
 201
 202
 203 static int tegra_fb_open(struct fb_info *info, int user)
 204 {
 205         return 0;
 206 }
 207
 208 static int tegra_fb_release(struct fb_info *info, int user)
 209 {
 210         return 0;
 211 }
 212
 213 static int tegra_fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 214 {
 215         if ((var->xres != info->var.xres) ||
 216             (var->yres != info->var.yres) ||
 217             (var->xres_virtual != info->var.xres_virtual) ||
 218             (var->yres_virtual != info->var.yres_virtual) ||
 219             (var->grayscale != info->var.grayscale))
 220                 return -EINVAL;
 221         return 0;
 222 }
 223
 224 static int tegra_fb_set_par(struct fb_info *info)
 225 {
 226         struct tegra_fb_info *tegra_fb = info->par;
 227         struct fb_var_screeninfo *var = &info->var;
 228         struct fb_fix_screeninfo *fix = &info->fix;
 229         u32 color_depth;
 230         unsigned int h_dda;
 231         unsigned int v_dda;
 232
 233         /* we only support RGB ordering for now */
 234         switch (var->bits_per_pixel) {
 235         case 32:
 236         case 24:
 237                 var->red.offset = 0;
 238                 var->red.length = 8;
 239                 var->green.offset = 8;
 240                 var->green.length = 8;
 241                 var->blue.offset = 16;
 242                 var->blue.length = 8;
 243                 color_depth = DC_COLOR_DEPTH_B8G8R8A8;
 244                 break;
 245         case 16:
 246                 var->red.offset = 11;
 247                 var->red.length = 5;
 248                 var->green.offset = 5;
 249                 var->green.length = 6;
 250                 var->blue.offset = 0;
 251                 var->blue.length = 5;
 252                 color_depth = DC_COLOR_DEPTH_B5G6R5;
 253                 break;
 254         default:
 255                 return -EINVAL;
 256         }
 257         fix->line_length = var->xres * var->bits_per_pixel / 8;
 258
 259         h_dda = (var->xres * 0x1000) / (tegra_fb->lcd_xres - 1);
 260         v_dda = (var->yres * 0x1000) / (tegra_fb->lcd_yres - 1);
 261
 262         tegra_fb_writel(tegra_fb, tegra_fb->lcd_yres<<16 | tegra_fb->lcd_xres,
 263                 DC_WIN_A_SIZE);
 264         tegra_fb_writel(tegra_fb, var->yres<<16 | fix->line_length,
 265                 DC_WIN_A_PRESCALED_SIZE);
 266         tegra_fb_writel(tegra_fb, 0, DC_WIN_A_H_INITIAL_DDA);
 267         tegra_fb_writel(tegra_fb, 0, DC_WIN_A_V_INITIAL_DDA);
 268         tegra_fb_writel(tegra_fb, v_dda << 16 | h_dda, DC_WIN_A_DDA_INCREMENT);
 269         tegra_fb_writel(tegra_fb, color_depth, DC_WIN_A_COLOR_DEPTH);
 270         tegra_fb_writel(tegra_fb, fix->line_length, DC_WIN_A_LINE_STRIDE);
 271         return 0;
 272 }
 273
 274 static int tegra_fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 275         unsigned blue, unsigned transp, struct fb_info *info)
 276 {
 277         struct fb_var_screeninfo *var = &info->var;
 278
 279         if (info->fix.visual == FB_VISUAL_TRUECOLOR ||
 280             info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
 281                 u32 v;
 282
 283                 if (regno >= 16)
 284                         return -EINVAL;
 285
 286                 v = (red << var->red.offset) |
 287                         (green << var->green.offset) |
 288                         (blue << var->blue.offset);
 289
 290                 ((u32 *)info->pseudo_palette)[regno] = v;
 291         }
 292
 293         return 0;
 294 }
 295
 296 static int tegra_fb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 297 {
 298         struct tegra_fb_info *tegra_fb = info->par;
 299         char __iomem *flush_start;
 300         char __iomem *flush_end;
 301         u32 addr;
 302
 303         flush_start = info->screen_base + (var->yoffset * info->fix.line_length);
 304         flush_end = flush_start + (var->yres * info->fix.line_length);
 305
 306         info->var.xoffset = var->xoffset;
 307         info->var.yoffset = var->yoffset;
 308
 309         addr = info->fix.smem_start + (var->yoffset * info->fix.line_length) +
 310                 (var->xoffset * (var->bits_per_pixel/8));
 311
 312         tegra_fb_writel(tegra_fb, addr, DC_WINBUF_A_START_ADDR);
 313         tegra_fb_activate(tegra_fb);
 314         return 0;
 315 }
 316
 317 static void tegra_fb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
 318 {
 319         cfb_fillrect(info, rect);
 320 }
 321
 322 static void tegra_fb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
 323 {
 324         cfb_copyarea(info, region);
 325 }
 326
 327 static void tegra_fb_imageblit(struct fb_info *info, const struct fb_image *image)
 328 {
 329         cfb_imageblit(info, image);
 330 }
 331
 332 #ifdef DEBUG
 333 #define DUMP_REG(a) dev_dbg(info->dev, "%-32s\t%03x\t%08x\n", #a, a, tegra_fb_readl(tegra_fb, a));
 334 static void dump_regs(struct fb_info *info)
 335 {
 336         struct tegra_fb_info *tegra_fb = info->par;
 337
 338         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
 339         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 340         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
 341         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
 342         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
 343         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
 344         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
 345         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
 346         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
 347         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
 348         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
 349         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
 350         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
 351         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 352         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 353         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 354         DUMP_REG(DC_CMD_INT_STATUS);
 355         DUMP_REG(DC_CMD_INT_MASK);
 356         DUMP_REG(DC_CMD_INT_ENABLE);
 357         DUMP_REG(DC_CMD_INT_TYPE);
 358         DUMP_REG(DC_CMD_INT_POLARITY);
 359         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 360         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 361         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 362         DUMP_REG(DC_CMD_STATE_ACCESS);
 363         DUMP_REG(DC_CMD_STATE_CONTROL);
 364         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 365         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 366         tegra_fb_writel(tegra_fb, 1<<4, DC_CMD_DISPLAY_WINDOW_HEADER);
 367         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 368         DUMP_REG(DC_WINC_A_COLOR_PALETTE);
 369         DUMP_REG(DC_WINC_A_PALETTE_COLOR_EXT);
 370         DUMP_REG(DC_WIN_A_WIN_OPTIONS);
 371         DUMP_REG(DC_WIN_A_BYTE_SWAP);
 372         DUMP_REG(DC_WIN_A_BUFFER_CONTROL);
 373         DUMP_REG(DC_WIN_A_COLOR_DEPTH);
 374         DUMP_REG(DC_WIN_A_POSITION);
 375         DUMP_REG(DC_WIN_A_SIZE);
 376         DUMP_REG(DC_WIN_A_PRESCALED_SIZE);
 377         DUMP_REG(DC_WIN_A_H_INITIAL_DDA);
 378         DUMP_REG(DC_WIN_A_V_INITIAL_DDA);
 379         DUMP_REG(DC_WIN_A_DDA_INCREMENT);
 380         DUMP_REG(DC_WIN_A_LINE_STRIDE);
 381         DUMP_REG(DC_WIN_A_BUF_STRIDE);
 382         DUMP_REG(DC_WINBUF_A_START_ADDR);
 383         DUMP_REG(DC_WINBUF_A_ADDR_H_OFFSET);
 384         DUMP_REG(DC_WINBUF_A_ADDR_V_OFFSET);
 385 }
 386 #endif
 387
 388 static struct fb_ops tegra_fb_ops = {
 389         .owner = THIS_MODULE,
 390         .fb_open = tegra_fb_open,
 391         .fb_release = tegra_fb_release,
 392         .fb_check_var = tegra_fb_check_var,
 393         .fb_set_par = tegra_fb_set_par,
 394         .fb_setcolreg = tegra_fb_setcolreg,
 395         .fb_pan_display = tegra_fb_pan_display,
 396         .fb_fillrect = tegra_fb_fillrect,
 397         .fb_copyarea = tegra_fb_copyarea,
 398         .fb_imageblit = tegra_fb_imageblit,
 399 };
 400
 401 static int tegra_plat_probe(struct platform_device *pdev)
 402 {
 403         struct fb_info *info;
 404         struct tegra_fb_info *tegra_fb;
 405         struct clk *clk;
 406         struct resource *res;
 407         struct resource *reg_mem;
 408         struct resource *fb_mem;
 409         int ret = 0;
 410         void __iomem *reg_base;
 411         void __iomem *fb_base;
 412         unsigned long fb_size;
 413         unsigned long fb_phys;
 414         int irq;
 415         const struct tegra_fb_lcd_data *lcd_data = pdev->dev.platform_data;
 416
 417         info = framebuffer_alloc(sizeof(struct tegra_fb_info), &pdev->dev);
 418         if (!info) {
 419                 ret = -ENOMEM;
 420                 goto err;
 421         }
 422
 423         irq = platform_get_irq(pdev, 0);
 424         if (irq <= 0) {
 425                 dev_err(&pdev->dev, "%s: no irq\n", pdev->name);
 426                 ret = -ENOENT;
 427                 goto err_free;
 428         }
 429
 430         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 431         if (!res) {
 432                 dev_err(&pdev->dev, "%s: no mem resource\n", pdev->name);
 433                 ret = -ENOENT;
 434                 goto err_free;
 435         }
 436
 437         reg_mem = request_mem_region(res->start, resource_size(res), pdev->name);
 438         if (!reg_mem) {
 439                 dev_err(&pdev->dev, "%s: request_mem_region failed\n", pdev->name);
 440                 ret = -EBUSY;
 441                 goto err_free;
 442         }
 443
 444         reg_base = ioremap(res->start, resource_size(res));
 445         if (!reg_base) {
 446                 dev_err(&pdev->dev, "%s: registers can't be mapped\n", pdev->name);
 447                 ret = -EBUSY;
 448                 goto err_release_resource_reg;
 449         }
 450
 451         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 452         if (!res) {
 453                 dev_err(&pdev->dev, "%s: no mem resource\n", pdev->name);
 454                 ret = -ENOENT;
 455                 goto err_iounmap_reg;
 456         }
 457
 458         fb_mem = request_mem_region(res->start, resource_size(res), pdev->name);
 459         if (!fb_mem) {
 460                 dev_err(&pdev->dev, "%s: request_mem_region failed\n", pdev->name);
 461                 ret = -EBUSY;
 462                 goto err_iounmap_reg;
 463         }
 464
 465         fb_size = resource_size(res);
 466         fb_phys = res->start;
 467         fb_base = ioremap_nocache(fb_phys, fb_size);
 468         if (!fb_base) {
 469                 dev_err(&pdev->dev, "%s: fb can't be mapped\n", pdev->name);
 470                 ret = -EBUSY;
 471                 goto err_release_resource_fb;
 472         }
 473
 474         clk = clk_get(&pdev->dev, NULL);
 475         if (!clk) {
 476                 dev_err(&pdev->dev, "%s: can't get clock\n", pdev->name);
 477                 ret = -ENOENT;
 478                 goto err_iounmap_fb;
 479         }
 480         clk_enable(clk);
 481
 482         tegra_fb = info->par;
 483         tegra_fb->clk = clk;
 484         tegra_fb->fb_mem = fb_mem;
 485         tegra_fb->reg_mem = reg_mem;
 486         tegra_fb->reg_base = reg_base;
 487         tegra_fb->irq = irq;
 488         tegra_fb->lcd_xres = lcd_data->lcd_xres;
 489         tegra_fb->lcd_yres = lcd_data->lcd_yres;
 490
 491         info->fbops = &tegra_fb_ops;
 492         info->pseudo_palette = pseudo_palette;
 493         info->screen_base = fb_base;
 494         info->screen_size = fb_size;
 495
 496         strlcpy(info->fix.id, "tegra_fb", sizeof(info->fix.id));
 497         info->fix.type = FB_TYPE_PACKED_PIXELS;
 498         info->fix.visual = FB_VISUAL_TRUECOLOR;
 499         info->fix.xpanstep   = 1;
 500         info->fix.ypanstep   = 1;
 501         info->fix.accel   = FB_ACCEL_NONE;
 502         info->fix.smem_start = fb_phys;
 503         info->fix.smem_len = fb_size;
 504
 505         info->var.xres                  = lcd_data->fb_xres;
 506         info->var.yres                  = lcd_data->fb_yres;
 507         info->var.xres_virtual          = lcd_data->fb_xres;
 508         info->var.yres_virtual          = lcd_data->fb_yres*2;
 509         info->var.bits_per_pixel        = lcd_data->bits_per_pixel;
 510         info->var.activate              = FB_ACTIVATE_NOW;
 511         info->var.height                = -1;
 512         info->var.width                 = -1;
 513         info->var.pixclock              = 24500;
 514         info->var.left_margin           = 0;
 515         info->var.right_margin          = 0;
 516         info->var.upper_margin          = 0;
 517         info->var.lower_margin          = 0;
 518         info->var.hsync_len             = 0;
 519         info->var.vsync_len             = 0;
 520         info->var.vmode                 = FB_VMODE_NONINTERLACED;
 521
 522         if (request_irq(irq, tegra_fb_irq, IRQF_DISABLED,
 523                         dev_name(&pdev->dev), info)) {
 524                 pr_debug("%s: request_irq %d failed\n",
 525                         pdev->name, irq);
 526                 ret = -EBUSY;
 527                 goto err_clk_disable;
 528         }
 529
 530         init_waitqueue_head(&tegra_fb->event_wq);
 531
 532         /* Enable writes to Window A */
 533         tegra_fb_writel(tegra_fb, 1<<4, DC_CMD_DISPLAY_WINDOW_HEADER);
 534
 535 #ifdef DEBUG
 536         info->dev = &pdev->dev;
 537         dev_dbg(info->dev, "Framebuffer registers before init:\n");
 538         dump_regs(info);
 539 #endif
 540
 541         tegra_fb_set_par(info);
 542
 543 #ifdef DEBUG
 544         dev_dbg(info->dev, "Framebuffer registers after init:\n");
 545         dump_regs(info);
 546 #endif
 547
 548         dev_info(&pdev->dev, "base address: %08x (%08x)\n",
 549                         (unsigned int)info->fix.smem_start,
 550                         (unsigned int)info->screen_base);
 551
 552         if (register_framebuffer(info)) {
 553                 dev_err(&pdev->dev, "failed to register framebuffer\n");
 554                 ret = -ENODEV;
 555                 goto err_free_irq;
 556         }
 557         platform_set_drvdata(pdev, info);
 558         return 0;
 559
 560 err_free_irq:
 561         free_irq(irq, info);
 562 err_clk_disable:
 563         clk_disable(clk);
 564 err_iounmap_fb:
 565         iounmap(fb_base);
 566 err_release_resource_fb:
 567         release_resource(fb_mem);
 568 err_iounmap_reg:
 569         iounmap(reg_base);
 570 err_release_resource_reg:
 571         release_resource(reg_mem);
 572 err_free:
 573         framebuffer_release(info);
 574 err:
 575         return ret;
 576 }
 577
 578 static int tegra_plat_remove(struct platform_device *pdev)
 579 {
 580         struct fb_info *info = platform_get_drvdata(pdev);
 581         struct tegra_fb_info *tegra_fb = info->par;
 582         unregister_framebuffer(info);
 583         free_irq(tegra_fb->irq, info);
 584         clk_disable(tegra_fb->clk);
 585         iounmap(info->screen_base);
 586         release_resource(tegra_fb->fb_mem);
 587         iounmap(tegra_fb->reg_base);
 588         release_resource(tegra_fb->reg_mem);
 589         framebuffer_release(info);
 590         return 0;
 591 }
 592
 593 struct platform_driver tegra_platform_driver = {
 594         .probe = tegra_plat_probe,
 595         .remove = tegra_plat_remove,
 596         .driver = {
 597                 .name = "tegrafb",
 598                 .owner = THIS_MODULE,
 599         },
 600 };
 601
 602 static int __init tegra_fb_init(void)
 603 {
 604         int e;
 605         e = platform_driver_register(&tegra_platform_driver);
 606         if (e) {
 607                 pr_info("tegrafb: platform_driver_register failed\n");
 608                 return e;
 609         }
 610         return e;
 611 }
 612
 613 static void __exit tegra_exit(void)
 614 {
 615         platform_driver_unregister(&tegra_platform_driver);
 616 }
 617
 618 module_exit(tegra_exit);
 619 module_init(tegra_fb_init);