drivers/video/tegra/dc/hdmi.c

   1 /*
   2  * drivers/video/tegra/dc/hdmi.c
   3  *
   4  * Copyright (C) 2010 Google, Inc.
   5  * Author: Erik Gilling <konkers@android.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  */
  17
  18 #include <linux/clk.h>
  19 #include <linux/delay.h>
  20 #include <linux/err.h>
  21 #include <linux/fb.h>
  22 #include <linux/gpio.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/switch.h>
  28 #include <linux/workqueue.h>
  29
  30 #include <mach/clk.h>
  31 #include <mach/dc.h>
  32 #include <mach/fb.h>
  33 #include <mach/nvhost.h>
  34
  35 #include <video/tegrafb.h>
  36
  37 #include "dc_reg.h"
  38 #include "dc_priv.h"
  39 #include "hdmi_reg.h"
  40 #include "hdmi.h"
  41 #include "edid.h"
  42 #include "nvhdcp.h"
  43
  44 /* datasheet claims this will always be 216MHz */
  45 #define HDMI_AUDIOCLK_FREQ              216000000
  46
  47 #define HDMI_REKEY_DEFAULT              56
  48
  49 struct tegra_dc_hdmi_data {
  50         struct tegra_dc                 *dc;
  51         struct tegra_edid               *edid;
  52         struct tegra_nvhdcp             *nvhdcp;
  53         struct delayed_work             work;
  54
  55         struct resource                 *base_res;
  56         void __iomem                    *base;
  57         struct clk                      *clk;
  58
  59         struct clk                      *disp1_clk;
  60         struct clk                      *disp2_clk;
  61
  62         struct switch_dev               hpd_switch;
  63
  64         spinlock_t                      suspend_lock;
  65         bool                            suspended;
  66         bool                            hpd_pending;
  67
  68         bool                            dvi;
  69 };
  70
  71 const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
  72         /* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
  73         {
  74                 .xres =         1280,
  75                 .yres =         720,
  76                 .pixclock =     KHZ2PICOS(74250),
  77                 .hsync_len =    40,     /* h_sync_width */
  78                 .vsync_len =    5,      /* v_sync_width */
  79                 .left_margin =  220,    /* h_back_porch */
  80                 .upper_margin = 20,     /* v_back_porch */
  81                 .right_margin = 110,    /* h_front_porch */
  82                 .lower_margin = 5,      /* v_front_porch */
  83                 .vmode =        FB_VMODE_NONINTERLACED,
  84                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  85         },
  86
  87         /* 720x480p 59.94hz: EIA/CEA-861-B Formats 2 & 3 */
  88         {
  89                 .xres =         720,
  90                 .yres =         480,
  91                 .pixclock =     KHZ2PICOS(27000),
  92                 .hsync_len =    62,     /* h_sync_width */
  93                 .vsync_len =    6,      /* v_sync_width */
  94                 .left_margin =  60,     /* h_back_porch */
  95                 .upper_margin = 30,     /* v_back_porch */
  96                 .right_margin = 16,     /* h_front_porch */
  97                 .lower_margin = 9,      /* v_front_porch */
  98                 .vmode =        FB_VMODE_NONINTERLACED,
  99                 .sync = 0,
 100         },
 101
 102         /* 640x480p 60hz: EIA/CEA-861-B Format 1 */
 103         {
 104                 .xres =         640,
 105                 .yres =         480,
 106                 .pixclock =     KHZ2PICOS(25200),
 107                 .hsync_len =    96,     /* h_sync_width */
 108                 .vsync_len =    2,      /* v_sync_width */
 109                 .left_margin =  48,     /* h_back_porch */
 110                 .upper_margin = 33,     /* v_back_porch */
 111                 .right_margin = 16,     /* h_front_porch */
 112                 .lower_margin = 10,     /* v_front_porch */
 113                 .vmode =        FB_VMODE_NONINTERLACED,
 114                 .sync = 0,
 115         },
 116
 117         /* 720x576p 50hz EIA/CEA-861-B Formats 17 & 18 */
 118         {
 119                 .xres =         720,
 120                 .yres =         576,
 121                 .pixclock =     KHZ2PICOS(27000),
 122                 .hsync_len =    64,     /* h_sync_width */
 123                 .vsync_len =    5,      /* v_sync_width */
 124                 .left_margin =  68,     /* h_back_porch */
 125                 .upper_margin = 39,     /* v_back_porch */
 126                 .right_margin = 12,     /* h_front_porch */
 127                 .lower_margin = 5,      /* v_front_porch */
 128                 .vmode =        FB_VMODE_NONINTERLACED,
 129                 .sync = 0,
 130         },
 131
 132         /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
 133         {
 134                 .xres =         1920,
 135                 .yres =         1080,
 136                 .pixclock =     KHZ2PICOS(148500),
 137                 .hsync_len =    44,     /* h_sync_width */
 138                 .vsync_len =    5,      /* v_sync_width */
 139                 .left_margin =  148,    /* h_back_porch */
 140                 .upper_margin = 36,     /* v_back_porch */
 141                 .right_margin = 88,     /* h_front_porch */
 142                 .lower_margin = 4,      /* v_front_porch */
 143                 .vmode =        FB_VMODE_NONINTERLACED,
 144                 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
 145         },
 146 };
 147
 148 struct tegra_hdmi_audio_config {
 149         unsigned pix_clock;
 150         unsigned n;
 151         unsigned cts;
 152 };
 153
 154 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
 155         {25200000,      4096,   25250},
 156         {27000000,      4096,   27000},
 157         {54000000,      4096,   54000},
 158         {74250000,      4096,   74250},
 159         {148500000,     4096,   148500},
 160         {0,             0,      0},
 161 };
 162
 163 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
 164         {25200000,      14112,  63125},
 165         {27000000,      6272,   30000},
 166         {54000000,      6272,   60000},
 167         {74250000,      6272,   82500},
 168         {148500000,     6272,   165000},
 169         {0,             0,      0},
 170 };
 171
 172 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
 173         {25200000,      6144,   25250},
 174         {27000000,      6144,   27000},
 175         {54000000,      6144,   54000},
 176         {74250000,      6144,   74250},
 177         {148500000,     6144,   148500},
 178         {0,             0,      0},
 179 };
 180
 181 static const struct tegra_hdmi_audio_config
 182 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
 183 {
 184         const struct tegra_hdmi_audio_config *table;
 185
 186         switch (audio_freq) {
 187         case 32000:
 188                 table = tegra_hdmi_audio_32k;
 189                 break;
 190
 191         case 44100:
 192                 table = tegra_hdmi_audio_44_1k;
 193                 break;
 194
 195         case 48000:
 196                 table = tegra_hdmi_audio_48k;
 197                 break;
 198
 199         default:
 200                 return NULL;
 201         }
 202
 203         while (table->pix_clock) {
 204                 if (table->pix_clock == pix_clock)
 205                         return table;
 206                 table++;
 207         }
 208
 209         return NULL;
 210 }
 211
 212
 213 unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
 214                                              unsigned long reg)
 215 {
 216         return readl(hdmi->base + reg * 4);
 217 }
 218
 219 void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
 220                                      unsigned long val, unsigned long reg)
 221 {
 222         writel(val, hdmi->base + reg * 4);
 223 }
 224
 225 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
 226                                          unsigned long reg, unsigned long clr,
 227                                          unsigned long set)
 228 {
 229         unsigned long val = tegra_hdmi_readl(hdmi, reg);
 230         val &= ~clr;
 231         val |= set;
 232         tegra_hdmi_writel(hdmi, val, reg);
 233 }
 234
 235 #define DUMP_REG(a) do {                                                \
 236                 printk("HDMI %-32s\t%03x\t%08lx\n",                     \
 237                        #a, a, tegra_hdmi_readl(hdmi, a));               \
 238         } while (0)
 239
 240 #ifdef DEBUG
 241 static void hdmi_dumpregs(struct tegra_dc_hdmi_data *hdmi)
 242 {
 243         DUMP_REG(HDMI_CTXSW);
 244         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
 245         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
 246         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
 247         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
 248         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
 249         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
 250         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
 251         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
 252         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
 253         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
 254         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
 255         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
 256         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
 257         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
 258         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
 259         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
 260         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
 261         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
 262         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
 263         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
 264         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
 265         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
 266         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
 267         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
 268         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
 269         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
 270         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
 271         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
 272         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
 273         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 274         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
 275         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
 276         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
 277         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
 278         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 279         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
 280         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
 281         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
 282         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
 283         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
 284         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
 285         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 286         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
 287         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
 288         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
 289         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
 290         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
 291         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
 292         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
 293         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
 294         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
 295         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
 296         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
 297         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
 298         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
 299         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 300         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 301         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
 302         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
 303         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
 304         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
 305         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
 306         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
 307         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
 308         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
 309         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
 310         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
 311         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
 312         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
 313         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 314         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
 315         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
 316         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
 317         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
 318         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
 319         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
 320         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
 321         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
 322         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
 323         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
 324         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
 325         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
 326         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
 327         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
 328         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
 329         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
 330         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
 331         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
 332         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
 333         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
 334         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
 335         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
 336         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
 337         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
 338         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
 339         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
 340         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
 341         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
 342         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
 343         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
 344         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
 345         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
 346         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
 347         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
 348         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
 349         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
 350         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
 351         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
 352         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
 353         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
 354         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
 355         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
 356         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
 357         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
 358         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
 359         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
 360         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
 361         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
 362         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
 363         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
 364         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
 365         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
 366         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
 367         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
 368         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
 369         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
 370         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
 371         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
 372         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
 373         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
 374         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
 375         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
 376         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
 377         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
 378         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
 379         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
 380         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
 381         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
 382         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
 383         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
 384         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
 385         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
 386         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
 387         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
 388         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
 389         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
 390         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
 391         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
 392         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
 393         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
 394         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
 395         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
 396         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
 397 }
 398 #endif
 399
 400 #define PIXCLOCK_TOLERANCE      200
 401
 402 static bool tegra_dc_hdmi_mode_equal(const struct fb_videomode *mode1,
 403                                         const struct fb_videomode *mode2)
 404 {
 405         return mode1->xres      == mode2->xres &&
 406                 mode1->yres     == mode2->yres &&
 407                 mode1->vmode    == mode2->vmode;
 408 }
 409
 410 static bool tegra_dc_hdmi_mode_filter(struct fb_videomode *mode)
 411 {
 412         int i;
 413         int clocks;
 414
 415         for (i = 0; i < ARRAY_SIZE(tegra_dc_hdmi_supported_modes); i++) {
 416                 if (tegra_dc_hdmi_mode_equal(&tegra_dc_hdmi_supported_modes[i],
 417                                              mode)) {
 418                         memcpy(mode, &tegra_dc_hdmi_supported_modes[i], sizeof(*mode));
 419                         mode->flag = FB_MODE_IS_DETAILED;
 420                         clocks = (mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len) *
 421                                 (mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len);
 422                         mode->refresh = (PICOS2KHZ(mode->pixclock) * 1000) / clocks;
 423                         return true;
 424                 }
 425         }
 426
 427         return false;
 428 }
 429
 430
 431 static bool tegra_dc_hdmi_hpd(struct tegra_dc *dc)
 432 {
 433         int sense;
 434         int level;
 435
 436         level = gpio_get_value(dc->out->hotplug_gpio);
 437
 438         sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
 439
 440         return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
 441                 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
 442 }
 443
 444 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
 445 {
 446         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 447         struct fb_monspecs specs;
 448         int err;
 449
 450         if (!tegra_dc_hdmi_hpd(dc))
 451                 goto fail;
 452
 453         err = tegra_edid_get_monspecs(hdmi->edid, &specs);
 454         if (err < 0) {
 455                 dev_err(&dc->ndev->dev, "error reading edid\n");
 456                 goto fail;
 457         }
 458
 459         /* monitors like to lie about these but they are still useful for
 460          * detecting aspect ratios
 461          */
 462         dc->out->h_size = specs.max_x * 1000;
 463         dc->out->v_size = specs.max_y * 1000;
 464
 465
 466         hdmi->dvi = !(specs.misc & FB_MISC_HDMI);
 467
 468         tegra_fb_update_monspecs(dc->fb, &specs, tegra_dc_hdmi_mode_filter);
 469         switch_set_state(&hdmi->hpd_switch, 1);
 470         dev_info(&dc->ndev->dev, "display detected\n");
 471         return true;
 472
 473 fail:
 474         switch_set_state(&hdmi->hpd_switch, 0);
 475         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
 476         return false;
 477 }
 478
 479
 480 static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
 481 {
 482         struct tegra_dc_hdmi_data *hdmi =
 483                 container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
 484         struct tegra_dc *dc = hdmi->dc;
 485
 486         if (!tegra_dc_hdmi_detect(dc)) {
 487                 tegra_dc_disable(dc);
 488                 tegra_fb_update_monspecs(dc->fb, NULL, NULL);
 489         }
 490 }
 491
 492 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
 493 {
 494         struct tegra_dc *dc = ptr;
 495         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 496         unsigned long flags;
 497
 498         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 499         if (hdmi->suspended) {
 500                 hdmi->hpd_pending = true;
 501         } else {
 502                 if (tegra_dc_hdmi_hpd(dc))
 503                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
 504                 else
 505                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
 506         }
 507         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 508
 509         return IRQ_HANDLED;
 510 }
 511
 512 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
 513 {
 514         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 515         unsigned long flags;
 516
 517         tegra_nvhdcp_suspend(hdmi->nvhdcp);
 518         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 519         hdmi->suspended = true;
 520         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 521 }
 522
 523 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
 524 {
 525         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 526         unsigned long flags;
 527
 528         spin_lock_irqsave(&hdmi->suspend_lock, flags);
 529         hdmi->suspended = false;
 530         if (hdmi->hpd_pending) {
 531                 if (tegra_dc_hdmi_hpd(dc))
 532                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
 533                 else
 534                         schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
 535                 hdmi->hpd_pending = false;
 536         }
 537         spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
 538 }
 539
 540 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
 541 {
 542         struct tegra_dc_hdmi_data *hdmi;
 543         struct resource *res;
 544         struct resource *base_res;
 545         void __iomem *base;
 546         struct clk *clk = NULL;
 547         struct clk *disp1_clk = NULL;
 548         struct clk *disp2_clk = NULL;
 549         int err;
 550
 551         hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
 552         if (!hdmi)
 553                 return -ENOMEM;
 554
 555         res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "hdmi_regs");
 556         if (!res) {
 557                 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
 558                 err = -ENOENT;
 559                 goto err_free_hdmi;
 560         }
 561
 562         base_res = request_mem_region(res->start, resource_size(res), dc->ndev->name);
 563         if (!base_res) {
 564                 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
 565                 err = -EBUSY;
 566                 goto err_free_hdmi;
 567         }
 568
 569         base = ioremap(res->start, resource_size(res));
 570         if (!base) {
 571                 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
 572                 err = -EBUSY;
 573                 goto err_release_resource_reg;
 574         }
 575
 576         clk = clk_get(&dc->ndev->dev, "hdmi");
 577         if (IS_ERR_OR_NULL(clk)) {
 578                 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
 579                 err = -ENOENT;
 580                 goto err_iounmap_reg;
 581         }
 582
 583         disp1_clk = clk_get_sys("tegradc.0", NULL);
 584         if (IS_ERR_OR_NULL(disp1_clk)) {
 585                 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
 586                 err = -ENOENT;
 587                 goto err_put_clock;
 588         }
 589
 590         disp2_clk = clk_get_sys("tegradc.1", NULL);
 591         if (IS_ERR_OR_NULL(disp2_clk)) {
 592                 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
 593                 err = -ENOENT;
 594                 goto err_put_clock;
 595         }
 596
 597         /* TODO: support non-hotplug */
 598         if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_hdmi_irq,
 599                         IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
 600                         dev_name(&dc->ndev->dev), dc)) {
 601                 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed\n",
 602                         gpio_to_irq(dc->out->hotplug_gpio));
 603                 err = -EBUSY;
 604                 goto err_put_clock;
 605         }
 606         enable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
 607
 608         hdmi->edid = tegra_edid_create(dc->out->dcc_bus);
 609         if (IS_ERR_OR_NULL(hdmi->edid)) {
 610                 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
 611                 err = PTR_ERR(hdmi->edid);
 612                 goto err_free_irq;
 613         }
 614
 615         hdmi->nvhdcp = tegra_nvhdcp_create(hdmi, dc->ndev->id,
 616                         dc->out->dcc_bus);
 617         if (IS_ERR_OR_NULL(hdmi->nvhdcp)) {
 618                 dev_err(&dc->ndev->dev, "hdmi: can't create nvhdcp\n");
 619                 err = PTR_ERR(hdmi->nvhdcp);
 620                 goto err_edid_destroy;
 621         }
 622
 623         INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
 624
 625         hdmi->dc = dc;
 626         hdmi->base = base;
 627         hdmi->base_res = base_res;
 628         hdmi->clk = clk;
 629         hdmi->disp1_clk = disp1_clk;
 630         hdmi->disp2_clk = disp2_clk;
 631         hdmi->suspended = false;
 632         hdmi->hpd_pending = false;
 633         spin_lock_init(&hdmi->suspend_lock);
 634
 635         hdmi->hpd_switch.name = "hdmi";
 636         switch_dev_register(&hdmi->hpd_switch);
 637
 638         dc->out->depth = 24;
 639
 640         tegra_dc_set_outdata(dc, hdmi);
 641
 642         /* boards can select default content protection policy */
 643         if (dc->out->flags & TEGRA_DC_OUT_NVHDCP_POLICY_ON_DEMAND) {
 644                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
 645                         TEGRA_NVHDCP_POLICY_ON_DEMAND);
 646         } else {
 647                 tegra_nvhdcp_set_policy(hdmi->nvhdcp,
 648                         TEGRA_NVHDCP_POLICY_ALWAYS_ON);
 649         }
 650         return 0;
 651
 652 err_edid_destroy:
 653         tegra_edid_destroy(hdmi->edid);
 654 err_free_irq:
 655         disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
 656         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 657 err_put_clock:
 658         if (!IS_ERR_OR_NULL(disp2_clk))
 659                 clk_put(disp2_clk);
 660         if (!IS_ERR_OR_NULL(disp1_clk))
 661                 clk_put(disp1_clk);
 662         if (!IS_ERR_OR_NULL(clk))
 663                 clk_put(clk);
 664 err_iounmap_reg:
 665         iounmap(base);
 666 err_release_resource_reg:
 667         release_resource(base_res);
 668 err_free_hdmi:
 669         kfree(hdmi);
 670         return err;
 671 }
 672
 673 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
 674 {
 675         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 676
 677         disable_irq_wake(gpio_to_irq(dc->out->hotplug_gpio));
 678         free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
 679         cancel_delayed_work_sync(&hdmi->work);
 680         switch_dev_unregister(&hdmi->hpd_switch);
 681         iounmap(hdmi->base);
 682         release_resource(hdmi->base_res);
 683         clk_put(hdmi->clk);
 684         clk_put(hdmi->disp1_clk);
 685         clk_put(hdmi->disp2_clk);
 686         tegra_edid_destroy(hdmi->edid);
 687         tegra_nvhdcp_destroy(hdmi->nvhdcp);
 688
 689         kfree(hdmi);
 690
 691 }
 692
 693 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
 694 {
 695         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 696         int i;
 697         unsigned freqs[] = {
 698                 32000,
 699                 44100,
 700                 48000,
 701                 88200,
 702                 96000,
 703                 176400,
 704                 192000,
 705         };
 706
 707         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
 708                 unsigned f = freqs[i];
 709                 unsigned eight_half;
 710                 unsigned delta;;
 711
 712                 if (f > 96000)
 713                         delta = 2;
 714                 else if (f > 48000)
 715                         delta = 6;
 716                 else
 717                         delta = 9;
 718
 719                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
 720                 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
 721                                   AUDIO_FS_HIGH(eight_half + delta),
 722                                   HDMI_NV_PDISP_AUDIO_FS(i));
 723         }
 724 }
 725
 726 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc)
 727 {
 728         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 729         const struct tegra_hdmi_audio_config *config;
 730         unsigned long audio_n;
 731         unsigned audio_freq = 44100; /* TODO: find some way of configuring this */
 732
 733         tegra_hdmi_writel(hdmi,
 734                           AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
 735                           AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
 736                           AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
 737                           HDMI_NV_PDISP_AUDIO_CNTRL0);
 738
 739         config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
 740         if (!config) {
 741                 dev_err(&dc->ndev->dev,
 742                         "hdmi: can't set audio to %d at %d pix_clock",
 743                         audio_freq, dc->mode.pclk);
 744                 return -EINVAL;
 745         }
 746
 747         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
 748
 749         audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
 750                 AUDIO_N_VALUE(config->n - 1);
 751         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 752
 753         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
 754                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
 755
 756         tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
 757                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
 758
 759         tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
 760                           SPARE_CTS_RESET_VAL(1),
 761                           HDMI_NV_PDISP_HDMI_SPARE);
 762
 763         audio_n &= ~AUDIO_N_RESETF;
 764         tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
 765
 766         tegra_dc_hdmi_setup_audio_fs_tables(dc);
 767
 768         return 0;
 769 }
 770
 771 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
 772                                          u8 type, u8 version, void *data, int len)
 773 {
 774         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 775         u32 subpack[2];  /* extra byte for zero padding of subpack */
 776         int i;
 777         u8 csum;
 778
 779         /* first byte of data is the checksum */
 780         csum = type + version + len - 1;
 781         for (i = 1; i < len; i++)
 782                 csum +=((u8 *)data)[i];
 783         ((u8 *)data)[0] = 0x100 - csum;
 784
 785         tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
 786                           INFOFRAME_HEADER_VERSION(version) |
 787                           INFOFRAME_HEADER_LEN(len - 1),
 788                           header_reg);
 789
 790         /* The audio inforame only has one set of subpack registers.  The hdmi
 791          * block pads the rest of the data as per the spec so we have to fixup
 792          * the length before filling in the subpacks.
 793          */
 794         if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
 795                 len = 6;
 796
 797         /* each subpack 7 bytes devided into:
 798          *   subpack_low - bytes 0 - 3
 799          *   subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
 800          */
 801         for (i = 0; i < len; i++) {
 802                 int subpack_idx = i % 7;
 803
 804                 if (subpack_idx == 0)
 805                         memset(subpack, 0x0, sizeof(subpack));
 806
 807                 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
 808
 809                 if (subpack_idx == 6 || (i + 1 == len)) {
 810                         int reg = header_reg + 1 + (i / 7) * 2;
 811
 812                         tegra_hdmi_writel(hdmi, subpack[0], reg);
 813                         tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
 814                 }
 815         }
 816 }
 817
 818 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
 819 {
 820         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 821         struct hdmi_avi_infoframe avi;
 822
 823         if (dvi) {
 824                 tegra_hdmi_writel(hdmi, 0x0,
 825                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 826                 return;
 827         }
 828
 829         memset(&avi, 0x0, sizeof(avi));
 830
 831         avi.r = HDMI_AVI_R_SAME;
 832
 833         if (dc->mode.v_active == 480) {
 834                 if (dc->mode.h_active == 640) {
 835                         avi.m = HDMI_AVI_M_4_3;
 836                         avi.vic = 1;
 837                 } else {
 838                         avi.m = HDMI_AVI_M_16_9;
 839                         avi.vic = 3;
 840                 }
 841         } else if (dc->mode.v_active == 576) {
 842                 /* CEC modes 17 and 18 differ only by the pysical size of the
 843                  * screen so we have to calculation the physical aspect
 844                  * ratio.  4 * 10 / 3  is 13
 845                  */
 846                 if ((dc->out->h_size * 10) / dc->out->v_size > 14) {
 847                         avi.m = HDMI_AVI_M_16_9;
 848                         avi.vic = 18;
 849                 } else {
 850                         avi.m = HDMI_AVI_M_16_9;
 851                         avi.vic = 17;
 852                 }
 853         } else if (dc->mode.v_active == 720) {
 854                 avi.m = HDMI_AVI_M_16_9;
 855                 if (dc->mode.h_front_porch == 110)
 856                         avi.vic = 4; /* 60 Hz */
 857                 else
 858                         avi.vic = 19; /* 50 Hz */
 859         } else if (dc->mode.v_active == 1080) {
 860                 avi.m = HDMI_AVI_M_16_9;
 861                 if (dc->mode.h_front_porch == 88)
 862                         avi.vic = 16; /* 60 Hz */
 863                 else if (dc->mode.h_front_porch == 528)
 864                         avi.vic = 31; /* 50 Hz */
 865                 else
 866                         avi.vic = 32; /* 24 Hz */
 867         } else {
 868                 avi.m = HDMI_AVI_M_16_9;
 869                 avi.vic = 0;
 870         }
 871
 872
 873         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
 874                                      HDMI_INFOFRAME_TYPE_AVI,
 875                                      HDMI_AVI_VERSION,
 876                                      &avi, sizeof(avi));
 877
 878         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 879                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
 880 }
 881
 882 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
 883 {
 884         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 885         struct hdmi_audio_infoframe audio;
 886
 887         if (dvi) {
 888                 tegra_hdmi_writel(hdmi, 0x0,
 889                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 890                 return;
 891         }
 892
 893         memset(&audio, 0x0, sizeof(audio));
 894
 895         audio.cc = HDMI_AUDIO_CC_2;
 896         tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
 897                                      HDMI_INFOFRAME_TYPE_AUDIO,
 898                                      HDMI_AUDIO_VERSION,
 899                                      &audio, sizeof(audio));
 900
 901         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
 902                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
 903 }
 904
 905 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
 906 {
 907         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
 908         int pulse_start;
 909         int dispclk_div_8_2;
 910         int pll0;
 911         int pll1;
 912         int ds;
 913         int retries;
 914         int rekey;
 915         int err;
 916         unsigned long val;
 917
 918         /* enbale power, clocks, resets, etc. */
 919
 920         /* The upstream DC needs to be clocked for accesses to HDMI to not
 921          * hard lock the system.  Because we don't know if HDMI is conencted
 922          * to disp1 or disp2 we need to enable both until we set the DC mux.
 923          */
 924         clk_enable(hdmi->disp1_clk);
 925         clk_enable(hdmi->disp2_clk);
 926         tegra_dc_setup_clk(dc, hdmi->clk);
 927         clk_set_rate(hdmi->clk, dc->mode.pclk);
 928
 929         clk_enable(hdmi->clk);
 930         tegra_periph_reset_assert(hdmi->clk);
 931         mdelay(1);
 932         tegra_periph_reset_deassert(hdmi->clk);
 933
 934         /* TODO: copy HDCP keys from KFUSE to HDMI */
 935
 936         /* Program display timing registers: handled by dc */
 937
 938         /* program HDMI registers and SOR sequencer */
 939
 940         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
 941         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
 942                         DC_DISP_DISP_COLOR_CONTROL);
 943
 944         /* video_preamble uses h_pulse2 */
 945         pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
 946                 dc->mode.h_back_porch - 10;
 947         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
 948         tegra_dc_writel(dc,
 949                         PULSE_MODE_NORMAL |
 950                         PULSE_POLARITY_HIGH |
 951                         PULSE_QUAL_VACTIVE |
 952                         PULSE_LAST_END_A,
 953                         DC_DISP_H_PULSE2_CONTROL);
 954         tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
 955                   DC_DISP_H_PULSE2_POSITION_A);
 956
 957         tegra_hdmi_writel(hdmi,
 958                           VSYNC_WINDOW_END(0x210) |
 959                           VSYNC_WINDOW_START(0x200) |
 960                           VSYNC_WINDOW_ENABLE,
 961                           HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
 962
 963         tegra_hdmi_writel(hdmi,
 964                           (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
 965                           ARM_VIDEO_RANGE_LIMITED,
 966                           HDMI_NV_PDISP_INPUT_CONTROL);
 967
 968         clk_disable(hdmi->disp1_clk);
 969         clk_disable(hdmi->disp2_clk);
 970
 971         dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
 972         tegra_hdmi_writel(hdmi,
 973                           SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
 974                           SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
 975                           HDMI_NV_PDISP_SOR_REFCLK);
 976
 977
 978         if (!hdmi->dvi) {
 979                 err = tegra_dc_hdmi_setup_audio(dc);
 980
 981                 if (err < 0)
 982                         hdmi->dvi = true;
 983         }
 984
 985         rekey = HDMI_REKEY_DEFAULT;
 986         val = HDMI_CTRL_REKEY(rekey);
 987         val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
 988                                         dc->mode.h_back_porch +
 989                                         dc->mode.h_front_porch -
 990                                         rekey - 18) / 32);
 991         if (!hdmi->dvi)
 992                 val |= HDMI_CTRL_ENABLE;
 993         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
 994
 995         if (hdmi->dvi)
 996                 tegra_hdmi_writel(hdmi, 0x0,
 997                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
 998         else
 999                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
1000                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
1001
1002
1003         tegra_dc_hdmi_setup_avi_infoframe(dc, hdmi->dvi);
1004         tegra_dc_hdmi_setup_audio_infoframe(dc, hdmi->dvi);
1005
1006         /* TMDS CONFIG */
1007         pll0 = 0x200033f;
1008         pll1 = 0;
1009
1010         pll0 &= ~SOR_PLL_PWR & ~SOR_PLL_VCOPD & ~SOR_PLL_PDBG & ~SOR_PLL_PDPORT & ~SOR_PLL_PULLDOWN &
1011                 ~SOR_PLL_VCOCAP(~0) & ~SOR_PLL_ICHPMP(~0);
1012         pll0 |= SOR_PLL_RESISTORSEL;
1013
1014         if (dc->mode.pclk <= 27000000)
1015                 pll0 |= SOR_PLL_VCOCAP(0);
1016         else if (dc->mode.pclk <= 74250000)
1017                 pll0 |= SOR_PLL_VCOCAP(1);
1018         else
1019                 pll0 |= SOR_PLL_VCOCAP(3);
1020
1021         if (dc->mode.h_active == 1080) {
1022                 pll0 |= SOR_PLL_ICHPMP(1) | SOR_PLL_TX_REG_LOAD(3) |
1023                         SOR_PLL_TX_REG_LOAD(3) | SOR_PLL_BG_V17_S(3);
1024                 pll1 |= SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN;
1025         } else {
1026                 pll0 |= SOR_PLL_ICHPMP(2);
1027         }
1028
1029         tegra_hdmi_writel(hdmi, pll0, HDMI_NV_PDISP_SOR_PLL0);
1030         tegra_hdmi_writel(hdmi, pll1, HDMI_NV_PDISP_SOR_PLL1);
1031
1032         if (pll1 & SOR_PLL_PE_EN) {
1033                 tegra_hdmi_writel(hdmi,
1034                                   PE_CURRENT0(0xf) |
1035                                   PE_CURRENT1(0xf) |
1036                                   PE_CURRENT2(0xf) |
1037                                   PE_CURRENT3(0xf),
1038                                   HDMI_NV_PDISP_PE_CURRENT);
1039         }
1040
1041         /* enable SOR */
1042         if (dc->mode.h_active == 1080)
1043                 ds = DRIVE_CURRENT_13_500_mA;
1044         else
1045                 ds = DRIVE_CURRENT_5_250_mA;
1046
1047         tegra_hdmi_writel(hdmi,
1048                           DRIVE_CURRENT_LANE0(ds) |
1049                           DRIVE_CURRENT_LANE1(ds) |
1050                           DRIVE_CURRENT_LANE2(ds) |
1051                           DRIVE_CURRENT_LANE3(ds) |
1052                           DRIVE_CURRENT_FUSE_OVERRIDE,
1053                           HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1054
1055         tegra_hdmi_writel(hdmi,
1056                           SOR_SEQ_CTL_PU_PC(0) |
1057                           SOR_SEQ_PU_PC_ALT(0) |
1058                           SOR_SEQ_PD_PC(8) |
1059                           SOR_SEQ_PD_PC_ALT(8),
1060                           HDMI_NV_PDISP_SOR_SEQ_CTL);
1061
1062         val = SOR_SEQ_INST_WAIT_TIME(1) |
1063                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1064                 SOR_SEQ_INST_HALT |
1065                 SOR_SEQ_INST_PIN_A_LOW |
1066                 SOR_SEQ_INST_PIN_B_LOW |
1067                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1068
1069         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
1070         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
1071
1072         val = 0x1c800;
1073         val &= ~SOR_CSTM_ROTCLK(~0);
1074         val |= SOR_CSTM_ROTCLK(2);
1075         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
1076
1077
1078         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1079         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1080         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1081
1082
1083         /* start SOR */
1084         tegra_hdmi_writel(hdmi,
1085                           SOR_PWR_NORMAL_STATE_PU |
1086                           SOR_PWR_NORMAL_START_NORMAL |
1087                           SOR_PWR_SAFE_STATE_PD |
1088                           SOR_PWR_SETTING_NEW_TRIGGER,
1089                           HDMI_NV_PDISP_SOR_PWR);
1090         tegra_hdmi_writel(hdmi,
1091                           SOR_PWR_NORMAL_STATE_PU |
1092                           SOR_PWR_NORMAL_START_NORMAL |
1093                           SOR_PWR_SAFE_STATE_PD |
1094                           SOR_PWR_SETTING_NEW_DONE,
1095                           HDMI_NV_PDISP_SOR_PWR);
1096
1097         retries = 1000;
1098         do {
1099                 BUG_ON(--retries < 0);
1100                 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1101         } while (val & SOR_PWR_SETTING_NEW_PENDING);
1102
1103         val = SOR_STATE_ASY_CRCMODE_COMPLETE |
1104                 SOR_STATE_ASY_OWNER_HEAD0 |
1105                 SOR_STATE_ASY_SUBOWNER_BOTH |
1106                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1107                 SOR_STATE_ASY_DEPOL_POS;
1108
1109         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_H_SYNC)
1110                 val |= SOR_STATE_ASY_HSYNCPOL_NEG;
1111         else
1112                 val |= SOR_STATE_ASY_HSYNCPOL_POS;
1113
1114         if (dc->mode.flags & TEGRA_DC_MODE_FLAG_NEG_V_SYNC)
1115                 val |= SOR_STATE_ASY_VSYNCPOL_NEG;
1116         else
1117                 val |= SOR_STATE_ASY_VSYNCPOL_POS;
1118
1119         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE2);
1120
1121         val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1122         tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
1123
1124         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1125         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1126         tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
1127                           HDMI_NV_PDISP_SOR_STATE1);
1128         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1129
1130         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1131
1132         tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1133                         PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1134                         DC_CMD_DISPLAY_POWER_CONTROL);
1135
1136         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1137         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1138         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1139
1140         if (!hdmi->dvi)
1141                 tegra_nvhdcp_set_plug(hdmi->nvhdcp, 1);
1142 }
1143
1144 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
1145 {
1146         struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1147
1148         tegra_nvhdcp_set_plug(hdmi->nvhdcp, 0);
1149
1150         tegra_periph_reset_assert(hdmi->clk);
1151         clk_disable(hdmi->clk);
1152 }
1153
1154 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
1155         .init = tegra_dc_hdmi_init,
1156         .destroy = tegra_dc_hdmi_destroy,
1157         .enable = tegra_dc_hdmi_enable,
1158         .disable = tegra_dc_hdmi_disable,
1159         .detect = tegra_dc_hdmi_detect,
1160         .suspend = tegra_dc_hdmi_suspend,
1161         .resume = tegra_dc_hdmi_resume,
1162 };
1163