2 * drivers/video/tegra/dc/hdmi.c
4 * Copyright (C) 2010 Google, Inc.
5 * Author: Erik Gilling <konkers@android.com>
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/err.h>
22 #include <linux/gpio.h>
23 #include <linux/interrupt.h>
24 #include <linux/kernel.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/switch.h>
28 #include <linux/workqueue.h>
33 #include <mach/nvhost.h>
41 /* datasheet claims this will always be 216MHz */
42 #define HDMI_AUDIOCLK_FREQ 216000000
44 #define HDMI_REKEY_DEFAULT 56
46 struct tegra_dc_hdmi_data {
48 struct tegra_edid *edid;
49 struct delayed_work work;
51 struct resource *base_res;
55 struct clk *disp1_clk;
56 struct clk *disp2_clk;
58 struct switch_dev hpd_switch;
60 spinlock_t suspend_lock;
65 const struct fb_videomode tegra_dc_hdmi_supported_modes[] = {
66 /* 1280x720p 60hz: EIA/CEA-861-B Format 4 */
70 .pixclock = KHZ2PICOS(74250),
71 .hsync_len = 40, /* h_sync_width */
72 .vsync_len = 5, /* v_sync_width */
73 .left_margin = 220, /* h_back_porch */
74 .upper_margin = 20, /* v_back_porch */
75 .right_margin = 110, /* h_front_porch */
76 .lower_margin = 5, /* v_front_porch */
77 .vmode = FB_VMODE_NONINTERLACED,
78 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
81 /* 720x480p 59.94hz: EIA/CEA-861-B Formats 2 & 3 */
85 .pixclock = KHZ2PICOS(27000),
86 .hsync_len = 62, /* h_sync_width */
87 .vsync_len = 6, /* v_sync_width */
88 .left_margin = 60, /* h_back_porch */
89 .upper_margin = 30, /* v_back_porch */
90 .right_margin = 16, /* h_front_porch */
91 .lower_margin = 9, /* v_front_porch */
92 .vmode = FB_VMODE_NONINTERLACED,
93 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
96 /* 640x480p 60hz: EIA/CEA-861-B Format 1 */
100 .pixclock = KHZ2PICOS(25200),
101 .hsync_len = 96, /* h_sync_width */
102 .vsync_len = 2, /* v_sync_width */
103 .left_margin = 48, /* h_back_porch */
104 .upper_margin = 33, /* v_back_porch */
105 .right_margin = 16, /* h_front_porch */
106 .lower_margin = 10, /* v_front_porch */
107 .vmode = FB_VMODE_NONINTERLACED,
108 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
111 /* 720x576p 50hz EIA/CEA-861-B Formats 17 & 18 */
115 .pixclock = KHZ2PICOS(27000),
116 .hsync_len = 64, /* h_sync_width */
117 .vsync_len = 5, /* v_sync_width */
118 .left_margin = 68, /* h_back_porch */
119 .upper_margin = 39, /* v_back_porch */
120 .right_margin = 12, /* h_front_porch */
121 .lower_margin = 5, /* v_front_porch */
122 .vmode = FB_VMODE_NONINTERLACED,
123 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
126 /* 1920x1080p 59.94/60hz EIA/CEA-861-B Format 16 */
130 .pixclock = KHZ2PICOS(148500),
131 .hsync_len = 44, /* h_sync_width */
132 .vsync_len = 5, /* v_sync_width */
133 .left_margin = 148, /* h_back_porch */
134 .upper_margin = 36, /* v_back_porch */
135 .right_margin = 88, /* h_front_porch */
136 .lower_margin = 4, /* v_front_porch */
137 .vmode = FB_VMODE_NONINTERLACED,
138 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
142 struct tegra_hdmi_audio_config {
148 const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
149 {25200000, 4096, 25250},
150 {27000000, 4096, 27000},
151 {54000000, 4096, 54000},
152 {74250000, 4096, 74250},
153 {148500000, 4096, 148500},
157 const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
158 {25200000, 14112, 63125},
159 {27000000, 6272, 30000},
160 {54000000, 6272, 60000},
161 {74250000, 6272, 82500},
162 {148500000, 6272, 165000},
166 const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
167 {25200000, 6144, 25250},
168 {27000000, 6144, 27000},
169 {54000000, 6144, 54000},
170 {74250000, 6144, 74250},
171 {148500000, 6144, 148500},
175 static const struct tegra_hdmi_audio_config
176 *tegra_hdmi_get_audio_config(unsigned audio_freq, unsigned pix_clock)
178 const struct tegra_hdmi_audio_config *table;
180 switch (audio_freq) {
182 table = tegra_hdmi_audio_32k;
186 table = tegra_hdmi_audio_44_1k;
190 table = tegra_hdmi_audio_48k;
197 while (table->pix_clock) {
198 if (table->pix_clock == pix_clock)
207 static inline unsigned long tegra_hdmi_readl(struct tegra_dc_hdmi_data *hdmi,
210 return readl(hdmi->base + reg * 4);
213 static inline void tegra_hdmi_writel(struct tegra_dc_hdmi_data *hdmi,
214 unsigned long val, unsigned long reg)
216 writel(val, hdmi->base + reg * 4);
219 static inline void tegra_hdmi_clrsetbits(struct tegra_dc_hdmi_data *hdmi,
220 unsigned long reg, unsigned long clr,
223 unsigned long val = tegra_hdmi_readl(hdmi, reg);
226 tegra_hdmi_writel(hdmi, val, reg);
229 #define DUMP_REG(a) do { \
230 printk("HDMI %-32s\t%03x\t%08lx\n", \
231 #a, a, tegra_hdmi_readl(hdmi, a)); \
235 static void hdmi_dumpregs(struct tegra_dc_hdmi_data *hdmi)
237 DUMP_REG(HDMI_CTXSW);
238 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
239 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
240 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
241 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
242 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
243 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
244 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
245 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
246 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
247 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
248 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
249 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
250 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
251 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
252 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
253 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
254 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
255 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
256 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
257 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
258 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
259 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
260 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
261 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
262 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
263 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
264 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
265 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
266 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
267 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
268 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
269 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
270 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
271 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
272 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
273 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
274 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
275 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
276 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
277 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
278 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
279 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
280 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
281 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
282 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
283 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
284 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
285 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
286 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
287 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
288 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
289 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
290 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
291 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
292 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
293 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
294 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
295 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
296 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
297 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
298 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
299 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
300 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
301 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
302 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
303 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
304 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
305 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
306 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
307 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
308 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
309 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
310 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
311 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
312 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
313 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
314 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
315 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
316 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
317 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
318 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
319 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_CTRL);
320 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
321 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
322 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
323 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
324 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
325 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
326 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
327 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
328 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
329 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
330 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
331 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
332 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST0);
333 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST1);
334 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST2);
335 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST3);
336 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST4);
337 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST5);
338 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST6);
339 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST7);
340 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST8);
341 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST9);
342 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTA);
343 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTB);
344 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTC);
345 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTD);
346 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTE);
347 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INSTF);
348 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
349 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
350 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
351 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
352 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
353 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
354 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
355 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
356 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
357 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
358 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
359 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
360 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
361 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
362 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
363 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
364 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
365 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
366 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
367 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
368 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
369 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
370 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
371 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
372 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
373 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
374 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
375 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
376 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
377 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
378 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
379 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
380 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
381 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
382 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
383 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
384 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
385 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
386 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
387 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
388 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
389 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
390 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
394 #define PIXCLOCK_TOLERANCE 200
396 static bool tegra_dc_hdmi_mode_equal(const struct fb_videomode *mode1,
397 const struct fb_videomode *mode2)
399 return mode1->xres == mode2->xres &&
400 mode1->yres == mode2->yres &&
401 mode1->vmode == mode2->vmode;
404 static bool tegra_dc_hdmi_mode_filter(struct fb_videomode *mode)
409 for (i = 0; i < ARRAY_SIZE(tegra_dc_hdmi_supported_modes); i++) {
410 if (tegra_dc_hdmi_mode_equal(&tegra_dc_hdmi_supported_modes[i],
412 memcpy(mode, &tegra_dc_hdmi_supported_modes[i], sizeof(*mode));
413 mode->flag = FB_MODE_IS_DETAILED;
414 clocks = (mode->left_margin + mode->xres + mode->right_margin + mode->hsync_len) *
415 (mode->upper_margin + mode->yres + mode->lower_margin + mode->vsync_len);
416 mode->refresh = (PICOS2KHZ(mode->pixclock) * 1000) / clocks;
425 static bool tegra_dc_hdmi_hpd(struct tegra_dc *dc)
430 level = gpio_get_value(dc->out->hotplug_gpio);
432 sense = dc->out->flags & TEGRA_DC_OUT_HOTPLUG_MASK;
434 return (sense == TEGRA_DC_OUT_HOTPLUG_HIGH && level) ||
435 (sense == TEGRA_DC_OUT_HOTPLUG_LOW && !level);
438 static bool tegra_dc_hdmi_detect(struct tegra_dc *dc)
440 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
441 struct fb_monspecs specs;
444 if (!tegra_dc_hdmi_hpd(dc))
447 err = tegra_edid_get_monspecs(hdmi->edid, &specs);
449 dev_err(&dc->ndev->dev, "error reading edid\n");
453 /* monitors like to lie about these but they are still useful for
454 * detecting aspect ratios
456 dc->out->h_size = specs.max_x * 1000;
457 dc->out->v_size = specs.max_y * 1000;
459 tegra_fb_update_monspecs(dc->fb, &specs, tegra_dc_hdmi_mode_filter);
460 switch_set_state(&hdmi->hpd_switch, 1);
461 dev_info(&dc->ndev->dev, "display detected\n");
465 switch_set_state(&hdmi->hpd_switch, 0);
470 static void tegra_dc_hdmi_detect_worker(struct work_struct *work)
472 struct tegra_dc_hdmi_data *hdmi =
473 container_of(to_delayed_work(work), struct tegra_dc_hdmi_data, work);
474 struct tegra_dc *dc = hdmi->dc;
476 if (!tegra_dc_hdmi_detect(dc)) {
477 tegra_dc_disable(dc);
478 tegra_fb_update_monspecs(dc->fb, NULL, NULL);
482 static irqreturn_t tegra_dc_hdmi_irq(int irq, void *ptr)
484 struct tegra_dc *dc = ptr;
485 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
488 spin_lock_irqsave(&hdmi->suspend_lock, flags);
489 if (hdmi->suspended) {
490 hdmi->hpd_pending = true;
492 if (tegra_dc_hdmi_hpd(dc))
493 schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
495 schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
497 spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
502 static void tegra_dc_hdmi_suspend(struct tegra_dc *dc)
504 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
507 spin_lock_irqsave(&hdmi->suspend_lock, flags);
508 hdmi->suspended = true;
509 spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
512 static void tegra_dc_hdmi_resume(struct tegra_dc *dc)
514 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
517 spin_lock_irqsave(&hdmi->suspend_lock, flags);
518 hdmi->suspended = false;
519 if (hdmi->hpd_pending) {
520 if (tegra_dc_hdmi_hpd(dc))
521 schedule_delayed_work(&hdmi->work, msecs_to_jiffies(100));
523 schedule_delayed_work(&hdmi->work, msecs_to_jiffies(0));
524 hdmi->hpd_pending = false;
526 spin_unlock_irqrestore(&hdmi->suspend_lock, flags);
529 static int tegra_dc_hdmi_init(struct tegra_dc *dc)
531 struct tegra_dc_hdmi_data *hdmi;
532 struct resource *res;
533 struct resource *base_res;
535 struct clk *clk = NULL;
536 struct clk *disp1_clk = NULL;
537 struct clk *disp2_clk = NULL;
540 hdmi = kzalloc(sizeof(*hdmi), GFP_KERNEL);
544 res = nvhost_get_resource_byname(dc->ndev, IORESOURCE_MEM, "hdmi_regs");
546 dev_err(&dc->ndev->dev, "hdmi: no mem resource\n");
551 base_res = request_mem_region(res->start, resource_size(res), dc->ndev->name);
553 dev_err(&dc->ndev->dev, "hdmi: request_mem_region failed\n");
558 base = ioremap(res->start, resource_size(res));
560 dev_err(&dc->ndev->dev, "hdmi: registers can't be mapped\n");
562 goto err_release_resource_reg;
565 clk = clk_get(&dc->ndev->dev, "hdmi");
566 if (IS_ERR_OR_NULL(clk)) {
567 dev_err(&dc->ndev->dev, "hdmi: can't get clock\n");
569 goto err_iounmap_reg;
572 disp1_clk = clk_get_sys("tegradc.0", NULL);
573 if (IS_ERR_OR_NULL(disp1_clk)) {
574 dev_err(&dc->ndev->dev, "hdmi: can't disp1 clock\n");
579 disp2_clk = clk_get_sys("tegradc.1", NULL);
580 if (IS_ERR_OR_NULL(disp2_clk)) {
581 dev_err(&dc->ndev->dev, "hdmi: can't disp2 clock\n");
586 /* TODO: support non-hotplug */
587 if (request_irq(gpio_to_irq(dc->out->hotplug_gpio), tegra_dc_hdmi_irq,
588 IRQF_DISABLED | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
589 dev_name(&dc->ndev->dev), dc)) {
590 dev_err(&dc->ndev->dev, "hdmi: request_irq %d failed\n",
591 gpio_to_irq(dc->out->hotplug_gpio));
596 hdmi->edid = tegra_edid_create(dc->out->dcc_bus);
597 if (IS_ERR_OR_NULL(hdmi->edid)) {
598 dev_err(&dc->ndev->dev, "hdmi: can't create edid\n");
599 err = PTR_ERR(hdmi->edid);
603 INIT_DELAYED_WORK(&hdmi->work, tegra_dc_hdmi_detect_worker);
607 hdmi->base_res = base_res;
609 hdmi->disp1_clk = disp1_clk;
610 hdmi->disp2_clk = disp2_clk;
611 hdmi->suspended = false;
612 hdmi->hpd_pending = false;
613 spin_lock_init(&hdmi->suspend_lock);
615 hdmi->hpd_switch.name = "hdmi";
616 switch_dev_register(&hdmi->hpd_switch);
620 tegra_dc_set_outdata(dc, hdmi);
625 free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
627 if (!IS_ERR_OR_NULL(disp2_clk))
629 if (!IS_ERR_OR_NULL(disp1_clk))
631 if (!IS_ERR_OR_NULL(clk))
635 err_release_resource_reg:
636 release_resource(base_res);
642 static void tegra_dc_hdmi_destroy(struct tegra_dc *dc)
644 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
646 free_irq(gpio_to_irq(dc->out->hotplug_gpio), dc);
647 cancel_delayed_work_sync(&hdmi->work);
648 switch_dev_unregister(&hdmi->hpd_switch);
650 release_resource(hdmi->base_res);
652 clk_put(hdmi->disp1_clk);
653 clk_put(hdmi->disp2_clk);
654 tegra_edid_destroy(hdmi->edid);
660 static void tegra_dc_hdmi_setup_audio_fs_tables(struct tegra_dc *dc)
662 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
674 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
675 unsigned f = freqs[i];
686 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
687 tegra_hdmi_writel(hdmi, AUDIO_FS_LOW(eight_half - delta) |
688 AUDIO_FS_HIGH(eight_half + delta),
689 HDMI_NV_PDISP_AUDIO_FS(i));
693 static int tegra_dc_hdmi_setup_audio(struct tegra_dc *dc)
695 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
696 const struct tegra_hdmi_audio_config *config;
697 unsigned long audio_n;
698 unsigned audio_freq = 44100; /* TODO: find some way of configuring this */
700 tegra_hdmi_writel(hdmi,
701 AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
702 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
703 AUDIO_CNTRL0_SOURCE_SELECT_AUTO,
704 HDMI_NV_PDISP_AUDIO_CNTRL0);
706 config = tegra_hdmi_get_audio_config(audio_freq, dc->mode.pclk);
708 dev_err(&dc->ndev->dev,
709 "hdmi: can't set audio to %d at %d pix_clock",
710 audio_freq, dc->mode.pclk);
714 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
716 audio_n = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNALTE |
717 AUDIO_N_VALUE(config->n - 1);
718 tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
720 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
721 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
723 tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config->cts),
724 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
726 tegra_hdmi_writel(hdmi, SPARE_HW_CTS | SPARE_FORCE_SW_CTS |
727 SPARE_CTS_RESET_VAL(1),
728 HDMI_NV_PDISP_HDMI_SPARE);
730 audio_n &= ~AUDIO_N_RESETF;
731 tegra_hdmi_writel(hdmi, audio_n, HDMI_NV_PDISP_AUDIO_N);
733 tegra_dc_hdmi_setup_audio_fs_tables(dc);
738 static void tegra_dc_hdmi_write_infopack(struct tegra_dc *dc, int header_reg,
739 u8 type, u8 version, void *data, int len)
741 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
742 u32 subpack[2]; /* extra byte for zero padding of subpack */
746 /* first byte of data is the checksum */
747 csum = type + version + len - 1;
748 for (i = 1; i < len; i++)
749 csum +=((u8 *)data)[i];
750 ((u8 *)data)[0] = 0x100 - csum;
752 tegra_hdmi_writel(hdmi, INFOFRAME_HEADER_TYPE(type) |
753 INFOFRAME_HEADER_VERSION(version) |
754 INFOFRAME_HEADER_LEN(len - 1),
757 /* The audio inforame only has one set of subpack registers. The hdmi
758 * block pads the rest of the data as per the spec so we have to fixup
759 * the length before filling in the subpacks.
761 if (header_reg == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
764 /* each subpack 7 bytes devided into:
765 * subpack_low - bytes 0 - 3
766 * subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
768 for (i = 0; i < len; i++) {
769 int subpack_idx = i % 7;
771 if (subpack_idx == 0)
772 memset(subpack, 0x0, sizeof(subpack));
774 ((u8 *)subpack)[subpack_idx] = ((u8 *)data)[i];
776 if (subpack_idx == 6 || (i + 1 == len)) {
777 int reg = header_reg + 1 + (i / 7) * 2;
779 tegra_hdmi_writel(hdmi, subpack[0], reg);
780 tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
785 static void tegra_dc_hdmi_setup_avi_infoframe(struct tegra_dc *dc, bool dvi)
787 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
788 struct hdmi_avi_infoframe avi;
791 tegra_hdmi_writel(hdmi, 0x0,
792 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
796 memset(&avi, 0x0, sizeof(avi));
798 avi.r = HDMI_AVI_R_SAME;
800 if (dc->mode.v_active == 480) {
801 if (dc->mode.h_active == 640) {
802 avi.m = HDMI_AVI_M_4_3;
805 avi.m = HDMI_AVI_M_16_9;
808 } else if (dc->mode.v_active == 576) {
809 /* CEC modes 17 and 18 differ only by the pysical size of the
810 * screen so we have to calculation the physical aspect
811 * ratio. 4 * 10 / 3 is 13
813 if ((dc->out->h_size * 10) / dc->out->v_size > 14) {
814 avi.m = HDMI_AVI_M_16_9;
817 avi.m = HDMI_AVI_M_16_9;
820 } else if (dc->mode.v_active == 720) {
821 avi.m = HDMI_AVI_M_16_9;
822 if (dc->mode.h_front_porch == 110)
823 avi.vic = 4; /* 60 Hz */
825 avi.vic = 19; /* 50 Hz */
826 } else if (dc->mode.v_active == 720) {
827 avi.m = HDMI_AVI_M_16_9;
828 if (dc->mode.h_front_porch == 88)
829 avi.vic = 16; /* 60 Hz */
830 else if (dc->mode.h_front_porch == 528)
831 avi.vic = 31; /* 50 Hz */
833 avi.vic = 32; /* 24 Hz */
835 avi.m = HDMI_AVI_M_16_9;
840 tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
841 HDMI_INFOFRAME_TYPE_AVI,
845 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
846 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
849 static void tegra_dc_hdmi_setup_audio_infoframe(struct tegra_dc *dc, bool dvi)
851 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
852 struct hdmi_audio_infoframe audio;
855 tegra_hdmi_writel(hdmi, 0x0,
856 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
860 memset(&audio, 0x0, sizeof(audio));
862 audio.cc = HDMI_AUDIO_CC_2;
863 tegra_dc_hdmi_write_infopack(dc, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
864 HDMI_INFOFRAME_TYPE_AUDIO,
866 &audio, sizeof(audio));
868 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
869 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
872 static void tegra_dc_hdmi_enable(struct tegra_dc *dc)
874 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
886 /* enbale power, clocks, resets, etc. */
888 /* The upstream DC needs to be clocked for accesses to HDMI to not
889 * hard lock the system. Because we don't know if HDMI is conencted
890 * to disp1 or disp2 we need to enable both until we set the DC mux.
892 clk_enable(hdmi->disp1_clk);
893 clk_enable(hdmi->disp2_clk);
894 tegra_dc_setup_clk(dc, hdmi->clk);
895 clk_set_rate(hdmi->clk, dc->mode.pclk);
897 clk_enable(hdmi->clk);
898 tegra_periph_reset_assert(hdmi->clk);
900 tegra_periph_reset_deassert(hdmi->clk);
902 /* TODO: copy HDCP keys from KFUSE to HDMI */
904 /* Program display timing registers: handled by dc */
906 /* program HDMI registers and SOR sequencer */
908 tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
909 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
910 DC_DISP_DISP_COLOR_CONTROL);
912 /* video_preamble uses h_pulse2 */
913 pulse_start = dc->mode.h_ref_to_sync + dc->mode.h_sync_width +
914 dc->mode.h_back_porch - 10;
915 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
918 PULSE_POLARITY_HIGH |
921 DC_DISP_H_PULSE2_CONTROL);
922 tegra_dc_writel(dc, PULSE_START(pulse_start) | PULSE_END(pulse_start + 8),
923 DC_DISP_H_PULSE2_POSITION_A);
925 tegra_hdmi_writel(hdmi,
926 VSYNC_WINDOW_END(0x210) |
927 VSYNC_WINDOW_START(0x200) |
929 HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
931 tegra_hdmi_writel(hdmi,
932 (dc->ndev->id ? HDMI_SRC_DISPLAYB : HDMI_SRC_DISPLAYA) |
933 ARM_VIDEO_RANGE_LIMITED,
934 HDMI_NV_PDISP_INPUT_CONTROL);
936 clk_disable(hdmi->disp1_clk);
937 clk_disable(hdmi->disp2_clk);
939 dispclk_div_8_2 = clk_get_rate(hdmi->clk) / 1000000 * 4;
940 tegra_hdmi_writel(hdmi,
941 SOR_REFCLK_DIV_INT(dispclk_div_8_2 >> 2) |
942 SOR_REFCLK_DIV_FRAC(dispclk_div_8_2),
943 HDMI_NV_PDISP_SOR_REFCLK);
945 err = tegra_dc_hdmi_setup_audio(dc);
949 rekey = HDMI_REKEY_DEFAULT;
950 val = HDMI_CTRL_REKEY(rekey);
951 val |= HDMI_CTRL_MAX_AC_PACKET((dc->mode.h_sync_width +
952 dc->mode.h_back_porch +
953 dc->mode.h_front_porch -
956 val |= HDMI_CTRL_ENABLE;
957 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_HDMI_CTRL);
960 tegra_hdmi_writel(hdmi, 0x0,
961 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
963 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
964 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
967 tegra_dc_hdmi_setup_avi_infoframe(dc, dvi);
968 tegra_dc_hdmi_setup_audio_infoframe(dc, dvi);
974 pll0 &= ~SOR_PLL_PWR & ~SOR_PLL_VCOPD & ~SOR_PLL_PDBG & ~SOR_PLL_PDPORT & ~SOR_PLL_PULLDOWN &
975 ~SOR_PLL_VCOCAP(~0) & ~SOR_PLL_ICHPMP(~0);
976 pll0 |= SOR_PLL_RESISTORSEL;
978 if (dc->mode.pclk <= 27000000)
979 pll0 |= SOR_PLL_VCOCAP(0);
980 else if (dc->mode.pclk <= 74250000)
981 pll0 |= SOR_PLL_VCOCAP(1);
983 pll0 |= SOR_PLL_VCOCAP(3);
985 if (dc->mode.h_active == 1080) {
986 pll0 |= SOR_PLL_ICHPMP(1) | SOR_PLL_TX_REG_LOAD(3) |
987 SOR_PLL_TX_REG_LOAD(3) | SOR_PLL_BG_V17_S(3);
988 pll1 |= SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN;
990 pll0 |= SOR_PLL_ICHPMP(2);
993 tegra_hdmi_writel(hdmi, pll0, HDMI_NV_PDISP_SOR_PLL0);
994 tegra_hdmi_writel(hdmi, pll1, HDMI_NV_PDISP_SOR_PLL1);
996 if (pll1 & SOR_PLL_PE_EN) {
997 tegra_hdmi_writel(hdmi,
1002 HDMI_NV_PDISP_PE_CURRENT);
1006 if (dc->mode.h_active == 1080)
1007 ds = DRIVE_CURRENT_13_500_mA;
1009 ds = DRIVE_CURRENT_5_250_mA;
1011 tegra_hdmi_writel(hdmi,
1012 DRIVE_CURRENT_LANE0(ds) |
1013 DRIVE_CURRENT_LANE1(ds) |
1014 DRIVE_CURRENT_LANE2(ds) |
1015 DRIVE_CURRENT_LANE3(ds) |
1016 DRIVE_CURRENT_FUSE_OVERRIDE,
1017 HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1019 tegra_hdmi_writel(hdmi,
1020 SOR_SEQ_CTL_PU_PC(0) |
1021 SOR_SEQ_PU_PC_ALT(0) |
1023 SOR_SEQ_PD_PC_ALT(8),
1024 HDMI_NV_PDISP_SOR_SEQ_CTL);
1026 val = SOR_SEQ_INST_WAIT_TIME(1) |
1027 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1029 SOR_SEQ_INST_PIN_A_LOW |
1030 SOR_SEQ_INST_PIN_B_LOW |
1031 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1033 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST0);
1034 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_SEQ_INST8);
1037 val &= ~SOR_CSTM_ROTCLK(~0);
1038 val |= SOR_CSTM_ROTCLK(2);
1039 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_CSTM);
1042 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
1043 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1044 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1048 tegra_hdmi_writel(hdmi,
1049 SOR_PWR_NORMAL_STATE_PU |
1050 SOR_PWR_NORMAL_START_NORMAL |
1051 SOR_PWR_SAFE_STATE_PD |
1052 SOR_PWR_SETTING_NEW_TRIGGER,
1053 HDMI_NV_PDISP_SOR_PWR);
1054 tegra_hdmi_writel(hdmi,
1055 SOR_PWR_NORMAL_STATE_PU |
1056 SOR_PWR_NORMAL_START_NORMAL |
1057 SOR_PWR_SAFE_STATE_PD |
1058 SOR_PWR_SETTING_NEW_DONE,
1059 HDMI_NV_PDISP_SOR_PWR);
1063 BUG_ON(--retries < 0);
1064 val = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1065 } while (val & SOR_PWR_SETTING_NEW_PENDING);
1067 tegra_hdmi_writel(hdmi,
1068 SOR_STATE_ASY_CRCMODE_COMPLETE |
1069 SOR_STATE_ASY_OWNER_HEAD0 |
1070 SOR_STATE_ASY_SUBOWNER_BOTH |
1071 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1072 /* TODO: to look at hsync polarity */
1073 SOR_STATE_ASY_HSYNCPOL_POS |
1074 SOR_STATE_ASY_VSYNCPOL_POS |
1075 SOR_STATE_ASY_DEPOL_POS,
1076 HDMI_NV_PDISP_SOR_STATE2);
1078 val = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1079 tegra_hdmi_writel(hdmi, val, HDMI_NV_PDISP_SOR_STATE1);
1081 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1082 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1083 tegra_hdmi_writel(hdmi, val | SOR_STATE_ATTACHED,
1084 HDMI_NV_PDISP_SOR_STATE1);
1085 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1087 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
1089 tegra_dc_writel(dc, PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1090 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE,
1091 DC_CMD_DISPLAY_POWER_CONTROL);
1093 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1094 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1095 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1098 static void tegra_dc_hdmi_disable(struct tegra_dc *dc)
1100 struct tegra_dc_hdmi_data *hdmi = tegra_dc_get_outdata(dc);
1102 tegra_periph_reset_assert(hdmi->clk);
1103 clk_disable(hdmi->clk);
1105 struct tegra_dc_out_ops tegra_dc_hdmi_ops = {
1106 .init = tegra_dc_hdmi_init,
1107 .destroy = tegra_dc_hdmi_destroy,
1108 .enable = tegra_dc_hdmi_enable,
1109 .disable = tegra_dc_hdmi_disable,
1110 .detect = tegra_dc_hdmi_detect,
1111 .suspend = tegra_dc_hdmi_suspend,
1112 .resume = tegra_dc_hdmi_resume,